JP3394887B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOSFET formed on a silicon substrate.

[0002]

2. Description of the Related Art Generally, a MOSFET (Metal O
xide Semiconductor Field
The Effect Transistor) is formed on the silicon wafer 10 as shown in FIG. That is, the gate electrode 21 is formed in a predetermined region of the wafer 10, and the source region 22 and the drain region 23 are formed on the wafer so as to sandwich the gate electrode 21 (see FIG. 8). It is known that in such a MOSFET, if the flatness of the surface of the wafer is high, that is, if the surface roughness is small, good electrical characteristics can be obtained.

However, even if the surface of the wafer is flattened to the limit, since the crystals are lined up, roughness at the atomic level occurs. In addition, in order to prevent crystal defects from occurring on the wafer surface, a silicon wafer generally has a surface inclined at an angle (called an off-angle) with respect to a stacked crystal surface (for example, a crystal surface having a plane index (100)). It is configured to be the wafer surface. Therefore, steps 15 and terraces 16 as shown in FIG. 9 occur on the surface of the silicon wafer.

[0004]

[Problems to be Solved by the Invention]
MOS on a silicon wafer with a terrace structure on the surface
When an FET is formed, carriers moving from the source region to the drain region on the wafer surface under the gate electrode during the operation of the transistor are more likely to collide with steps as shown in FIG. Therefore, there is a problem that the mobility of carriers is lowered and the MOSFET cannot operate at high speed.

The present invention has been made in consideration of the above circumstances, and even if a MOSFET is formed on a wafer having a step-terrace structure on its surface, it is possible to obtain a MOSFET whose operating speed is as fast as possible. An object is to provide a possible semiconductor device.

[0006]

A first aspect of a semiconductor device according to the present invention has a MOSFET formed on a step of a silicon substrate, and an extension direction of the step on the surface of the silicon substrate under the gate electrode of the MOSFET. And the MO
When the angle formed by the direction of carriers flowing from the source region to the drain region of the SFET is θ, the gate length of the gate electrode is L, and the terrace length on the surface of the silicon substrate is d, L / d ≦ | k / Sin θ | (-90 ° ≦ θ ≦ 90 °,
It is characterized by satisfying k ≦ 5).

A second aspect of the semiconductor device according to the present invention is a MOSFE formed on a step of a silicon substrate.
T, the angle formed by the extension direction of the step on the surface of the silicon substrate under the gate electrode of the MOSFET and the direction of carrier flow from the source region to the drain region of the MOSFET is θ, and the gate length of the gate electrode is L , L / d ≦ | k / sin θ | (−2 ° ≦ θ ≦ 2 °, k>, where d is the length of the terrace on the surface of the silicon substrate.
5) is satisfied.

A third aspect of the semiconductor device according to the present invention is a MOSFE formed on a step of a silicon substrate.
The gate insulating film and the gate electrode of this MOSFET are formed so as to extend over at least the above steps. An epitaxial wafer or a wafer annealed in an inert gas or a reducing gas at 1100 ° C. or higher may be used as the silicon substrate.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS.

The present inventors have conducted the following experiment, assuming that there is some relation between the number of steps under the gate electrode of the MOSFET and the mobility of the MOSFET.

First, the off angle is 0.03 degrees and 0.0.
Five types of silicon wafers, which are attached at 7 degrees, 0.15 degrees, 0.25 degrees, and 0.3 degrees, are prepared. Then, the following process is performed to form a step-terrace structure on these wafers. These wafers are annealed in a hydrogen atmosphere, for example, at 1200 ° C. for 1 hour. Then A
Annealing is performed in an r atmosphere at 1200 ° C. for 1 hour. Then, CVD (Chemical Vapor D
A 5 μm epilayer is grown on each wafer using the Eposition method. After that, a step-terrace structure is formed on the wafer surface by performing wet cleaning.

As shown in FIG. 3, the angle formed by the orientation flat 11 of the wafer 10 and the direction in which the carriers of the MOSFET flow with respect to each of the five types of wafers having the step-terrace structure thus formed. ψ (also called azimuth angle ψ) is 0 degrees, ± 2 degrees, ± 20
A plurality of N-channel MOSFETs having the same dimensions of ± 40 degrees, ± 60 degrees, ± 80 degrees, and 90 degrees are formed. At this time, each N-channel MOSFET
Has a channel length L of 1 μm, a channel width W of 25 μm, a threshold voltage Vth of 0.8 V, and a gate oxide film thickness Tox of 150 angstrom.

The above-mentioned azimuth angle ψ is the extension direction of step 15 on the wafer surface and the MOSFET shown in FIG.
It becomes equal to the angle θ formed by the carrier flow direction 25 of 20 carriers. 5, 6 and 7 show MOSFETs when θ is −60 degrees, 0 degrees and 90 degrees.

Generally, when the off angle is changed, the terrace 16
The length d of is changed. Observing the terrace length d of the surface under the gate electrode of the MOSFET formed on five types of wafers having different off angles as described above with an atomic force microscope, the off angle α was 0.03 degrees and 0.07 degrees. Every time,
Gate length d for 0.15 degrees, 0.25 degrees, and 0.3 degrees
Are about 200 nm, 100 nm, 50 nm and 30 n, respectively.
m and 25 nm. The step height h was about 0.12 to 0.13 nm in the monatomic step.

The relationship between the terrace length d of the silicon wafer surface and the off-angle α is expressed as h = d · tan α, where h is the step height. The theoretical value of the step height h is 0.13 nm for the monatomic step and 0.27 for the diatomic step.
nm, which is in agreement with the above observation result.

Using this step height h, the off angle α is 0.03 °, 0.07 °, 0.15 °, 0.2.
Calculation of the terrace lengths at 5 degrees and 0.3 degrees agreed with the observation results using the atomic force microscope described above.

This means that the step-terrace structure is M
It is shown that after the OSFET is formed, it remains on the surface under the gate electrode.

A conventional MOSFE of the dimensions described above.
T mobility mu of the Id = μ · A · (V G -Vth) 2 obtained by using the following equation, becomes ^{μ = 150cm 2 / V · sec} . Here, V _G was 5 V and Id was 0.4 mA.

In the above equation, Id is drain current, V
_G represents the gate voltage, Vth represents the threshold voltage, and A is represented by A = 0.5 · (W · ε _ox ) / (L · Tox). Here, W is the channel width, L is the channel length, Tox is the thickness of the gate oxide film, and ε _ox is the dielectric constant of the gate oxide film (3.8 [F / m]).

A plurality of MOSFEs formed as described above
The mobility μ of T is actually obtained, the abscissa represents the angle θ (the angle formed by the extension direction of the step and the carrier flow direction of the MOSFET), and the ordinate represents the ratio L / of the gate length L and the step length d. When d is taken and the obtained mobility μ is equal to or larger than the conventional value, that is, when μ ≧ 150 cm ² / V · sec, it is indicated by ○, and when μ <150 cm ² / V · sec is indicated by ×. The displayed experimental results are shown in FIG. It should be noted that this experimental result shows that when θ is negative (for example, −2 degrees, −20 degrees, −40 degrees,
In the case of -60 degrees and -80 degrees), since it coincides with the positive case, only the positive part is displayed.

FIG. 1 also shows graphs g ₁ , g ₂ and g ₃ of the curve L / d = k / sin θ when k is 5, 4, and 6.

As can be seen from FIG. 1, if L / d and θ are in the region under the graph g ₁ (k = 5), performance equivalent to that of the conventional MOS transistor can be obtained.

This indicates that good performance can be obtained if the number of steps (= K) under the gate electrode between the source region and the drain region is 5 or less. This is because, as can be seen from FIG. 4, the apparent terrace length d'is d '= d
Since it is represented by sin θ, the number of steps in the gate length L is substantially L / d ′.

Even if k> 5, θ is −2 to
Within the range of 2 °, the mobility μ is μ ≧ 150 cm ²
It can be seen from Fig. 1 that / Vsec is obtained.

FIG. 2 is a graph showing the test yield relating to the number of steps in the gate and the mobility at θ = 90 degrees. From this result, if L / d ≦ 5, L /
Good performance was obtained as compared with d> 5.

In the above experiment, the step-terrace structure was obtained by epitaxial growth, but a similar step-terrace structure can be obtained by annealing at 1100 ° C. or higher in a reducing or inert gas atmosphere. Was given.

Needless to say, the present invention can be applied to devices having gates on steps other than the above embodiments, such as IGBTs.

[0028]

As described above, according to the present invention, it is possible to obtain a MOSFET having an operation speed as fast as possible even when formed on a wafer having a step-terrace structure on its surface.

[Brief description of drawings]

FIG. 1 is a graph illustrating the effects of the present invention.

FIG. 2 is a graph illustrating the function and effect of the present invention when the angle θ is 90 degrees.

FIG. 3 is a diagram illustrating an azimuth angle ψ.

FIG. 4 is an explanatory diagram for explaining an angle formed between a direction in which a step extends and a direction in which a carrier of a MOSFET flows.

FIG. 5 is a configuration diagram of a MOSFET when θ is −60 degrees.

FIG. 6 is a configuration diagram of a MOSFET when θ is 0 degrees.

FIG. 7 is a configuration diagram of a MOSFET when θ is 90 degrees.

FIG. 8 is a configuration diagram of a conventional MOSFET.

FIG. 9 is a schematic diagram illustrating a step-terrace structure.

[Explanation of symbols]

10 Silicon wafer 11 Orientation flat 15 steps 16 terraces 20 MOSFET 21 Gate electrode 22 Source area 23 Drain region

Front page continuation (72) Inventor Norihiko Tsuchiya 72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Kawasaki Plant (56) Reference JP-A-4-373177 (JP, A) JP-A-8- 264780 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (2)

(57) [Claims] 1. An M formed on a step of a silicon substrate.
The MOSFET has an OSFET, and the extension direction of the step on the surface of the silicon substrate under the gate electrode of the MOSFET and the MOSF.
The angle formed by the direction in which carriers flow from the source region to the drain region of ET is θ, the gate length of the gate electrode is L,
When the number of steps under the gate electrode is k and the length of the terrace on the surface of the silicon substrate is d, L / d ≦ | k / sin θ | (−90 ° ≦ θ <0 ° or 0 ° <θ A semiconductor device satisfying ≦ 90 °, k ≦ 5). 2. An M formed on a step of a silicon substrate.
The MOSFET has an OSFET, and the extension direction of the step on the surface of the silicon substrate under the gate electrode of the MOSFET and the MOSF.
The angle formed by the direction in which carriers flow from the source region to the drain region of ET is θ, the gate length of the gate electrode is L,
When the number of steps under the gate electrode is k and the terrace length on the surface of the silicon substrate is d, L / d ≦ | k / sin θ | (−2 ° ≦ θ <0 ° or 0
A semiconductor device satisfying the following condition: ° <θ ≦ 2 °, k> 5).