JP3394881B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device used as a charge pump circuit or the like.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has been remarkably improved. In a gigabit class semiconductor memory, hundreds of millions of semiconductor elements are included in one chip, and in a 64-bit microprocessor, several millions to 1,000s of chips are included in one chip. Ten thousand semiconductor devices will be integrated. The improvement in the degree of integration is achieved by the miniaturization of devices, and the MOS with a gate length of 0.1 micron or less
Transistors will be used.

In such a fine MOS transistor, deterioration of transistor characteristics due to generation of hot carriers and TDDB (Time Dependent Dielectric Breakdow).
Insulation film breakdown due to n) occurs. Further, in order to suppress the decrease in punch-through breakdown voltage due to the shortened channel length, if the impurity concentration in the substrate region and the channel region is increased, the junction breakdown voltage of the source and drain is reduced, and the reliability of the device is reduced.

In order to maintain the reliability of these fine elements, it is effective to lower the power supply voltage. That is, by weakening the horizontal electric field between the source and drain, generation of hot carriers is prevented, and by weakening the vertical electric field between the gate and the substrate, TDDB is prevented. Furthermore, by lowering the power supply voltage, between the source and substrate,
The reverse bias applied to the junction between the substrates is reduced to cope with the reduction in breakdown voltage.

Semiconductor memories and microprocessors are composed of memory cells for storing information and a large number of logic gates for performing logical operations. When the number of logic gates increases as the degree of integration increases, the power consumed by the semiconductor chip increases. When the power consumption increases, the life of the battery of portable information devices such as mobile phones, which has been remarkably popularized in recent years, becomes short, and the usability becomes poor. Therefore, with the spread of portable information devices, there is an increasing demand for semiconductor chips with low power consumption.

Generally, the power consumption P of a logic gate is P =
It is represented by CVdd ² f. Here, C is the sum of parasitic capacitance, intrinsic capacitance and wiring capacitance of the MOS transistor forming the logic gate, Vdd is the power supply voltage, and f is the operating frequency. Now, assuming that the operating frequency f is constant, in order to suppress power consumption, the capacity C may be reduced or the power supply voltage Vdd may be lowered. In order to reduce C, MOS that constitutes a logic circuit
It is effective to reduce the number of transistors or shorten the gate width of MOS transistors. Further, since the power consumption P is proportional to the square of the power supply voltage Vdd, lowering the power supply voltage is effective in reducing power consumption.

By the way, in semiconductor memories and microprocessors, a charge pump circuit is provided in a chip. This charge pump circuit is a circuit necessary for pumping up charges by using a clock and generating a desired voltage. For example, in dynamic memory, it is used for word line drive circuits and substrate bias generation circuits.
It is used in phase locked loop circuits in microprocessors.

FIG. 5 shows an example of a charge pump circuit that generates a voltage approximately twice the power supply voltage. M7
Is an NMOS transistor having a drain and a gate connected to a power supply (voltage Vdd), a source connected to a node N3, and a substrate (body) grounded (voltage Vss).
The drain and gate of M8 are connected to the node N3,
It is an NMOS transistor whose source is connected to the output (voltage Vout) and whose substrate is grounded (voltage Vss). M7
And M8 are bulk transistors formed on the same common conductive type substrate. Also, one end of C4 is the node N3.
And a clock Φ1 is input to the other end of the capacitor.

The operation of the charge pump circuit shown in FIG. 5 will be described below with reference to the timing chart of FIG.
6A to 6C, the clock Φ1 is at a high level (Vdd) at time t0 and at a low level (Vs at time t1).
s), when the voltage becomes high level again at time t2, the respective voltages VN3 and Vout of the node N3 and the output, and the respective threshold voltages Vth1 and Vth of the MOS transistors M7 and M8.
It shows the change of th2. Here, the clock Φ
It is assumed that a sufficient time has passed since 1 was input and the circuit operation at time t0 is in a stable state (Vout is Vdd or more).

When the clock Φ1 goes low at the time t1, the node N3 is capacitively coupled by the capacitor C4.
Potential VN3 of is decreased. Then, the voltage VN3 of the node N3
When (Vdd-Vth1) or less, the MOS transistor M7 becomes conductive, so that VN3 is clamped to (Vdd-Vth1). The substrate potential of the transistor M7 is Vss (= 0
V) and the source potential is VN3 (= Vdd-Vth1), the Vth1 becomes higher than the threshold voltage Vth0 when the back bias is not applied due to the back bias effect. At this time, since the output Vout is Vdd or more, MO
The S transistor M8 is non-conductive, and the output Vout does not change.

Next, when the clock Φ1 becomes high level at time t2, the potential VN3 of the node N3 rises due to capacitive coupling by the capacitor C4. At this time, since the MOS transistor M7 is non-conductive, the charge pumped to the node N3 does not flow to the power supply Vdd through the transistor M7. Here, the amplitude of the clock Φ1 is Vd
When the capacitance of the capacitor C4 is Cc4 and the parasitic capacitance of the node N3 is Cp3, the potential increase V1 of the node N3 and the potential VN3 of the node N3 are as follows: V1 = Vdd-.DELTA.V1 VN3 = Vdd-Vth1 + V1 = 2Vdd- (Vth1 + ΔV1) ΔV1 = Cp3 · Vdd / (Cc4 + Cp3). If there is no parasitic capacitance of the node N3, V1 = Vdd, but the potential VN3 of the node N3 is Vdd due to the parasitic capacitance.
By .DELTA.V1. Output potential Vout is (VN3-V
When it drops below th2), the MOS transistor M8 becomes conductive, so that Vout becomes (VN3−Vth2). The substrate potential of the MOS transistor M8 is Vss, and the source potential thereof is Vout.
Therefore, due to the back bias effect, the threshold Vth2
Becomes higher than the threshold value Vth0.

As described above, the output voltage Vout of the conventional charge pump circuit is: Vout = VN3−Vth2 = 2Vdd− (Vth1 + ΔV1 + Vth2), which is twice the desired voltage 2Vdd (Vth1 +
ΔV1 + Vth2).

It is necessary to lower the threshold voltage in order to prevent the logic gate from malfunctioning when the power supply voltage is lowered to secure the reliability of the element and reduce the power consumption.
As a result, the amount of decrease in the output Vout from the desired potential can be suppressed. However, the MOS transistor M
If the threshold voltage of 7 is lowered too much, the cutoff characteristic of M7 when the potential of the node N3 rises deteriorates, the pumped charge becomes a leak current and is discharged to the power supply, and the potential increase V1 of the node N3 decreases. Resulting in. Therefore, the threshold voltage cannot be lowered sufficiently, so that the efficiency of the pump is lowered when the power supply voltage is lowered. Also,
If the threshold voltage of the MOS transistor M8 is lowered too much, the MOS transistor M8 when the potential of the node N3 drops
Of the output terminal becomes a leak current and leaks to the node N3, resulting in a decrease in the output voltage Vout.

The parasitic capacitance of the node N3 is mainly MOS.
It is the sum of the junction capacitance on the source side of the transistor M7 and the junction capacitance on the drain side of the MOS transistor M8. In the case of a bulk transistor, the sum of the junction capacitance is the gate width 1
It is several fF per μm. Therefore, in order to reduce the voltage drop ΔV1 due to the parasitic capacitance, the capacitor C
Although it is necessary to increase the capacitance of No. 4, the layout area and power consumption increase.

As a concrete numerical example, Vdd = 3.3V,
Vth1 = 0.8V, Vth2 = 0.9V, Cp3 = 100f
Assuming that F and Cc4 = 1 pF, .DELTA.V1 = 0.3 (V) Vout = 2.3.3-0.8-0.3-0.9 = 4.6.
(V). Therefore, the desired voltage (2Vdd = 6.6V)
However, only about 70% of the voltage can be obtained. Also,
When the power supply voltage is reduced to 0.5V, even if the threshold voltages are set as low as Vth1 = 0.3V and Vth2 = 0.4V, ΔV1 = 0.05 (V) Vout = 2.0.5- 0.3-0.05-0.4 = 0.
25 (V), which is 25% of the desired voltage (2Vdd = 1.0V)
However, the efficiency is greatly reduced.

[0016]

As described above, in the conventional charge pump circuit, when the threshold voltage is lowered in order to lower the voltage, the leak current increases and the pump efficiency lowers. was there. Further, when a bulk transistor having a common substrate region is used, a large-capacity capacitor is required in order to prevent the efficiency of the pump from being lowered due to parasitic capacitance. As a result, there is a problem that the power consumption increases and the layout area increases.

A first object of the present invention is to control the threshold voltage of a MOS transistor so that the efficiency of the charge pump circuit can be improved. A second object of the present invention is to reduce the parasitic capacitance of the MOS transistor, so that a sufficient capacitance coupling ratio can be obtained even with a capacitor having a small capacitance, and the efficiency of the charge pump circuit can be improved. To do so.

[0018]

In a semiconductor integrated circuit device according to the present invention, a first conductivity type first M having a gate and a drain connected to a power supply section and a source connected to a first node.
An OS transistor, a second MOS transistor of a first conductivity type having a gate and a drain connected to the first node and a source connected to an output section, and the first node and the first clock supply section. the first capacitor and, possess a body potential controlling means for controlling the body potential and the body potential of the second MOS transistor of said first MOS transistor, the body potential controlling hand provided between
The stage includes a source and a drain of the first MOS transistor.
The potential boosted above the in potential is applied to the first MOS transistor.
It is characterized by including means for supplying to the body of the transistor .

[0019]

The body potential control means may be, for example, a third MOS transistor of the first conductivity type in which a gate, a drain and a body are connected to the power supply section and a source is connected to the body of the first MOS transistor. A fourth MOS transistor of the first conductivity type having a gate, a drain and a body connected to the body of the first MOS transistor and a source connected to the second node, and a source connected to the second node A fifth MOS transistor of the second conductivity type having a gate and a body connected to the body of the first MOS transistor and a drain connected to the body of the second MOS transistor; and a source connected to the power supply unit. The gate and body are the first MO
The drain is connected to the body of the S-transistor
A sixth MOS transistor of the first conductivity type connected to the body of the first MOS transistor, a second capacitor provided between the body of the first MOS transistor and a second clock supply section, The third capacitor is provided between the second node and the first clock supply section.

In this case, it is preferable that the clock supplied to the first clock supply section and the clock supplied to the second clock supply section have opposite phases.

According to the above invention, the body potential of each MOS transistor is controlled to increase the threshold voltage of the MOS transistor in the non-conducting state, and the MOS transistor in the conducting state.
By lowering the threshold voltage of the transistor (N
In the case of a MOS transistor, the reverse is true in the case of a PMOS transistor), and it is possible to obtain an efficient charge pump circuit with less decrease in output voltage.

Also, in the above invention, the first and second MOS transistors and the third to sixth MO transistors are also provided.
It is preferable that the S transistor is formed over a semiconductor layer (for example, over an SOI substrate) formed over the substrate with an insulating layer interposed therebetween.

By forming a MOS transistor on such a substrate, the body region of each transistor is separated for each transistor, so that the body potential of each transistor can be controlled for each transistor. The effects can be easily obtained. Also, MOS
Since the source / drain junction capacitance of a transistor can be made significantly smaller than that of a bulk transistor,
Even if the charge pump circuit is configured using a small capacity capacitor, a sufficient capacitance coupling ratio can be obtained, the efficiency of the charge pump circuit can be improved, and an increase in layout area and power consumption can be suppressed. be able to.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a basic configuration example of a charge pump circuit according to the present invention.

The drain and gate of M1 are connected to the power supply (voltage Vdd), the source is connected to the node N1, and the body is connected to the body potential control circuit CNT.
The transistor M2 is an NMOS transistor having a drain and a gate connected to the node N1, a source connected to the output (voltage Vout), and a body connected to the body potential control circuit CNT. The NMOS transistors M1 and M2 are formed using an SOI substrate or the like whose body region is separated for each transistor. C1 is a capacitor whose one end is connected to the node N1 and whose other end receives the clock Φ1.

The difference from the prior art shown in FIG.
The transistors M1 and M2 are transistors formed on an SOI substrate or the like, and the bodies of these transistors are connected to the body potential control circuit CNT.

FIG. 2 is a diagram showing a first specific structural example of the charge pump circuit according to the present invention. In this example, the body potentials of the NMOS transistors M1 and M2 are controlled by the gates of the NMOS transistors M1 and M2, respectively.

The clock Φ1 is low level (ground potential Vs
s), since the source of the transistor M1 is on the node N1 side, the body potential becomes a positive bias with respect to the source, and the threshold voltage of the transistor M1 is Vtho (threshold voltage when no back bias is applied). Will be lower. The source of the transistor M2 is also the node N1.
Since it is on the side, the body potential and the source potential are equal, and the threshold voltage of the transistor M2 is Vtho.

Clock Φ1 is at high level (power supply potential Vd
In the case of d), since the source of the transistor M1 is on the power supply Vdd side, the body potential and the source potential are equal, and the threshold voltage of the transistor M1 is Vtho. Since the source of the transistor M2 is on the output Vout side, the body potential has a positive bias with respect to the source, and the threshold voltage of the transistor M2 becomes lower than Vtho.

Therefore, the threshold voltages of the transistors M1 and M2 are both Vtho when not conducting,
When conducting, it becomes lower than Vtho. When the lowered threshold voltage is Vth3, the output voltage Vout is Vout = 2Vdd-2Vth3-ΔV2. Here, .DELTA.V2 is a voltage drop due to the parasitic capacitance of the node N1, and assuming that the parasitic capacitance of the node N1 is Cp1 and the capacitance of the capacitor C1 is Cc1, .DELTA.V2 = Cp1.Vdd / (Cc1 + Cp1).

Since the bottom surfaces of the source / drain of the transistor formed on the SOI substrate are covered with a thick oxide film, the junction capacitance is about 1/10 of that of the bulk transistor. Therefore, assuming that the parasitic capacitance Cp1 of the node N1 is 10 fF which is 1/10 of the parasitic capacitance of the node N3 in the prior art shown in FIG. 5 and the capacitance Cc1 of the capacitor C1 is 1 pF, Vdd = 0.5V and Vtho = 0.2V , Vth3 = 0.
ΔV2 and Vout at 1 V are ΔV2 = 0.005 (V) Vout = 2 · 0.5−2 · 0.1−0.005 = 0.7
It becomes 95 (V). Therefore, the efficiency of the pump is about 80%, which is a great increase compared to the case of using the conventional technique.

FIG. 3 is a diagram showing a second specific configuration example of the charge pump circuit according to the present invention. In the first specific configuration example shown in FIG. 2, in order to make Vth3 lower than Vtho, it is necessary to make the body-source voltage positive. Therefore, Vth3 needs to be higher than 0V. Therefore, the threshold voltage drop of the output cannot be eliminated. Therefore, in the second specific configuration example, a configuration that eliminates the threshold voltage drop of the output is adopted. That is, the threshold voltage when the NMOS transistors M1 and M2 are conductive is set to 0 V or less, and the threshold voltage when the NMOS transistors M1 and M2 are non-conductive is 0.
The body potential control circuit is configured to be higher than V.

M3 is an NMOS transistor whose drain, gate and body are connected to the power supply (voltage Vdd) and whose source is connected to the body B1 of the NMOS transistor M1. M4 is NM whose drain, gate and body are NM.
The NMOS transistor is connected to the body B1 of the OS transistor M1 and the source is connected to the node N2. M5 has a source connected to the node N2, a gate and a body connected to the body B1 of the NMOS transistor M1, and a drain connected to the drain. A PMOS transistor M6 connected to the body B2 of the NMOS transistor M2.
Is the body B2 of the drain of the NMOS transistor M2
, The gate and body are connected to the body B1 of the NMOS transistor M1, and the source is the power supply (voltage Vd
It is an NMOS transistor connected to d). MOS
The transistors M1 to M6 are formed using an SOI substrate or the like in which the body region is separated for each transistor.
C2 is a capacitor whose one end is connected to the body B1 of the transistor M1 and whose other end receives the clock Φ2,
C3 is a capacitor whose one end is connected to the node N2 and whose other end receives the clock Φ1.

The operation of the charge pump circuit shown in FIG. 3 will be described below with reference to the timing chart shown in FIG. In FIGS. 4A to 4D, the clock Φ1 is at time t.
In the case where the clock Φ2 is a high level (power supply potential Vdd) at 0, a low level (ground potential Vss) at time t1, and a high level again at time t2, and the clock Φ2 is an inverted signal (reverse-phase signal) of the clock Φ1, the node N1 and It shows changes in the potential of N2, the potentials of the bodies B1 and B2 of the transistors M1 and M2, the output potential Vout, and the threshold voltage of the transistors M1 and M2. In addition, here
Sufficient time has elapsed since the clocks Φ1 and Φ2 were input, and the circuit operation at time t0 is in a stable state (Vout is V
dd or more).

From time t0 to t1, since the clock Φ2 is at low level, Vth4 is set to the MOS transistor M3.
, The body B of the transistor M1
When the potential of 1 drops below (Vdd-Vth4), the transistor M3 becomes conductive, and the potential VB1 of the body B1 is clamped to VB1 = Vdd-Vth4.

When the clock Φ2 changes from the low level to the high level at the time t1, the potential VB1 of the body B1 rises to VB1 = 2Vdd− (Vth4 + ΔV3) due to the capacitive coupling by the capacitor C2. Here, ΔV3 is the amount of voltage drop due to the parasitic capacitance, and the capacitance of the capacitor C2 is Cc2 and the body B1 is
If the parasitic capacitance of Cpb1 is Cpb1, then ΔV3 = Cpb1.Vdd / (Cc2 + Cpb1).

At this time, since the clock Φ1 is at the low level, the node N1 is charged by the transistor M1. However, since the potential of the body B1 is higher than the source potential of the transistor M1, the threshold voltage Vth of the transistor M1.
1 becomes lower than Vtho (threshold voltage when no back bias is applied). Therefore, if the channel profile of the transistor M1 is set so that the threshold voltage at this time becomes 0 V or less, the potential VN1 of the node N1 is charged to VN1 = Vdd.

Further, since the clock Φ1 is at the low level, if Vth5 is the threshold voltage of the MOS transistor M4, the potential VN2 of the node N2 is charged to VN2 = 2Vdd− (Vth4 + ΔV3 + Vth5) through M4.

Since the transistor M5 is non-conductive and the transistor M6 is conductive, the potential VB2 of the body B2.
Becomes VB2 = Vdd. At this time, since the output potential Vout is higher than Vdd and the transistor M2 is non-conductive, Vout does not change.

Next, at time t2, Φ1 is high level, Φ2
Becomes low level, the potential VB1 of the body B1 is clamped to VB1 = Vdd-Vth4, and the potential of the node N1 rises to a value higher than Vdd due to capacitive coupling by the capacitor C1. At this time, since the transistor M1 is non-conductive, the node N1
The electric charge pumped to the power supply Vdd does not flow through the transistor M1 toward the power supply Vdd. Here, the capacitor C1
Is Cc1 and the parasitic capacitance of the node N1 is Cpn1, the potential increase V1 of the node N1 and the potential VN1 of the node N1 are as follows: ).

Further, since Φ1 is at the high level, the potential V of the node N2 is caused by the capacitive coupling by the capacitor C3.
N2 rises to VN2 = 3Vdd- (Vth4 + ΔV3 + Vth5 + ΔV4). ΔV4 is the potential drop due to parasitic capacitance,
When the capacitance of the capacitor C3 is Cc3 and the parasitic capacitance of the node N2 is Cpn2, ΔV4 = Cpn2Vdd / (Cc3 + Cpn2).

Since M5 is conducting and M6 is non-conducting, the potential of the body B2 becomes equal to VN2. Body B2
Is higher than Vout which is the source potential of the transistor M2, the threshold voltage Vth2 of the transistor M2 is lower than Vtho. Therefore, if the channel profile of the transistor M2 is set so that the threshold voltage at this time becomes 0 V or less, the output potential Vout is charged to Vout = 2Vdd-ΔV2.

Therefore, as in the case of the first specific configuration example, the junction capacitance of the transistor formed on the SOI substrate is set to about 1/10 of that of the bulk transistor, and the node N
Assuming that the parasitic capacitance Cpn1 of 1 is 10 fF and the capacitance Cc1 of the capacitor C1 is 1 pF, when the power supply voltage Vdd = 0.5 V, Vout = 2.0.5−0.005 = 0.995 (V), It is possible to obtain an output voltage that is substantially the same as the desired output voltage Vdd = 1.0 (V).

It is also possible to realize a charge pump circuit by combining the first and second specific structural examples. For example, the body of the transistor M1 may be controlled as in the first specific configuration example (FIG. 2) and the body of the transistor M2 may be controlled as in the second specific configuration example (FIG. 3). Second body of transistor M1
The specific configuration example (FIG. 3) and the body of the transistor M2 may be controlled as in the first specific configuration example (FIG. 2).

In the above embodiment, the transistor M
Although 1 to M4 and M6 are NMOS transistors and the transistor M5 is a PMOS transistor, conversely, the transistors M1 to M4 and M6 may be PMOS transistors and the transistor M5 may be an NMOS transistor. In addition, the present invention can be variously modified and implemented within a range not departing from the gist thereof.

[0047]

According to the present invention, by controlling the body potential of each MOS transistor, it is possible to obtain an efficient charge pump circuit with a small decrease in output voltage. Further, by forming each MOS transistor on the semiconductor layer (for example, on the SOI substrate) formed on the substrate via the insulating layer, the parasitic capacitance of the MOS transistor can be significantly reduced, and the charge pump circuit It is possible to further improve efficiency.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration example of a charge pump circuit according to the present invention.

FIG. 2 is a diagram showing a first specific configuration example of a charge pump circuit according to the present invention.

FIG. 3 is a diagram showing a second specific configuration example of the charge pump circuit according to the present invention.

FIG. 4 is a timing chart showing the operation of the charge pump circuit of FIG.

FIG. 5 is a diagram showing a configuration example of a charge pump circuit according to a conventional technique.

6 is a timing diagram showing the operation of the charge pump circuit of FIG.

[Explanation of symbols]

M1 ... First MOS transistor M2 ... second MOS transistor M3 ... Third MOS transistor M4 ... Fourth MOS transistor M5 ... Fifth MOS transistor M6 ... Sixth MOS transistor C1 ... first capacitor C2 ... second capacitor C3 ... Third capacitor N1 ... first node N2 ... second node

Claims (4)

(57) [Claims] 1. A first conductivity type first MOS transistor having a gate and a drain connected to a power supply section and a source connected to a first node; and a gate and a drain connected to the first MOS transistor.
A second MOS transistor of the first conductivity type, the source of which is connected to the node and the source of which is connected to the output section, and the first capacitor which is provided between the first node and the first clock supply section. A body potential control means for controlling a body potential of the first MOS transistor and a body potential of the second MOS transistor, wherein the body potential control means comprises the first MOS transistor.
Potential boosted higher than the source and drain potential
To supply the body of the first MOS transistor
A semiconductor integrated circuit device comprising a stage . 2. The third MOS transistor of the first conductivity type, wherein the body potential control means has a gate, a drain and a body connected to the power supply section and a source connected to the body of the first MOS transistor, A fourth MOS transistor of the first conductivity type having a gate, a drain and a body connected to the body of the first MOS transistor and a source connected to the second node; and a source connected to the second node and a gate And the body is connected to the body of the first MOS transistor and the drain is the second M
A fifth MOS transistor of the second conductivity type connected to the body of the OS transistor, a source connected to the power supply unit, a gate and a body connected to the body of the first MOS transistor, and a drain connected to the second MOS. Sixth MOS of the first conductivity type connected to the body of the transistor
A transistor, a second capacitor provided between the body of the first MOS transistor and a second clock supply section, and a second capacitor provided between the second node and the first clock supply section. The semiconductor integrated circuit device according to claim 1, further comprising a third capacitor. 3. The semiconductor integrated device according to claim 2, wherein the clocks supplied to the first clock supply unit and the clocks supplied to the second clock supply unit have opposite phases to each other. Circuit device. 4. The first and second MOS transistors are formed on a semiconductor layer formed on a substrate with an insulating layer interposed therebetween, according to any one of claims 1 to 3. Semiconductor integrated circuit device.