JP3388936B2 - AC discharge matrix type plasma display panel driving apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC discharge type matrix type plasma display panel driving apparatus and method.

[0002]

2. Description of the Related Art As is well known, a plasma display panel has been recently researched as one of thin secondary screen displays, and one of them is an AC discharge type matrix system having a memory function. Plasma display panels are known. FIG. 1 shows the configuration of a display device including such a plasma display panel.

Such a display device comprises a signal processing section A for processing a so-called composite video signal as an input signal, and a display section B for receiving a drive signal from the signal processing section A and displaying a two-dimensional screen. . In the signal processing unit A,
The A / D converter 3 converts the input composite video signal into, for example, 8-bit pixel data. On the other hand, the timing pulse generating circuit 2 generates various timing pulses based on the horizontal and vertical synchronizing signals extracted from the input composite video signal by the sync separating circuit 1. The A / D converter 3 operates in synchronization with these timing pulses. The memory control circuit 5 supplies write and read pulses synchronized with the timing pulse from the timing pulse generation circuit 2 to the frame memory 4 to sequentially read pixel data from the A / D converter 3 into the frame memory 4. To the output processing circuit 6 of the next stage.

The read timing signal generating circuit 7 generates a timing signal corresponding to the supply timing of the pixel data pulse and supplies it to the output processing circuit 6. Further, the read timing signal generation circuit 7 generates a write pulse for starting discharge light emission, a sustain pulse for maintaining the discharge state, and an erase pulse for stopping discharge light emission to generate these as row electrode drive pulses. It is supplied to the generation circuit 10.

The output processing circuit 6 supplies the pixel data to the pixel data pulse generating circuit 12 in synchronization with the timing signal from the read timing signal generating circuit 7. The plasma display panel 11 has column electrodes D1, D2, D3.
..... Dm-1, Dm orthogonal to such column electrodes and x
And y pair of row electrodes x1, x2, x3 forming one row.
, X4 ... Xn and y1, y2, y3, y4 ... Yn-1
, Yn. These column electrode and row electrode pairs face each other with a dielectric (not shown) in between to form a pixel cell.

The pixel data pulse generation circuit 12 generates a pixel data pulse corresponding to each pixel data supplied from the output processing circuit 6 and applies it to the column electrodes D1 to Dm. On the other hand, the row electrode drive pulse generation circuit 10 generates a wall charge in response to the timing pulse from the read timing signal generation circuit 7 for stable operation of the plasma display panel 11 and has a high voltage level. The row electrodes x1 to x of the plasma display panel 11
Apply to n. Next, the read timing signal generation circuit 7
A write pulse for selecting whether to emit light is applied to the row electrodes x1 to xn of the plasma display panel 11 in response to the pixel data supplied in response to the timing signal from. Further, the row electrode drive pulse generating circuit 10 generates a sustain pulse having a potential for maintaining a light emitting state based on the written data in response to the timing signal from the read timing signal generating circuit 6 to generate a plasma display panel. 11 row electrodes y1 to yn and row electrodes x1 to
Apply to xn respectively. At this time, sustain pulses are applied to the x and y electrodes at mutually shifted timings.

Next, the driving operation of the plasma display panel 11 having such a configuration will be described with reference to FIG. Prior to the display on the plasma display panel 11, the row electrode drive pulse generation circuit 10 applies a wall charge generation pulse CP to each of the row electrodes y1 to yn at the same timing at time t ₀ in order to generate wall charges in each cell. To apply. Next, the pixel data pulse generation circuit 12 sets the time t ₁
At, a positive pixel data pulse corresponding to the pixel data in each row is applied to the column electrodes D1 to Dm.

In the figure, at time t ₁ , the write pulse SP and the pixel data pulse are simultaneously applied to the first row electrode y 1. At this time, since the cells have wall charges in advance, if the potential difference between the write pulse SP and the pixel data pulse generated by the wall charges exceeds the discharge start voltage of the cells, the discharge is performed in the first row. Light emission occurs. Then, the row electrode driving pulse generating circuit 10 applies a negative sustain pulse IA of the respective row electrodes x1 to Xn same timing, i.e., at time t _2. Further, the row electrode drive pulse generation circuit 10 applies the sustain pulse IB having the negative polarity to each of the row electrodes y1 to yn at the same timing.

Here, at time t _{0 as} described above, discharge occurs when the potential difference due to the wall charge generation pulse exceeds the discharge start voltage in the cell, and the charge generated by this discharge is on the boundary between the dielectric and the electrode. Remain to form wall charges. Since this wall charge exists in the dielectric, the discharge can be performed again by applying a voltage lower than the above-mentioned discharge starting voltage. Therefore, after the discharge light emission is started and ended by the application of the write pulse SP and the pixel data pulse, the discharge light emission is generated again in the first row by the sustain pulse IA applied to the x electrode at time t ₂ . .
At this time, this re-discharge also ends instantly, but at time t
_The sustain pulse IB applied to the y ₁ electrode at ₃ again causes discharge light emission in the first row. Since such an operation is repeatedly executed until the light emission is erased as shown in the figure, discharge is repeatedly generated and the light emitting state of the pixel is maintained.

[0010]

In order to stabilize the display operation, the plasma display panel 11 having the above-described structure is provided with discharge discharge for display on the panel 11 prior to the discharge emission.
A configuration is adopted in which a wall charge generation pulse CP that generates wall charges is applied to each cell in advance. However, since the voltage level of this wall charge generation pulse is higher than the voltage level of the light emission sustaining pulse, the cell is generated by applying the wall charge generation pulse to the row electrodes y1 to yn regardless of the target display. It may emit light, which is one of the causes for lowering the contrast of the plasma display panel 11.

In view of the above problems, an object of the present invention is to provide a driving device for an AC discharge type matrix type plasma display panel which suppresses discharge light emission of a cell by applying a preliminary discharge pulse including a wall charge generation pulse to the cell, and It is to provide the method.

[0012]

A driving device for an AC discharge type matrix type plasma display panel according to the present invention comprises:
A plurality of row electrodes extension length in pairs, covering the row electrode
To face the dielectric layer through the discharge space
A plurality of column electrodes extending in a direction orthogonal to the row electrodes, a plurality of switching current paths connected in parallel with each other and electrically connected to the row electrodes, and the switching current paths are individually controlled to perform switching. Driving an AC discharge type matrix type plasma display panel in which the switching current path has a row electrode drive pulse generating means including a controller for supplying a pre-discharge pulse, a display data writing pulse and a light emission sustaining pulse to the row electrode. In the device, the switching current path corresponding to the preliminary discharge pulse includes a current limiting element having a resistance value higher than the total resistance value of the switching current path for generating at least one of the write pulse and the light emission sustaining pulse. Is.

[0013]

When the preliminary discharge pulse is applied to the row electrode, the discharge current generated by the preliminary discharge pulse flows through the current limiting element included in the corresponding switching current path.
It is suppressed to a small amount.

[0014]

Embodiments of the present invention will be described with reference to FIGS. FIG. 3 shows a configuration of a display device 18 including a driving device according to the present invention and a plasma display panel driven by the driving device. Such a display device 1
8 has the same configuration as the conventional display device shown in FIG. 1 except for the read timing signal generating circuit 7a and the row electrode drive pulse generating circuit 10a. Note that, in FIG. 3, the components having the same reference numerals as those in FIG. 1 have the same functions as the components in FIG.

FIG. 4 is a configuration diagram showing the details of the plasma display panel 11, and reference numeral 20 denotes a plurality of pixel electrodes of an AC surface discharge type PDP having a three-electrode configuration driven by the driving device according to the present invention. Show. The pixel cell 20 includes a front glass substrate 22 and a rear glass substrate 24 made of transparent glass, which face each other in parallel with a gap of 100 to 200 μm therebetween, and extend in parallel to each other in the vertical direction of the rear substrate 24 and are adjacent to each other. A discharge space 28 is defined by the barrier ribs 26, 26 that are adjacent to each other.

The front substrate 22 serves as a display surface, and a plurality of row electrodes Xi, Yi (i = 1, 2, ..., N) are formed on the surface of the front substrate 22 facing the rear substrate 24, for example, ITO. And tin oxide (SnO) are formed by vapor deposition of tin oxide (SnO) and the like in a horizontal direction with a film thickness of about several hundreds of nm. In order to enhance the conductivity of the row electrodes Xi and Yi,
The metal bus electrodes αi and βi, which are narrower than the widths of the row electrodes Xi and Yi, are used as auxiliary electrodes for the row electrodes Xi and
It is formed in close contact with Yi. Further, two row electrodes Xi and Yi adjacent to each other are paired to form a row electrode pair (Xi, Yi
Yi). Next, a dielectric layer 30 having a film thickness of about 10 μm is formed so as to cover these row electrodes Xi and Yi, and magnesium oxide (M
A MgO layer 32 made of gO) is laminated to have a film thickness of approximately several hundred nm.

On the other hand, in the rear substrate 24, the front substrate 2
The partition wall 26 formed to maintain the gap between the two is formed by using, for example, a thick film printing technique, and the longitudinal direction is the row electrodes Xi, Y.
They extend in a direction orthogonal to i and are formed in parallel with each other so as to have a width of 50 μm and an interval of 300 μm, for example.
Further, the column electrodes Dj (j = 1,2, ..., m) made of, for example, aluminum (Al) or an aluminum alloy are arranged between the partition walls 26, 26 adjacent to each other in the extending direction of the row electrodes Xi, Yi. It is formed in a film thickness of about 100 nm in the orthogonal direction. This column electrode Dj is made of a metal having a high reflectance, such as Al or an Al alloy, and therefore has a wavelength band of 38.
It has a reflectance of 80% or more at 0 to 650 nm.
The column electrode Dj is not limited to Al or Al alloy, and can be made of an appropriate metal or alloy such as Cu or Au having high reflectance.

Further, a phosphor film 36 is formed as a light emitting layer with a film thickness of, for example, 10 to 30 μm while covering each column electrode Dj. As described above, each electrode Xi, Yi, Dj
The front substrate 22 and the rear substrate 24 on which the dielectric layer 30 and the light emitting layer 36 are formed are sealed to evacuate the discharge space 28, and the moisture on the surface of the MgO layer 32 is removed by baking. Next, the discharge space 28 is filled and sealed with a rare gas such as Ne.Xe gas or He.Xe gas.

In this way, the paired row electrodes Xi, Y are formed.
A unit light emitting region surrounded by i and a column electrode Dj orthogonal to the row electrode is defined as one pixel cell Pi, j,
In the pixel cell Pi, j, the phosphor is excited by the discharge between the electrodes Xi, Yi, Dj to emit light. That is, in each pixel cell, the start, maintenance and erasure of light emission of the pixel cell Pi, j are controlled by the voltage application between the electrodes Xi, Yi and Dj.

FIG. 5 shows a row electrode drive pulse generating circuit 10a for driving one pixel cell Pi, j and the generating circuit 10
The detailed configuration of the read timing signal generating circuit 7a for supplying various pulses to a is shown. In FIG. 5, one pixel cell Pi, j has a row electrode pair Xi, Yi and a column electrode Dj, the row electrode Xi is connected to a row electrode X drive unit 10x, and the row electrode Yi is a row electrode Y drive. Connected to the portion 10y, the column electrode D
j is connected to the pixel data pulse generation circuit 12.
The row electrode X and Y drive units 10x and 10y constitute a row electrode drive pulse generation circuit 10a.

The read timing signal generation circuit 7a includes a controller 42. The controller 42 has a wall charge generation pulse Pc for generating wall charges, a pixel data selection pulse (writing pulse) Pe for selecting pixel data, as a pulse for driving a pixel cell.
Sustaining pulse Ps for maintaining the discharge state of the pixel cell,
Also, an erase pulse Pk for stopping discharge light emission is generated and supplied to the row electrode drive pulse generation circuit 10a. The wall charge generation pulse Pc is the preliminary discharge pulse P.
It is one type of p.

As shown in FIG. 5, the row electrode X drive section 10x is formed by connecting a plurality of switching current paths Px1 to Px3, which include corresponding switches SWX1 to SWX3 in series, in parallel with each other. Such switch SW
Each of X1 to SWX 3 is switch-controlled by a command from the controller 42. Switching current path Px
1, a current limiting element 40a and a switch SWX1 are connected in series, and a negative first potential −Vr for generating wall charges is applied to a contact a of the switch SWX1 so that a contact of the switch SWX1. b is a current limiting element 40a
It is connected to the row electrode Xi via. Switch SWX
1 is closed in response to the wall charge generation pulse Pc supplied from the controller 42, and connects the potential -Vr to the row electrode Xi via the current limiting element 40a. Such current limiting element 40a preferably comprises a resistor having a resistance value R1.

In the switching current path Px2, a positive potential + Vs for maintaining discharge is applied to the contact a of the switch SWX2, and the contact b of the switch SWX3.
Are connected to the row electrodes Xi. The switch SWX2 is
It is closed in response to the sustain pulse Ps supplied from the controller 42 to connect the potential + Vs to the row electrode Xi.

In the switching current path Px3, the contact a of the switch SWX3 is connected to the GND potential, and the contact b of the switch SWX3 is connected to the row electrode Xi.
The switch SWX3 is the switch SWX1, SWX2.
Will be closed only when both are open at the same time,
A GND potential is applied to the row electrode Xi. On the other hand, the row electrode Y drive unit 10y is also configured in substantially the same manner as the row electrode X drive unit 10x, and is configured such that a plurality of switching current paths Py1 to Py4 each including a corresponding switch SWY1 to SWY4 in series are connected in parallel with each other. Has been done. Such switch S
Each of WY1 to SWY4 is switch-controlled by a command from the controller 42.

The switching current path Py1 is composed of a current limiting element 40b and a switch SWY1 connected in series, and a positive potential + Vr for generating a wall charge is applied to a contact point a of the switch SWY1. SWY
The contact b of No. 1 is connected to the row electrode Yi via the current limiting element 40b.
It is connected to the. The switch SWY1 is closed in response to the wall charge generation pulse Pc supplied from the controller 42, so that the potential Vr is applied to the row electrode Yi and the current limiting element 40b.
Applied through. Such current limiting element 40b preferably comprises a resistor having a resistance value R2.

In the switching current path Py2, a negative potential -Ve for selecting pixel data is applied to the contact a of the switch SWY2, and the contact b of the switch SWY2 is connected to the row electrode Yi. Switch SWX
2 is a selection pulse Pe supplied from the controller 42
To the row electrode Yi.

In the switching current path Py3, a positive potential + Vs for maintaining discharge is applied to the contact a of the switch SWY3, and the contact b of the switch SWY3.
Are directly connected to the row electrodes Yi. Switch SWY3
Is closed in response to the sustain pulse Ps supplied from the controller 42, and applies the potential + Vs to the row electrode Yi.

In the switching current path Py4, the contact a of the switch SWY4 is connected to the GND potential, and the contact b of the switch SWY4 is directly connected to the row electrode Xi. The switch SWY4 is the switch SWY1 to SWY.
It is closed only when all of Y3 are opened at the same time, and the GND potential is applied to the row electrode Xi. The pixel data pulse generation circuit 12 supplies a data signal having a level corresponding to the display of the pixel Pi, j to the column electrode Dj.

In this way, each pixel cell Pi, j (i = 1-n, j
= 1-m), the row electrode drive pulse generation circuit 10a and the read timing signal generation circuit 7a are configured as described above. When the current limiting elements 40a and 40b are resistors, the resistors preferably have a resistance value on the order of kΩ.

The operation of the above configuration will be described with reference to FIG. The pixel cell Pi, j is composed of a non-display section (A) including a reset section (a) of the pixel cell and a write section (b) to the next cell, a sustain discharge section (c) and a full erase section (d). Dynamic display is performed by repeating one subfield consisting of the display section (B).

In the section (a) of FIG. 6, no pixel data is supplied and the wall charge generation pulse Pc is applied to all the row electrodes Xi and Yi at time t1. At this time, switch S
Each of WX1 and SWY1 is closed, and the potential −Vr is applied to the row electrode Xi via the current limiting element 40a, and the potential + Vr is applied to the row electrode Yi via the current limiting element 40b. When the potential difference generated by the potential −Vr and the potential Vr applied between each row electrode pair exceeds the discharge start voltage, the cell starts discharge, and this discharge is instantaneously terminated.
The wall charges generated by the discharge remain in the dielectric layer.

Normally, due to the discharge of the cell caused by the application of the wall charge generation pulse Pc, the cell instantaneously emits light regardless of the display, and the emission brightness thereof has a substantially linear relationship with the amount of discharge current flowing by the discharge. ing. However, the discharge currents flowing through the switching current paths Px1 and Py1 by the discharge based on the wall charge generation pulse Pc are
Since it flows through the current limiting elements 40a, 40b connected in series with the cell, it is suppressed to a considerably small amount by such current limiting elements 40a, b. Therefore, since the discharge current is considerably smaller than the discharge current by the conventional wall charge generation pulse, the brightness of discharge light emission due to the application of the wall charge generation pulse is lower than that of the conventional plasma display panel. . Therefore, the contrast in the plasma display panel can be improved.

Next, in the section (b), the pixel data is supplied at time t2, the pixel data pulse Dp1 corresponding thereto is applied to the column electrode, and at the same time, the pixel data selection pulse Pe is applied to the row electrode Y1. Is applied. At this time, SW
When Y2 is closed and the potential -Ve is applied to the row electrode Y1, the data signal is selected by the row electrode Y1 according to the pixel data. That is, when the cell is made to emit light in the next section (c) according to the supplied data signal by the pixel data selection pulse (write pulse), the wall charge is maintained,
When the cell is made to emit no light in the next section (c), the wall charges are extinguished. In this way, the column electrodes Di and the row electrodes Y
Pixel data for display is sequentially written in the plasma display panel 11 by the corresponding pixel data pulse and pixel data selection pulse sequentially supplied to each i.

Next, in the section (c), the row electrode Xi
, Yi are alternately applied to the sustain pulse Ps to hold the pixel data written in the section (b). At this time, only the cells in which the wall charge is stored in the previous section (b) are applied with the sustain pulse, and the row electrode X is generated by the charge energy of the wall charge itself and the energy of the sustain pulse.
Discharge occurs between 1 and Y1 to cause the cell to emit light. On the other hand, in the cell in which the wall charges have been erased, the potential difference Vs generated in the cell only by the sustain pulse is lower than the discharge start voltage, so that the discharge is not generated in the cell, and therefore the cell does not emit light.

Next, when the erase pulse Pk is applied to all the row electrodes Yi at time t3, the light emission discharge of the cells is stopped, and all the pixel data written in the cells in the section (b) are erased. To be done. As described above, the driving device of the present invention generates wall charges in all the pixel cells in preparation for discharge light emission in the section (a), sequentially writes pixel data to each pixel cell in the section (b), and The cells are discharged and displayed based on the pixel data written in c), and display is performed in the interval (d).
The display is stopped at.

When the pixel device is driven by the driving device having the above structure, the application of the wall charge generation pulse is intended to generate the wall charge by the discharge, and is not intended for the discharge light emission of the pixel cell. Absent. Therefore, when a relatively high level wall charge generation pulse is applied, if the discharge current is suppressed to a small amount by causing a discharge current to flow in the current limiting element connected in series with the row electrode, discharge light emission irrelevant to display is generated. Since the brightness is kept low, it is possible to improve the contrast of the plasma display panel.

Although the current limiting elements 40a and 40b are configured by using resistors in the above-described embodiments, the present invention is not limited to resistors and any element having a function of limiting the amount of flowing current can be used. It can also be used as a limiting element. Further, by connecting the current limiting elements in series to the current paths Px1 and Py1, since the cell has a capacitive load, when the wall charge generation pulse is supplied to the current paths Px1 and Py1, the row electrodes Xi, The potential change appearing in each Yi has a waveform that rises gently.

[0038]

According to the driving apparatus of the present invention, the switching current path corresponding to the preliminary discharge pulse has a current limiting element having a resistance value higher than the total resistance value of the switching current path for generating the light emission sustaining pulse. Since the current amount due to the discharge generated by the application of the preliminary discharge pulse to the pixel cell is suppressed to a small amount by flowing through the current limiting element, the display light emission caused by the application of the pulse is The brightness of discharge light emission, which is irrelevant, is suppressed low, and the contrast of the plasma display panel is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a display device including a plasma display panel.

FIG. 2 is a diagram showing operation waveforms of a conventional plasma display panel driving device.

FIG. 3 is a configuration diagram showing an embodiment of a display device including a plasma display panel to which the present invention is applied.

FIG. 4 is an exploded perspective view of pixel cells forming a plasma display panel driven by the driving device of the present invention.

FIG. 5 is a configuration diagram showing an embodiment of a driving device according to the present invention.

6 is a diagram showing operation waveforms by the driving device shown in FIG.

[Explanation of symbols]

Xi, Yi row electrode Dj column electrode Px1 to Px3, Py1 to Py4 switching current path 10a row electrode driving pulse generating circuit 11 as row electrode driving pulse generating means 11 plasma display panel 40a, 40b current limiting element 42 controller

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/66 101 G09G 3/28

Claims (6)

(57) [Claims] A plurality of row electrodes extension length at an 1. A pair of the dielectric layer which covers said row electrode, opposite to the row electrodes and straight through the discharge space and the dielectric layer
A plurality of column electrodes extending in the intersecting direction, a plurality of switching current paths connected in parallel with each other and electrically connected to the row electrodes, and a switching current path by individually controlling switching of the switching current paths. And a row electrode drive pulse generating means each comprising a controller for supplying a priming discharge pulse, a display data writing pulse and a light emission sustaining pulse to the row electrode, and a drive device for an AC discharge type matrix type plasma display panel comprising: The switching current path corresponding to the preliminary discharge pulse is
A driving device for an AC discharge type matrix type plasma display panel, comprising a current limiting element having a resistance value higher than a total resistance value of a switching current path for generating at least one of the write pulse and the light emission sustaining pulse. 2. The drive device according to claim 1, wherein the current limiting element is a resistance element. 3. The priming discharge pulse has a waveform that gently rises, and priming discharge occurs between the paired row electrodes.
The drive device according to claim 1, wherein the drive device is generated . Wherein said preliminary discharge pulse is driving apparatus according to claim 1 or claim 3, wherein the containing wall charge generating pulses allowed to generate a wall charge in the dielectric layer. 5. A plurality of row electrodes extension length in pairs, before
A dielectric layer covering the writing electrode, the dielectric layer and the discharge space;
A plurality of column electrodes facing each other with a space therebetween and extending in a direction orthogonal to the row electrodes, a plurality of switching current paths connected in parallel with each other and electrically connected to the row electrodes, and the switching current path. AC discharge type matrix type plasma having individually controlled switching control so that the switching current paths each include a pre-discharge pulse, a write pulse for display data, and a row electrode drive pulse generating means including a controller for supplying a sustaining pulse to the row electrode. A method of driving a display panel, wherein the discharge current amount by the preliminary discharge pulse is limited to a smaller amount than the discharge current amount by at least one of the write pulse and the light emission sustaining pulse. Method for driving plasma display panel. 6. A plurality of row electrodes extending in pairs, and
A dielectric layer covering the writing electrode, the dielectric layer and the discharge space;
The two electrodes face each other with a space therebetween and extend in a direction orthogonal to the row electrode.
An AC discharge type matrix system plug having a plurality of column electrodes.
A method of driving a plasma display panel, A pre-discharge pulse is applied to all the paired row electrodes simultaneously.
The reset section, in which the pair is applied to cause a preliminary discharge,
Apply a write pulse to one of the row electrodes
A pixel data pulse corresponding to pixel data is printed on the column electrode.
In addition, a write area that selectively forms wall charges in the pixel cells
While the sustain pulse is applied to the row electrodes, the wall charges are formed.
Sustain discharge section that allows sustain discharge of the formed pixel cells
With a subfield containing The preliminary discharge pulse has a waveform that rises gently.
The discharge current amount by the preliminary discharge pulse,
Pulse and / or the sustaining pulse
It is characterized by limiting to a smaller amount than the discharge current amount
AC discharge type matrix plasma display panel
Driving method.