JP3383154B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single insulated gate type semiconductor device and a semiconductor device such as an integrated circuit (LSI) including the same, and more particularly to an insulated gate type semiconductor device formed on an insulating film.

[0002]

2. Description of the Related Art Recent advances in high integration of semiconductor integrated circuits (LSIs) found in 256 Mb dynamic random access memory (DRAM) technology and the like are remarkable. However, taking a DRAM as an example, the memory cell area tends to decrease more and more with the progress of the degree of integration, and it is difficult to secure a cell capacity for preventing so-called soft error caused by alpha rays.
In order to prevent a soft error of DRAM, a so-called SOI (Si (Si) film is formed on the single crystal silicon film 165 on the insulating film (SOI insulating film) 202 as shown in FIG.
The Licon-On-Insulator structure is adopted. The SOI element is fine and can operate at high speed, and is promising as a high-performance element. If the SOI structure is used, the electron-hole pairs generated by alpha rays are
Since it can be limited to the single crystal silicon film (hereinafter referred to as “SOI film”) 165 on the insulating film, the soft error resistance is dramatically improved. Figure 11 shows n-channel SOI
This n-channel SOI device is a device shown in FIG.
As shown in, the so-called substrate floating effect due to holes accumulated in the channel region occurs, so that the drain breakdown voltage is lower than that of the bulk MOSFET. The conventional n-channel SOI device is shown in FIG.
As shown in (3), there is a problem of instability such as current overshoot in switching operation, which is a big problem in practical use.

As a measure against such a substrate floating effect in an n-channel SOI device, a structure using a material having a narrow bandgap (forbidden band width) E _g for the source region of the MOSFET channel region has been proposed. (JP-A-1-255252). Japanese Patent Laid-Open No. 1-252525
In the MOSFET disclosed in Japanese Unexamined Patent Publication No. 2 publication, by narrowing the band gap E _g of the semiconductor material forming the source region, it is possible to effectively prevent the accumulation of holes in the channel, which is the main cause of the substrate floating effect. is there.

MOSFET having Si as a channel region
On the other hand, the most typical material having a narrow band gap is Si _x Ge _1-x (0 <x <1), and one SOI / MOSFET using this is shown in FIG. . The n-channel SOI MOSFET of FIG. 14 (a)
Is an SOI film such as an oxide film on a Si substrate 201 which is a base substrate.
An insulating film 202 is formed, and a p-type S that serves as an active layer is formed thereon.
An OI film 203 is formed, and an n ⁺ source / drain region 206 is formed in a part of this SOI film. 14
The feature of (a) is that this n ⁺ source / drain region 206 is
The point is that the Si _x Ge _1-x layer 207 is formed inside. n ⁺ source region 206 and n ⁺ drain region 206
Channel region 20 made of p-type SOI film sandwiched between
A gate oxide film 25 is formed on the upper part of the gate electrode 3, and a gate electrode 26 made of, for example, polysilicon is formed on the gate oxide film 25, which is similar to a normal n-channel MOSFET.

The n-channel SOI MO of FIG. 14A
The potential profile of the SFET is shown in FIG. In such a MOSFET, as shown in FIG. 14B, the bandgap of the source region can be narrowed to the position of the broken line, and the hole current flowing inside the n ⁺ source region exponentially increases. It is clear experimentally or by simulation. For example, n-channel SOI / MOSF with a channel length of 0.5 μm
The current-voltage characteristic of ET is shown in FIG. The solid line in the current-voltage characteristics shown in FIG. 15 indicates that Ge ions have an acceleration voltage V _ac = 50.
This is a measurement for an SOI-MOSFET which is ion-implanted at a dose amount Φ = 3 × 10 ¹⁶ cm ^-2 at kV. In FIG. 15, the SiGe layer shown by the solid line is the source / drain region for the n-channel MOSFET (without the SiGe region) shown in FIG.
It can be seen that the drain breakdown voltage of the n-channel MOSFET inside the drain region is improved by 1 V or more.

As shown in the sectional structure of FIG.
The channel SOI.MOSFET is manufactured by the following manufacturing process. First, SIMOX (Separati)
An SOI substrate is prepared by using an on-by-implanted OXygen) method. That is, the silicon substrate 2
Oxygen ions are ion-implanted into 01 and heat-treated to separate the upper silicon film (SOI film) 203 from the lower silicon substrate 201 so that the buried oxide film (S
An OI insulating film) 202 is formed. And the upper layer SOI
A field oxide film region serving as an element isolation region for electrically decomposing elements adjacent to the film 203 is formed by S.
LOCOS (Local Oxi) using i ₃ N ₄ film, etc.
formation by a method such as a date of silicon method (however, in FIG. 14A, although illustration of the element isolation region is omitted, it is easily understood that the element isolation regions are located on both sides deviated from the illustrated portion. Will). Subsequently, the Si ₃ N ₄ film used for the LOCOS method is removed to expose the surface of the element formation region (active region) 203 surrounded by the field oxide film region, and the exposed active region (SOI film) 203 A gate oxide film 25 is formed on the surface of the substrate by a thermal oxidation method or the like. And after this, LPCV on this
D (Low Pressure Chemical V
The polysilicon film 26 is formed by an apour deposition method or the like. Then, by a photolithography process, a resist pattern is formed only on the upper portion of the gate electrode planned region portion of the polysilicon film 26, and this resist pattern is used as a mask for RIE (React).
A polysilicon gate electrode 26 and a gate oxide film 25 are formed by an iv Ion Etching method or the like. Then, n-type impurity ions such as As for forming the n ⁺ source / drain regions 206 are ion-implanted in a self-aligned manner by using the polysilicon gate electrode 26 and heat-treated. Subsequently, Ge is ion-implanted into the source / drain regions 206 and heat treatment is performed to form the source / drain regions 2
If the SiGe layer 207 is formed in the inside of FIG.
N-channel SOI / MOSFE as shown in (a)
T is completed. Actually, after this, further oxide film, PSG
An interlayer insulating film such as a film or a BPSG film is deposited on the surface, an opening (contact hole) for electrode contact is formed in this interlayer insulating film, and a metallization process for source / drain metal electrode wiring or the like is performed. The illustration is omitted here.

[0007]

On the other hand, p channel S
Until recently, the floating body effect of OI / MOSFETs has not received much attention because of its high drain breakdown voltage. The drain breakdown voltage is high because the current driving power of the p-channel SOI.MOSFET is smaller than that of the n-channel SOI.MOSFET, and the impact ionization rate of holes due to the electric field near the drain for electrons is small. However, according to a detailed experiment by the inventor of the present invention, the gate length is 0.5 μm.
With the miniaturization of LSI patterns using the following elements,
Even in the p-channel SOI MOSFET, the current driving force is increased, and the electric field near the drain is increased,
It has gradually become clear that the substrate floating effect can no longer be ignored. For example, as shown in FIG. 16A, even in the case of a p-channel SOI MOSFET, Id-V
d: A kink in the characteristic can be seen, or FIG.
It has become clear that an abnormal decrease in the threshold coefficient appears in the pentode region as shown in (b). These abnormal characteristics cause the formation of "distortion" of the output wave in, for example, an analog circuit, as in the case of the n-channel SOI.MOSFET, and lower the threshold value in the pentode region. Further, as shown in FIG. 17A, a p-channel SOI.MOSFET (solid line) whose drain breakdown voltage is lower than that of a bulk MOSFET (broken line) is used in a CMOS inverter circuit as shown in FIG. 17B, for example. In this case, even if the input is at the high level (High), the output does not go to the low level (Low) and the output does not swing fully.

In view of the above problems, the object of the present invention is to
A p-channel SOI / MOS that cannot be ignored in a miniaturized structure with a gate length of 0.5 μm or less
It is to provide a novel structure capable of suppressing the floating body effect of a semiconductor device such as a pMOS LSI or a CMOS LSI including an FET.

[0009]

In order to achieve the above object, the present invention provides an n-type first semiconductor region, a source region, a drain region, and an n-type first semiconductor region formed on a first insulating film. 1
A semiconductor device including at least a transistor having a gate electrode for controlling a current flowing through the first semiconductor region via a second insulating film as a gate insulating film formed on the semiconductor region of The source and drain regions contain a p-type impurity element, and at least part or all of at least one of the source and drain regions or part of the region reaches the channel region.
The first feature is that the second semiconductor region has a forbidden band width (bandgap) E _g smaller than that of the second semiconductor region.

To further achieve the above object, the present invention provides an n-type first semiconductor region formed on a first insulating film, a source region, a drain region, and the first semiconductor region. What is claimed is: 1. A semiconductor device comprising at least a transistor having a gate electrode for controlling a current flowing through the first semiconductor region via a gate insulating film formed on the upper part, wherein a p-type impurity element is contained in the source and drain regions. A second semiconductor region having a forbidden band width E _g smaller than that of the first semiconductor region is formed on the upper part or the lower part or both of the upper part and the lower part of at least one of the source and drain regions. This is the second feature.

As the second semiconductor region having a small band gap E _g, a Si-based material is preferable when the first semiconductor region is Si, and specifically, Si _x G
e _1-x and Si _x Sn _1-x are preferable.

The second semiconductor region may be made of a material containing strain in the direction of increasing the lattice constant of Si.
Good. As a method for forming these materials, ion implantation of Ge or Sn into Si, selective CV of SiGe layer (SiSn layer or the like may be used instead of SiGe) on Si are selected.
D, formation of a SiGe layer (or SiSn layer) which is not strained (no change in lattice constant), Si crystal growth on it, Si crystal growth on CaF2 and CaSrF2 layers, etc. .

C of the SiGe layers 238 and 239 shown in FIG.
In the case of VD, p of the first semiconductor region made of Si or the like is used.
The second semiconductor regions 238 and 239 having a small forbidden band width E _g are formed on the ⁺ source / drain regions 312 and 313. Further, p ⁺ source region 4 when the growth of the Si layer 45a on the SiGe layer 44 shown in FIG. 7
A second semiconductor region is formed under 09, and p ⁺
The source region itself is also strained and the band gap Eg is reduced.

FIG. 1 (a) shows p ⁺ as the most basic example.
FIG. 7 shows a band diagram in the case where the entire source region is formed of a SiGe layer and the band gap E _{g of} only the p ⁺ source region is narrowed uniformly. For Si, Si _x Ge _1-x is Δ
Since the band gap is narrow by Ev, ΔE on the valence band side
There will be a discontinuity in the band of v. Due to this discontinuity, the energy barrier φ ₁ against the inflow of electrons accumulated in the channel portion toward the source is reduced as shown in FIG. This promotes the inflow of electrons accumulated in the channel portion into the p ⁺ source region, and suppresses the substrate floating effect. In theory, it is desirable that the heterojunction interface and the edge of the p ⁺ source region coincide with each other as shown in FIG. 1A, but from the viewpoint of manufacturing technology, it may be as shown in FIG. 1B. That is, FIG. 1B shows a band diagram when a part of the p ⁺ source region is the SiGe layer, that is, when the SiGe / Si heterojunction interface is in the p ⁺ source region. In this case, the barrier against the electrons accumulated in the channel is increased due to the presence of Si in the p ⁺ source region, but if this Si part is formed as an extremely thin layer of 10 nm or less, a tunnel current flows and the charge is accumulated in the channel. The electrons are sucked into the p ⁺ source region. S
Manufacturing the thickness of the i portion with an accuracy of 10 nm or less can be controlled relatively easily by selecting heat treatment conditions and the like. Furthermore Si
_Since the increase in the recombination rate of carriers in _x Ge _1-x also promotes the extraction of electrons from the channel part,
Even in the structure shown in FIG. 1B in which the Si portion is present in the p ⁺ source region, it is possible to suppress the floating body effect of the p-channel SOI MOSFET. However, in this case,
Since the portion A shown in (b) works in the direction of suppressing the flow of holes, which is a transistor current, the p ⁺ source region p-type impurity density (n _SiGe and n _Si ) should be as high as possible. It is good practice not to block the flow of holes.

On the other hand, from the viewpoint of extracting the electrons accumulated in the channel to the source, the impurity density n of the _SiGe portion is nSiGe, and the impurity density n of the Si portion of the p ⁺ source region is n.
If si is lowered, a band diagram as shown in FIG. 1C is obtained, and the barrier against electrons is a value ΔE (<Δ which is smaller than ΔEv.
Since it can be set to Ev), it is more effective than the case of FIG. Moreover, as compared with FIG. 1A, Si _x Ge _1-x
May enter the channel side, and in this case also, the effect of extracting electrons into the source as described above occurs.

[0016]

FIG. 2A shows a sectional structure of a p-channel SOI.MOSFET according to a first embodiment of the present invention. In FIG. 2A, the n-type (1
00) a first insulating film (SOI
An n-type SOI film 23 to be an n-type first semiconductor region is formed via a buried oxide film 202 to be an insulating film. The n-type SOI film 23 is isolated by the thermal oxide film 24 which is deeply formed from the surface of the SOI film 23 to the buried oxide film 202. Then, using the region of the n-type SOI film 23 thus isolated as the active region, the p ⁺ source region 216 and the p ⁺ drain region 226 are formed inside the active region so that their bottoms are in contact with the buried oxide film 202. ing. Inside the p ⁺ source region 216 and the p ⁺ drain region 226, a silicon germanium (SiGe) region 21 containing boron (B) is formed.
7, 227 are formed, and the SiGe regions 217, 22 are formed.
On top of 7, oxide film (SiO ₂ film), PSG film, BP
An interlayer insulating film 211 such as an SG film is formed, and a source metal electrode 218 and a drain metal electrode 228 are formed through contact holes formed in the interlayer insulating film 211. 2A is an exaggerated schematic cross-sectional view for the sake of convenience. Actually, the p ⁺ source / drain regions 216 and 226 protruding from the SiGe regions 217 and 227 are 10 n.
It is a thin region of m or less. A gate electrode 26 made of polysilicon or the like is formed on the channel region 23 sandwiched between the p ⁺ source region 216 and the p ⁺ drain region 226 via a gate oxide film 25 serving as a second insulating film. . A thin oxide film 27 called a post oxide film is formed on the surface of the polysilicon gate electrode 26. The p ⁺ source region 216 and the p ⁺ drain region 226 contain a p-type impurity element such as boron (B) in a range of 6 × 10 ^{18 to} 6 × 1.
This is a region doped with a high impurity density of about 0 ²⁰ cm ^-3 .

FIG. 2B is a diagram showing the drain current (Id) -drain voltage (Vd) characteristics of the single p-channel SOI.MOSFET according to the first embodiment of the present invention in comparison with the reference example. . The Id-Vd characteristics shown in FIG. 2B are p with a gate length L = 0.4 μm and a gate width W = 100 μm.
This is for channel SOI MOSFET, and the solid line is Ge ⁺ ions at 25 KeV and the dose amount is 3 × 1.
Implanted at 0 ¹⁶ cm ^-2 p ⁺ -SiGe regions 217, 22
7 is the characteristic of the single element formed, and the broken line shows the corresponding p
These are the characteristics of a single element (reference example) having no ⁺ -SiGe region. It can be seen that by having the p ⁺ -SiGe regions 217 and 227, the flow of electrons accumulated in the channel portion into the p ⁺ source region is promoted, and the drain breakdown voltage is improved by 1 V or more.

The p-channel SOI shown in FIG.
The MOSFET can be manufactured by the method shown in FIGS. 3 (a) to 3 (d).

(A) First, the n-type (100) Si substrate 2
Oxygen in 1 acceleration voltage 180 KeV, dose 2 × 12 ¹⁸
cm ⁻² and heat treatment at 1300 ° C. for 5 hours by a so-called SIMOX method to obtain a depth of 200 n from the silicon surface.
A buried oxide film (SOI oxide film) 202 having a thickness of 100 nm is formed at the position m. At this time, a single crystal silicon film (SOI film) 23 is formed on the SOI oxide film 202 by about 200.
nm is formed. Next, the surface of the SOI film 23 is thermally oxidized,
The SOI film 23 is thinned to a thickness of 100 nm by etching away the oxide film with NH ₄ F solution or the like.

(B) Next, an element isolation film 24 is formed by a selective oxidation technique such as LOCOS method, and adjacent elements are electrically isolated. Next, a gate oxide film 25 is formed to a thickness of 5 nm, polycrystalline Si (polysilicon) 26 doped with boron (B) at a concentration of 10 ²⁰ cm ^{-3 is} deposited to a thickness of about 200 nm by a CVD method, and photolithography is performed. The gate electrode 26 is processed into the shape shown in FIG. For example, gate length L = 0.4 μm, gate width W = 1
The gate electrode is processed to have a size of 0 μm. Next, the entire surface is oxidized to form a post oxide film 27 having a thickness of 5 nm on the surface of the polycrystalline Si (upper surface and side surface).

(C) Next, as shown in FIG.
Acceleration voltage 30 KeV, dose 1-3 × 10 ¹⁶ cm ^-2
Ion implantation is carried out at a Si layer (Si _0.9 Ge _0.1 to Si _0.7 Ge) containing about 10 to 30% of Ge in peak concentration.
_0.3 layer) 28 is formed.

(D) Next, a SiN film having a thickness of 20 nm is deposited on the entire surface, and then the entire surface is etched to form sidewall SiN on the sidewall of the polycrystalline silicon gate electrode as shown in FIG. 3C.
The film 29 is formed. Furthermore, BF ₂ ⁺ is accelerated at an acceleration voltage of 20 Ke.
V, and the ion implanted at a dose 3 × 10 ¹⁵ cm ^-2, by which the 30 minute anneal in a nitrogen atmosphere at then 850 ° C., the p ⁺ layer 217 and 227 and Si of SiGe p ⁺
Layers 216 and 226 are formed.

(E) Further, Si is formed on the entire surface by the CVD method or the like.
An interlayer insulating film 211 such as an O ₂ film, a PSG film, and a BPSG film is deposited to a thickness of 300 nm, a contact hole is opened at a predetermined portion in the interlayer insulating film 211, and wiring materials such as Si and Cu are used.
As shown in FIG. 3D, the source metal electrode 218 and the drain metal electrode 2 are formed by depositing Al (Al-Si, Al-Cu-Si) or the like on the entire surface by 400 nm and processing it.
By forming 28, the p-channel SOI MOSFET of the first embodiment of the present invention is completed.

In the structural example shown in FIG. 2, the source region is not entirely made of SiGe and the heterojunction interface is inside the p ⁺ source region. However, as described above with reference to FIGS. As described above, it is preferable that the edge of the p ⁺ source region coincides with the heterojunction interface. However, not all source regions are S
It does not have to be iGe, and the source portion in contact with the channel region may have a structure in which the p ⁺ -Si region 216 of at most about 10 nm remains, as shown in FIGS. 1B and 1C. The thickness of the p ⁺ -Si portion is 850 to 900 after BF ₂ ⁺ ion implantation for the p ⁺ source / drain region.
It can be controlled by adjusting the annealing time at about ° C. What happens is that under the diffusion conditions of about this temperature, the Si of Ge is
This is because the diffusion inside is so small that it can be ignored. Also,
Further, if the annealing time is adjusted, the edge of the p ⁺ source region and the heterojunction interface can be made to coincide with each other to obtain a potential profile as shown in FIG. B like this
It is also possible to easily realize the form in which the impurity density n _{S i} of the source Si portion is lower than the impurity density n _SiGe of the source SiGe portion as shown in FIG. Further, in this embodiment, Ge ions are vertically incident (ion-implanted) on the Si substrate. However, in order to prevent channeling of Ge ⁺ ions, a slight inclination angle (for example, 7 °) is provided to form a hetero interface. The position may be controlled. Further, in order to make Ge ⁺ ions incident on a portion closer to the channel, so-called rotational ion implantation (oblique ion implantation) may be performed at an angle of about 40 °.

Further, in the first embodiment of the present invention, Si
Ge is used as a material with a narrow band gap,
The material is not limited to SiGe, and other materials having a narrower band gap than Si-based Si may be used. For example, an alloy of Sn and Si may be used.

Although the impurity for forming the p ⁺ layer is boron (B) in the above description, other group III impurities such as indium (In) or gallium (Ga) may be used. In the above description, SALICIDE (Self
Although it does not have an Aligned Silicon structure, if the parasitic resistance needs to be reduced, SALI is naturally used.
The CIDE structure is also applicable. Further, in the structure shown in FIG. 2A, both of the p ⁺ source / drain regions are SiGe.
However, the effect of the present invention is that only the source portion is made of SiG.
Even if it is e, it will not be lost. Further, even if SiGe gets into the channel, the effect of the present invention is not lost. The band diagram at this time is close to that of FIG. 1A, and the band discontinuity of ΔEv in the valence band slightly moves to the channel side.

Although the polycrystalline Si of the gate is described as that of boron (B) -doped p-type doped polysilicon, n-type doped polysilicon such as phosphorus (P) -doped may be used, or polycide (poly- A two-layer structure of crystalline Si and silicide) may be used. Further, a refractory metal such as W, Ti or Mo, or another metal may be used as the gate material.

FIG. 4 shows p according to the second embodiment of the present invention.
The cross-sectional structure of a channel SOI MOSFET is shown. In FIG. 4, an n-type SOI film 23 to be an n-type first semiconductor region is formed on an n-type (100) silicon substrate 21 with a buried oxide film 202 to be a first insulating film interposed. The n-type SOI film 23 is isolated by the thermal oxide film 24 deeply formed from the surface of the SOI film 203 to the buried oxide film 202. Then, using the region of the SOI film 23 thus isolated as an active region as an active region, ap ⁺ source region 312 and ap ⁺ drain region 313 are formed inside the active region so that their bottoms are in contact with the buried oxide film 202. . A second layer is formed on the p ⁺ source region 312 and the p ⁺ drain region 313.
Of p ⁺ -SiGe containing boron (B) to be the semiconductor region of
Regions 238 and 239 are formed. SiGe region 2
38 and 239, an interlayer insulating film 211 is formed on
The interlayer insulating film 211 is formed on the SiGe regions 238 and 239.
A source metal electrode 218 and a drain metal electrode 228 are formed through the contact holes formed therein. A gate oxide film (gate insulating film) 2 is formed on the channel region 23 formed of the first semiconductor region sandwiched between the p ⁺ source region 312 and the p ⁺ drain region 313.
A gate electrode 26 made of polysilicon or the like is formed via 5. A thin oxide film 27 called a post oxide film is formed on the surface of the polysilicon gate electrode 26. p
^{The +} source region 312 and the p ⁺ drain region 313 are made of p-type impurities such as boron (B) in a range of 6 × 10 ¹⁸ to 1 × 1.
This is a region doped with a high impurity density of about 0 ²⁰ cm ^-3 .

The p-channel SOI.MOSFET according to the second embodiment of the present invention can be manufactured by the manufacturing method shown in FIGS. 5 (a) to 5 (c).

(A) Using an SOI substrate (SIMOX-SOI substrate) by SIMOX method or the like, and for this SIMOX-SOI substrate, after element isolation by LOCOS method, gate oxidation is performed and B-doped polycrystalline Si is used. Membrane 2
The process is the same as that of the first embodiment of the present invention up to the step of processing 6 as a gate electrode and heat-treating the entire surface in an oxidizing atmosphere to form an oxide film 27 thereafter.

Next, a SiN film having a thickness of 20 nm is deposited on the entire surface, and the entire surface is etched back to form a sidewall SiN film 29 on the sidewall of the gate electrode as shown in FIG. 5A.

(B) Next, as shown in FIG. 5 (b), SiG is selectively formed on the exposed Si surface of the n-type SOI film by the CVD method using the reaction of SiH ₄ gas and GeH ₄ gas.
e layers 238 and 239 are deposited to a thickness of 100 nm. Then, B ⁺ is ion-implanted at 3 × 10 ¹⁵ cm ⁻² at 30 KeV.

[0033] (c) subsequently the substrate temperature 850 ° C., in a nitrogen atmosphere, by annealing for 30 minutes, also in the p ⁺ layer Si thereunder including SiGe layer 239 p ⁺ -SiGe
Regions 238 and 239 p ⁺ source region 312 and p ⁺ drain region 313 are formed. Further, as shown in FIG. 5C, an interlayer insulating film 2 such as a SiO ₂ film is formed on the entire surface by a CVD method or the like.
11 is deposited to a thickness of 300 nm, and the interlayer insulating film 21
1. Make a contact hole in 1 and make wiring material such as Si, Cu
If a source metal electrode 218 and a drain metal electrode 228 are formed by depositing Al containing 400 nm on the entire surface and processing the p-channel SOI.MOSF of the second embodiment of the present invention.
ET is completed.

In the second embodiment of the present invention, an n-type SOI is used.
The SiGe layers 238 and 239 are formed on the film 23 by CVD.
Therefore, the portion of the p ⁺ source / drain region close to the channel is made of Si, and the band diagram is the same as in FIGS. 1B and 1C. This SiGe
In the case of the second embodiment of the present invention, the size (distance) of the Si region between the edge and the channel region is mainly the gate sidewall 29.
And the thickness of the SOI film 23.

As a modification of the second embodiment of the present invention, as shown in FIG. 6, a sidewall Si is formed on the sidewall of the gate electrode 26.
The structure does not have an N film. In the structure of FIG. 6, after the post oxide film 27 is formed, the entire surface is etched back to remove only that on the n-type SOI film 23, and then the SiGe layer 2 is formed by selective CVD.
38 and 239 with a thickness of 100 nm, and then B ⁺
Ion implantation is performed to make the SiGe layers 238 and 239 and the n-type SOI film 23 thereunder into p ⁺ layers, so that the p ⁺ -SiGe source region 238, the p ⁺ -SiGe drain region 239,
A p ⁺ -Si source region 312 and a p ⁺ -Si drain region 313 are formed. The subsequent steps are the same as above.

In the description of the manufacturing method of the second embodiment of the present invention described above, the case where B ⁺ ion implantation is used has been described, but ion implantation by ion of a compound molecule such as BF ₂ ⁺ may also be used. Alternatively, In ⁺ or Ga ⁺ may be ion-implanted instead to form the p ⁺ layer. Also, SAL
It is also possible to apply the ICIDE structure. Further, in the above, the introduction of the p-type impurity such as B is performed by the SiGe layers 238, 2
39 is performed, but p-type impurities are previously introduced into the n-type SOI film 23 by ion implantation or the like, and then the SiGe layers 238 and 239 are deposited, and then the p-type impurities are further added to the SiGe layers 238 and 239. Type impurities may be introduced, or a gas such as BH ₃ or B ₂ H ₆ may be introduced into the CVD gas to perform p ⁺ conversion simultaneously with SiGe deposition. Semiconductors with narrow bandgap are Si _x Ge _1-x
However, Si _x Sn _1-x , Ge or the like may be used.

FIG. 7 shows p according to the third embodiment of the present invention.
The cross-sectional structure of a channel SOI MOSFET is shown. In FIG. 7, an n-type S is formed on the n-type (100) silicon substrate 21 with a buried oxide film 202 serving as a first insulating film interposed therebetween.
The OI film 231 is formed. And the n-type SOI film 2
A silicon germanium (SiGe) film 44 serving as a second semiconductor region is formed on a part of 31 to form the SiGe film 44.
N-type S on which the SiGe film 44 is not formed
An n-type silicon (Si) film 45 serving as a first semiconductor region is formed on the OI film 231. n-type Si film 4
From the surface of No. 5 until reaching the n-type SOI film 231
An element isolation insulating film 24 such as _two films is formed. The element isolation insulating film 24 may be deeply formed from the surface of the n-type SOI film 231 to the buried oxide film 202.
The element-isolated region of the n-type Si film 45 is used as an active region, and the p ⁺ source region 40 is provided inside the active region.
9 and the p ⁺ drain region 226 are formed so that the p ⁺ source region 409 has its bottom in contact with the SiGe film 44 and the p ⁺ drain region 410 has its bottom in contact with the buried oxide film 202. This p ⁺ source region 409,
For the p ⁺ drain region 410, the source metal electrode 2 is formed through a contact hole formed in the interlayer insulating film 211.
18 and a drain metal electrode 228 are formed.
In addition, p ⁺ source region 409 and p ⁺ drain region 41
A gate electrode 26 made of polysilicon or the like is formed on the n-type Si film 45 serving as a channel region between 0s via a gate insulating film (gate oxide film) 25. The p ⁺ source region 409 and the p ⁺ drain region 410 are made of a p-type impurity element such as boron (B) in a range of 6 × 10 ¹⁸ to 1 × 10 6.
^This is a region doped with a high impurity density of about ²⁰ cm ⁻³ .

According to the third embodiment of the present invention, p ⁺
The Si layer to be the source region 409 is formed on the SiGe layer 44 having a lattice constant larger than that of Si and is a strained silicon film. Since the p ⁺ source region 409 is formed of strained silicon, a normal silicon-based M
As compared with the case of the OSFET, the bandgap Eg of the source is also narrowed (for example, ΔEg = 0.2 eV is narrowed), and as a result, the flow of electrons from the channel toward the source can be greatly promoted.

The p-channel SOI.MOSFET of the third embodiment of the present invention can be manufactured by the method shown in FIGS. That is, (a) by implanting oxygen ions into the n-type (100) silicon substrate 21 under the conditions of an accelerating voltage of 180 KeV and a dose of 2 × 10 ¹⁸ cm ⁻² , heat treatment is performed at 1300 ° C. for 5 hours, As shown in FIG. 8 (a), the depth from the surface is 20
A buried oxide film (SO
(I oxide film) 202 and an n-type SOI film 231 are formed on the surface of the substrate. In addition, here, the SOI
The SIMOX method has been taken as an example of the method for forming the substrate, but the bonding method (Silicon Direct Bond) is used.
ing: SDB method) may be used (the same applies to other embodiments). Next, the n-type SOI film 23
After thermally oxidizing the surface of No. 1, the step of etching away this oxide film portion with NH ₄ F solution is repeated,
The n-type SOI film 231 is thinned to 10 nm.

(B) Next, as shown in FIG. 8B, a thickness of 30 n with a Ge concentration of 50% is formed on the n-type SOI film 231.
The SiGe film 44 of m is formed by the CVD method. At this time, since the Ge concentration is high, the SiGe film 44 grows beyond its critical thickness. Therefore, Si _x Ge _1-x (0
The <x <1) film 44 is made of Si of the underlying n-type SOI film 231.
It does not match the lattice constant of, and grows with the original lattice constant of Si _x Ge _1-x . Next, as shown in FIG. 8C, Si is formed using photolithography and RIE.
The Ge film 44 is replaced with the SOI film 23 in the region serving as the p ⁺ source region.
Leave only on 1.

(D) Next, as shown in FIG. 8D, an n-type silicon (Si) film 45 having a thickness of 80 nm is formed on the entire surface by a CVD method using SiH ₄ as a raw material at a film forming temperature of 550 ° C. , 45a are formed. At this time, the n-type Si film 45,
A portion 45a of the 45a on the SiGe film 44 is subjected to spreading strain and grows with a lattice constant of Si _x Ge _1-x ,
It becomes a strained n-type Si film. The base of other parts is n-type SO
Since it is the I film 231, it is not strained and grows with the original lattice constant of Si to become an unstrained n-type Si film 45.

(E) Next, as shown in FIG.
P (Chemical Mechanical Pol)
isching: chemical mechanical polishing)
After the surfaces of the type Si films 45 and 45a are flattened and flattened, the element isolation insulating film 24 is formed around the portion to be the active layer. Then, on the n-type Si film 45, a silicon oxide film having a thickness of 5 nm to be the gate oxide film 25 and a boron-doped polysilicon film having a thickness of 300 nm to be the gate electrode 26 are sequentially formed. Since the difference between the n-type Si films 45 and 45a is about 30 nm, the flattening is not performed by the CMP method or the like, and the difference is left and used as a reference for mask alignment in photolithography. Good. Next, as shown in FIG. 8E, the doped polysilicon film 26 and the silicon oxide film 25 are patterned to form a gate electrode 26 and a gate oxide film 25. At this time, the strained n-type Si film 45a and the unstrained portion of the n-type Si film
The interface with the film 45 is the gate electrode 2 as shown in FIG.
Most preferably, it is directly below the 6 end. However, the interface may enter the channel, or the interface may be located farther from the channel than the end of the gate electrode 26. Next, as shown in FIG. 8E, BF ₂ ions are ion-implanted under conditions of an acceleration voltage of 30 KeV and a dose amount of 5 × 10 ¹⁵ cm ^{−2 using} the gate electrode 26 as a mask, and then 850 ° C. for 30 minutes. Heat treatment is performed to form the p ⁺ source region 409 and the p ⁺ drain region 410. At this time, p ⁺ source region and n
The pn junction with the Si-type silicon film 45 is a strained p-type silicon film 45.
Most preferably, the interface between a and the p-type silicon film 45 in the unstrained portion coincides with the interface, but the pn junction does not have to coincide with the interface.

(F) Finally, as shown in FIG.
After forming a SiO ₂ film 211 as an interlayer insulating film with a thickness of 400 nm on the entire surface, a contact hole is opened in this SiO ₂ film 211 to form a source metal electrode 218 and a drain metal electrode 228, and further a gate wiring. (Not shown)
To complete.

In the case of the third embodiment of the present invention, Si
Since the two narrow bandgap materials of the Ge layer 44 and the p ⁺ strained silicon layer 409 are simultaneously formed as the p ⁺ source region, the above-mentioned electron flow is further promoted, which is very effective in suppressing the substrate floating effect of the p-channel SOI MOSFET. Is effective for.

Instead of the SiGe layer 44, a narrow bandgap material such as a SiSn layer having a lattice constant larger than that of other Si and a band gap smaller than that of Si may be used.

FIG. 9 shows p according to the fourth embodiment of the present invention.
The cross-sectional structure of a channel SOI MOSFET is shown. In FIG. 9, an n-type S is formed on the n-type (100) silicon substrate 21 via an embedded insulating film 251 serving as a first insulating film.
The OI film 255 is formed. Embedded insulating film 251
For this, a CaF ₂ film having a lattice constant substantially equal to that of Si is used, and a part thereof is a Ca _1-x Sr _x F ₂ (0 <x <1) film 252. Therefore, the n-type first semiconductor region (n-type SOI) above the Ca _1-x Sr _x F ₂ film 252 is formed.
The film) 255 becomes a strained Si film and the band gap is narrowed. The SOI film 2 having the narrowed band gap
55 is a p ⁺ source region 259 and a p ⁺ drain region 260, and the unstrained portion of the n-type SOI film 255 is a channel region. And SO including the strained Si film portion
The I film 255 is isolated from the surface of the SOI film 255 by the thermal oxide film 24 formed deeply until reaching the buried insulating film 252. Then, the strained and non-strained SOI film 255 thus isolated is used as an active region, and the p ⁺ source region 259 and the p ⁺ drain region 260 made of only the strained Si film are buried in the bottom of the active region. It is formed so as to be in contact with the insulating film 252. A source metal electrode 218 and a drain metal electrode 228 are formed in p ⁺ source region 259 and p ⁺ drain region 260 through contact holes formed in interlayer insulating film 211. Also p ⁺
A gate electrode 2 made of polysilicon or the like is formed above the channel region 255, which is a strain-free Si film between the source region 259 and the p ⁺ drain region 260, via the gate oxide film 25.
6 is formed.

The p-channel SOI.MOSFET according to the fourth embodiment of the present invention can be manufactured by the method shown in FIGS.

(A) First, as shown in FIG.
A CaF ₂ film 251 and an n-type SOI film 255 are formed on the silicon substrate 21 by a vapor phase epitaxial growth method or MBE (Mole).
It is sequentially formed by a method such as a Clarious Bean Epitaxy method. Next, as shown in FIG. 10A, after forming the element isolation insulating film 24, the gate oxide film 25 and the gate electrode 26 are formed on the n-type SOI film 255. n-type SOI
The thickness of the film 255 is, eg, 30 nm.

(B) Next, as shown in FIG. 10B, an acceleration voltage of 80 KeV and a dose of 1 so that Sr ⁺ ions penetrate the n-type SOI film 255 into the CaF ₂ film 251 by using the gate electrode 26 as a mask. Ion implantation is performed at × 10 ¹⁷ cm ^-2 . After that, heat treatment is performed to form the CaF ₂ film 52.
Is partially changed to the Ca _1-x Sr _x F ₂ (0 <x <1) film 252, and at the same time, the strained n-type SOI film 255a is formed in a self-aligned manner. As a result, the strained n-type SOI film 255a and the unstrained portion of the n-type SOI film 2 which are the most preferable form are formed.
It becomes possible to easily form a structure in which the interface with 55 coincides with the gate end.

(C) Next, as shown in FIG. 10C, p ⁺ such as B ⁺ or ⁴⁹ BF ₂ ⁺ is formed by using the gate electrode 26 as a mask.
Type impurity ions are implanted into the strained n-type SOI film 255a, and then heat treatment is performed to form ap ⁺ source region 259,
A p ⁺ drain region 260 is formed. Subsequent steps are similar to those of the first to third embodiments. An interlayer insulating film 211 such as a SiO ₂ film or a PSG film is formed on the entire surface by a CVD method or the like, and contact holes in the interlayer insulating film are formed. By forming the source metal electrode 218 and the drain metal electrode 228 through the above, the p-channel SOI.MOSFET of the fourth embodiment of the present invention shown in FIG. 9 is completed.

Although only the p-channel MOSFET has been described in the above-described first to fourth embodiments of the present invention, the present invention is not limited to the semiconductor device using only the p-channel MOSFET described above. In practicing the present invention, an LS using only p-channel MOSFETs
C in which not only I but also n-channel MOSFETs are mixed
The present invention can be applied to circuits such as MOS / LSI.

According to the present invention, since the band gap of the source portion or the source / drain portion is narrow, the energy difference between the Fermi level of the wiring material and the valence band of the p ⁺ semiconductor at the contact portion with the wiring material ( The so-called Schottky barrier) is reduced and the contact resistance is reduced.
As a result, the conversion conductance gm of the semiconductor device of the present invention increases, and high speed operation becomes possible.

Further, a material layer having a narrow band gap may be formed above and below the source / drain regions. In addition, the present invention is not limited to the above-described embodiment, but can be modified in various ways.

[0054]

As described above, according to the present invention, a p-channel MOSFET having an SOI structure due to miniaturization is provided.
The substrate floating effect can be suppressed.

[Brief description of drawings]

FIG. 1 is a band diagram for explaining the principle of the present invention.

FIG. 2 (a) is a schematic diagram of p according to the first embodiment of the invention.
2 is a sectional view of the channel SOI MOSFET.
(B) is a figure which shows the static characteristic.

FIG. 3 is a cross-sectional view for explaining the manufacturing process of the p-channel SOI • MOSFET according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a p-channel SOI MOSFET according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the manufacturing process of the p-channel SOI.MOSFET according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a p-channel SOI MOSFET according to a modification of the second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a p-channel SOI.MOSFET according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the manufacturing process of the p-channel SOI.MOSFET according to the third embodiment of the present invention.

FIG. 9 is a cross-sectional view of a p-channel SOI MOSFET according to a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining the manufacturing process of the p-channel SOI.MOSFET according to the fourth embodiment of the present invention.

FIG. 11 is an example of a structure of a conventional n-channel SOI MOSFET.

FIG. 12 is a diagram for comparing drain breakdown voltages of an n-channel SOI MOSFET and an n-channel bulk MOSFET.

FIG. 13 is a diagram for explaining overshoot of an output current when switching an n-channel SOI MOSFET.

FIG. 14A is an n-channel SOI.MO having a Si _x Ge _1-x region in an n ⁺ source / drain region.
FIG. 14B is a sectional view of the SFET, and its potential profile (band diagram) is shown.

FIG. 15 is an n-channel F having a Si _x Ge _1-x region.
It is a figure which compares the Id-Vd characteristic of n channel FET which does not have ET.

FIG. 16: P-channel SOI / MO with L = 0.2 μm
It is a figure which shows the substrate floating effect of SFET.

FIG. 17 is a diagram for comparing the IV characteristics of a conventional p-channel bulk MOSFET and a conventional p-channel SOI.MOSFET (FIG. 17A) and a diagram for explaining a CMOS inverter (FIG. 17B). Is.

[Explanation of symbols]

21 Si substrate 23, 45, 165, 231, 255
First semiconductor region: SOI layer Single crystal silicon layer 24 Element isolation film 25 Second insulating film: Gate insulating film (gate oxide film) 26 Gate polycrystalline Si 27 Post oxide film 28, 44 Second semiconductor region: SiGe Layer 29 SiN sidewall 202 First insulating film: buried oxide film (SOI insulating film) 211 CVD SiO ₂ 216, 312, p ⁺ source region 217, 238 p ⁺ -SiGe source region (second semiconductor region) 218, source Metal electrode 226, 313, 410 p ⁺ drain region 227, 239 p ⁺ -SiGe source region (second semiconductor region) 228 drain metal electrode 251 First insulating film: CaF ₂ film 252 Ca _1-x Sr _x F ₂ Film 255a Strained Si layers 259 and 409 p ⁺ strained Si source region 260 p ⁺ strained Si drain region

Continuation of the front page (56) Reference JP-A-5-21762 (JP, A) JP-A-7-94738 (JP, A) JP-A-5-3322 (JP, A) JP-A-4-313242 (JP , A) JP-A-7-335888 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (5)

(57) [Claims] 1. An n-type first film formed on a first insulating film.
On the first insulating film with the n-type first semiconductor region interposed therebetween.
A source region formed of the p-type first semiconductor region and
And fine drain region, a first semiconductor region of the second insulating film and the n-type through the second insulating film as the first gate insulating film formed over the semiconductor region of the n-type a gate electrode to control current flow through each of the upper portion of the source region and the drain region
And a second semiconductor region having a forbidden band width smaller than that of the first semiconductor region formed in . Wherein said and said n-type first semiconductor region of the p
The semiconductor device according to claim 1, wherein the first semiconductor region of the mold has the same thickness . 3. The first semiconductor region is made of silicon (S
3. The semiconductor device according to claim 1 or 2, wherein the second semiconductor region acts so as to generate strain in a direction in which the lattice constant of Si expands. 4. The first semiconductor region is made of silicon (S
i), wherein the second semiconductor region is Si _x Ge _1-x
Or Si _x Sn _1-x.
Alternatively, the semiconductor device according to item 2. 5. A second semiconductor region above the source region.
The source metal electrode is in contact with the region,
The drain metal electrode is in contact with the second semiconductor region here
The semi-finished product according to any one of claims 1 to 4, characterized in that
Conductor device.