JP3376209B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double diffusion type insulated gate field effect transistor, and in particular, it has a reverse withstand voltage characteristic similar to that of a conventional double diffusion type insulated gate field effect transistor without increasing the chip size. It is concerned with keeping the same and simplifying the element forming process.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional double-diffused MOSFET (Double-diffused MOSFET).
Hereafter, a cross-sectional view of a chip terminal portion of the DMOSFET) will be shown. A channel stopper region 22 is provided in the chip end portion in addition to the FET cell region 21.

The manufacturing process of this DMOS transistor will be described below. First, the N-epitaxial layer 2 is formed on the high-concentration N + substrate 1 to form an N-type semiconductor substrate. A field oxide film 3 is formed on the entire surface of this semiconductor substrate, and F
The field oxide film 3 in the ET cell region 21 is removed. At this time, the channel stopper region 22 remains covered with the field oxide film 3.

After that, a gate insulating film 6 is formed in the FET cell region 21, polysilicon is deposited on the gate insulating film 6, and phosphorus is diffused to reduce the resistance value of the polysilicon. After that, patterning is performed using the photolithography technique to form the gate electrode 7.

Then, for example, boron ions are ion-implanted into the N-region 2 in a self-aligning manner with the gate electrode 7 and thermal diffusion is performed to form a P-type base diffusion region 4. Then, a resist is applied and patterning is performed so as to open the channel stopper region, and the field oxide film in the channel stopper region is removed.

Subsequently, for example, arsenic is ion-implanted to perform thermal diffusion, and the N + source diffusion region 5 is formed in the FET cell region 21.
At the same time that the N + is formed in the channel stopper region 22.
The diffusion region 9 is formed.

After that, an oxide film is deposited by the CVD method to form an interlayer insulating film 8, a contact is opened in this interlayer insulating film, and a source electrode 11 connected to the N + source diffusion region of the FET cell region 21 is formed. , Channel stopper area 2
A drain electrode 10 connected to the second N + diffusion region 9 is formed.

The N + diffusion region 9 of the channel stopper region is provided so as to surround the FET cell region, and the drain electrode 10 connected to the FET cell region is arranged in a circle. The channel stopper region stabilizes the reverse breakdown voltage characteristic between the source and the drain.

[0009]

DISCLOSURE OF THE INVENTION Conventional DMOSFET
, The FET cell region 21 is formed by the N− type substrate, the P type base diffusion region 4, and the N + type source diffusion region 5, while the channel stopper region is formed at the same time as the N + type source diffusion region 5. It is formed of the N + type diffusion region 9. As described above, in order to simultaneously form the diffusion region 9 in the channel stopper region and the source diffusion region 5 in the FET cell region, it is necessary to remove the thick field oxide film 3 in the channel stopper region. Therefore, the lithography process for removing the field oxide film is required at least once, which complicates the process and increases the production cost.

In view of the above problems, the present invention simplifies the device forming process while simultaneously forming the channel stopper region and the FET cell region in the same lithography process while maintaining the conventional reverse withstand voltage characteristic between the drain and the source. The purpose is to

[0011]

The present invention SUMMARY OF] In order to solve the above problems, a semiconductor substrate, a front Symbol semiconductor layer of a first conductivity type formed in the upper surface of the semiconductor substrate, spaced apart by a field insulating film a cell region and a channel stopper region provided, a semi-conductor cells formed in the cell region, the formed on the surface region of the channel stopper region, the second conductivity type surrounding said cell region and the field insulating film The first impurity diffusion layer, the second impurity diffusion layer of the first conductivity type formed in the surface region of the first impurity diffusion layer, and at least between the first impurity diffusion layer and the field insulating film. A first insulating film, a first electrode formed on the first insulating film, the second impurity diffusion layer , the first
Have a second electrode electrically connected to the electrode, the second
The electrodes and the semiconductor substrate are electrically connected . Also books
A semiconductor device of the invention comprises a semiconductor substrate and the semiconductor substrate
A first conductive type semiconductor layer formed on the upper surface and a field
A cell region and a channel provided separated by an insulating film
Gate stopper formed in the cell stopper area and the cell area.
Edge film and gate electrode formed on the gate insulating film
And a second conductivity type formed on the surface region of the cell region.
A base diffusion region and a base diffusion region formed in the base diffusion region.
First conductivity type source diffusion region and the channel stopper
Formed on the surface region of the region,
Second conductivity type first impurity diffusion layer surrounding the field insulating film
And a first layer formed on the surface region of the first impurity diffusion layer.
A conductive type second impurity diffusion layer, and at least the first impurity
Formed between the object diffusion layer and the field insulating film.
1. Insulating film and first electrode formed on the first insulating film
And electrically contact the second impurity diffusion layer and the first electrode.
A drain electrode connected to the drain electrode, and
The semiconductor substrates are electrically connected.

Further, the method of manufacturing a semiconductor device of the present invention
Includes a step of forming a field insulating film provided on the semiconductor substrate so as to separate the cell region and the channel stopper region, a step of forming a gate insulating film in the cell region and the channel stopper region, and When a first gate electrode is formed on the formed gate insulating film ,
Both gates formed in the channel stopper region
A second gate electrode on the insulating film and the field insulating film
And a step of forming a front Symbol first and second gate electrodes and self-aligned ion implantation, by thermal diffusion, forming a first impurity diffusion layer of the second conductivity type, said first the surface area of the impurity diffusion layer, the first and second to the gate electrode self-alignment with inlet ions Note, forming a second impurity diffusion layer of the first conductivity type, at least said second gate electrode And a step of forming an interlayer insulating film having a contact opening in the second impurity diffusion layer, and a step of forming a wiring connecting the second gate electrode and the second impurity diffusion layer formed in the channel stopper region. It is equipped with.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.
FIG. 1 shows a cross section of a chip termination portion of a DMOSFET.
Hereinafter, the same components as those in FIG. 2 are designated by the same reference numerals, and description thereof will be omitted.

The manufacturing process of the DMOS transistor of the present invention will be described below. First, the N− epitaxial layer 2 is formed on the high concentration N + substrate 1 to form an N-type semiconductor substrate. Then, a field oxide film 3 is formed on the entire surface of this semiconductor substrate. After that, the field oxide film 3 in the FET cell region 21 and the chip termination region 23 is removed.

Subsequently, gate insulating films 6 and 16 are formed in the FET cell region 21 and the chip termination region 23, respectively,
Polysilicon is grown on the gate insulating films 6 and 16 by, for example, the CVD method. After that, patterning is performed using the photolithography technique to form the gate electrodes 7 and 17. At this time, the polysilicon 17 at the end of the chip is FE
It is separated from the gate polysilicon 7 in the T cell region 21,
Patterning is performed so that a part thereof exists on the field oxide film 3 and another part exists on the gate oxide film 16.

Then, using the polysilicon electrodes 7 and 17 as a mask, the P type base diffusion regions 4 and 14 and the N type source.
The drain diffusion regions 5 and 15 are sequentially formed by using the ion implantation technique and the thermal diffusion technique.

Subsequently, an interlayer insulating film 8 is deposited and a contact is opened. At the chip termination 23, the contacts are
It is opened on the N-type diffusion region 15 and the polysilicon electrode 17. Then, a metal such as Al is deposited by a sputtering method and patterned to form an electrode. Chip termination 2
3, the N type diffusion region 15 and the polysilicon electrode 17 are connected to the same drain electrode 10.

In this embodiment, when a reverse bias is applied to the drain electrode, as shown in FIG. 3B, the gate insulating film 1 under the polysilicon electrode 17 at the chip termination portion is formed.
Electrons are accumulated in the substrate under 6 and the conductivity type is N- to N +.
Change to. As a result, the chip end portion can function as a channel stopper, as in the case where the drain of the conventional channel stopper structure shown in FIG. 3A is reverse biased. Reference numeral 12 in FIG. 3 denotes a depletion layer, and 13 denotes an electron storage layer.

The polysilicon electrode at the end of the chip needs to be arranged at an appropriate position and with an appropriate length so as to function as a channel stopper. In particular, FIG.
The length of the storage layer 13, which is represented by AA ′ in (a) and in which electrons are stored and the N− substrate changes to N + when a reverse bias is applied, needs to be set appropriately. For example, N
-If the resistivity of the substrate is 20 Ω · cm, the distance AA ′ must be 15 μm or more. If this distance is short,
As shown in (b), when a reverse bias is applied to the drain, the depletion layer 12 extending from the FET cell region reaches the P-type diffusion region at the end of the chip, and the reverse bias leak current between the drain and the source. Will occur. Figure 5
4A and FIG. 5B show the reverse breakdown voltage characteristics of FIG. 4A and FIG. 4B, respectively. The edge of the polysilicon electrode 17 at the end of the chip is always the field oxide film 3
Must be on top. If the polysilicon electrode 17 is not on the field oxide film 3, a P-type region is formed between the polysilicon electrode 17 and the field oxide film 3,
It no longer serves as a channel stopper. Further, there arises a problem of reverse breakdown voltage reliability. The N-channel type DMOSFET has been described above.
The present invention can be applied to FETs and IGBTs.

[0020]

As described above, the DMOS of the present invention.
At the same time when the FET cell is formed,
By forming the region having the function of the channel stopper of the OS structure, it is possible to simplify the manufacturing process and reduce the production cost while securing the reverse breakdown voltage characteristic between the drain and the source as in the conventional case.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional DMOSFET.

FIG. 3 is a diagram showing a state when a reverse bias voltage is applied to a DMOSFET.

FIG. 4 is a diagram showing a state when a reverse bias voltage is applied to the DMOSFET.

FIG. 5 is a diagram showing reverse breakdown voltage characteristics.

[Explanation of symbols]

1 ... High-concentration silicon substrate, 2 ... Epitaxial layer, 3 ... Field insulating film, 4 ... Base diffusion region, 5 ... Source diffusion region, 6 ... Gate oxide film, 7 ... Gate electrode, 8 ... Interlayer insulating film, 9 ... diffusion area, 10 ... drain electrode, 11 ... Source electrode, 12 ... Depletion layer, 13 ... Storage layer.

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (8)

(57) [Claims] 1. A semiconductor substrate, a first conductivity type semiconductor layer formed on the upper surface of the front Symbol semiconductor substrate, the cell region and a channel stopper region formed spaced apart by a field insulating film, said cell area a semi-conductor cell formed, the channel is formed in the surface region of the stopper region, the cell region and the field insulation and the first impurity diffusion layer of the second conductivity type surrounding the film, the surface of the first impurity diffusion layer A second impurity diffusion layer of the first conductivity type formed in the region, a first insulating film formed at least between the first impurity diffusion layer and the field insulating film, and on the first insulating film Electrically connected to the formed first electrode, the second impurity diffusion layer , and the first electrode.
The second and the electrodes possess, the said second electrode semiconductor substrate
Is a semiconductor device that is electrically connected . 2. A semiconductor substrate, a first conductivity type semiconductor layer formed on the upper surface of the front Symbol semiconductor substrate, the cell region and a channel stopper region formed spaced apart by a field insulating film, said cell area The formed gate insulating film, the gate electrode formed on the gate insulating film, the second conductivity type base diffusion region formed in the surface region of the cell region, and the base diffusion region formed in the base diffusion region. A first conductivity type source diffusion region, a second conductivity type first impurity diffusion layer formed in a surface region of the channel stopper region and surrounding the cell region and the field insulating film, and the first impurity diffusion layer A second impurity diffusion layer of a first conductivity type formed in a surface region of the first insulation film; a first insulation film formed at least between the first impurity diffusion layer and the field insulation film; A first electrode formed on the insulating film, the second impurity diffusion layer, electrically connected is to the first electrode
The have a drain electrode, the drain electrode and the half
A semiconductor device in which the conductor substrate is electrically connected . One end of claim 3 wherein said first insulating film, a semiconductor device according to claim 1 or 2, characterized in that provided in contact with the field insulating film. 4. The other end of the first insulating film is formed on the first end of the first insulating film.
The semiconductor device according to claim 3, wherein the semiconductor device is provided on the impurity diffusion layer, and the second electrode is provided on the first insulating film. 5. The semiconductor device according to claim 3, wherein one end of the second electrode is formed on the field insulating film. 6. The semiconductor layer of the first conductivity type is 20 Ω · c.
3. The semiconductor device according to claim 1 , wherein when the thickness is m, the length of the first insulating film is 15 μm or more. 7. The semiconductor device according to claim 1, wherein the first electrode and the second electrode have substantially the same potential. 8. A step of forming a field insulating film provided on a semiconductor substrate so as to separate the cell region and the channel stopper region, a step of forming a gate insulating film in the cell region and the channel stopper region, A first gate electrode is formed on the gate insulating film formed in the cell region, and the channel stopper is formed.
Gate insulating film formed in the region and the field insulation
Forming a second gate electrode on the membrane, prior to SL and the first and second gate electrodes and self-aligned ion implantation, by thermal diffusion, the first impurity diffusion layer of the second conductivity type And a step of forming the first and second impurity diffusion layers on the surface region of the first impurity diffusion layer.
It entrance gate electrode and a self-aligned manner ions Note, forming a second impurity diffusion layer of the first conductivity type, an interlayer having a contact opening in at least the second gate electrode and said second impurity diffusion layer A method of manufacturing a semiconductor device, comprising: a step of forming an insulating film; and a step of forming a wiring connecting the second gate electrode and a second impurity diffusion layer formed in a channel stopper region.