JP3374534B2 - Method for manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor having ion-implanted source / drain regions.

[0002]

2. Description of the Related Art A thin film transistor, especially a polysilicon thin film transistor having ion-implanted source / drain regions is characterized in that a large leak current occurs when the gate voltage is reverse biased, and this leak current is reduced. An offset gate structure is considered as one method. The offset gate structure is a structure in which the gate electrode is formed smaller than the channel region between the source / drain regions, and the length of the channel region portion protruding outward from both side ends of the gate electrode is called an offset length.

A thin film transistor having such an offset gate structure is conventionally manufactured as follows. First, a polysilicon layer is patterned on an insulating substrate such as ceramic or glass, and a gate insulating layer is formed thereon.
Further, a photoresist pattern is formed on the gate insulating layer by the photolithography method, and ions are implanted using the photoresist pattern as a mask to form source / drain regions in the polysilicon layer. Next, after removing the photoresist pattern, a gate electrode forming layer of aluminum or the like is formed on the gate insulating layer, and a photoresist pattern is formed again thereon by the photolithography method.
At this time, the photoresist pattern is made smaller than the channel region between the source / drain regions. Then, the gate electrode forming layer is etched by using this photoresist pattern as a mask to form the gate electrode smaller than the channel region, thereby completing the thin film transistor having the offset gate structure.

[0004]

However, in the conventional manufacturing method as described above, a photolithography process is required twice in total to form the source / drain regions and the gate electrode in order to obtain the offset gate structure. However, there is a problem that the process is complicated and long. Further, if the offset length is too long, the on-current of the transistor is lowered, so 1 μm or less is desirable. However, in the above conventional manufacturing method, the offset length is determined in relation to the two photolithography steps. In order to obtain a fine offset length, there is a drawback that high alignment accuracy and processing accuracy are required in each photolithography process. An object of the present invention is to provide a gate electrode side end and a source electrode.
It is an object of the present invention to provide a method of manufacturing a thin film transistor in which the length between drain regions can be easily and accurately formed and the number of photolithography steps can be reduced.

[0005]

The present invention provides a semiconductor layer,
After forming the gate insulating layer, a gate electrode forming portion is formed in a predetermined shape on the gate insulating layer, and the gate insulating layer is etched using the gate electrode forming portion as a mask to form a lower side of the gate electrode forming portion. While forming an undercut portion in the, by implanting ions into the semiconductor layer using the gate electrode formation portion as a mask, then by etching the overhang portion of the gate electrode formation portion corresponding to the undercut portion, The gate electrode is formed to be narrower than the gate electrode forming portion.

[0006]

According to the present invention, the length of the channel region between the source and drain regions is determined by the width of the gate electrode forming portion, and the offset length is the length of the channel region portion protruding outward from both side ends of the gate electrode. Is almost equal to the protrusion width of the overhang portion of the gate electrode formation portion corresponding to the undercut portion formed in the gate insulating layer, and the offset length is easily and accurately self-aligned by the etching amount of this overhang portion. In addition, the photolithography process is performed only once when the gate electrode formation portion is formed, which simplifies and shortens the manufacturing process.

[0007]

1 to 4 are sectional views showing an embodiment of the present invention in the order of manufacturing steps. An embodiment will be described below with reference to these drawings. First, as shown in FIG. 1, a polysilicon layer 2 is patterned on an upper surface of an insulating substrate 1 made of ceramic or glass. Next, as shown in FIG. 2, a gate insulating layer 3 made of silicon oxide or the like is formed on the entire surface, and the gate insulating layer 3 is used to form the polysilicon layer 2
Cover. Further, a gate electrode film made of chromium or the like is formed on the gate insulating layer 3, a photoresist is formed on the gate electrode film, and the gate electrode forming portion 4 is formed in a predetermined shape by the upper photolithography technique.

Next, the gate insulating layer 3 is etched by using the gate electrode forming portion 4 as a mask to reduce the film thickness of the gate insulating layer 3 as shown in FIG. The cut portion 3a is formed. Here, when the gate electrode forming portion 4 is used as a mask,
The photoresist (not shown) remaining on the gate electrode formation portion 4 may remain or may be removed. The etching at this time is preferably isotropic dry etching, for example, plasma etching of an anode couple using CF ₄ + O ₂ gas, but anisotropic dry etching or wet etching may be used. After that, impurities are ion-implanted into the polysilicon layer 2 using the gate electrode formation portion 4 as a mask, and a heat treatment is performed to activate the source / drain regions 5. As a result, a pair of source / drain regions 5 are formed in the polysilicon layer 2 so as to be separated from each other by the width of the gate electrode formation portion 4, and a portion corresponding to the width of the gate electrode formation portion 4 between the source / drain regions 5 is formed. Becomes the channel region 6.

Next, by uniformly etching the surface of the gate electrode forming portion 4, the overhang portion 4a and the upper portion of the gate electrode forming portion 4 corresponding to the undercut portion 3a of the gate insulating layer 3 are evenly removed. The gate electrode 7 corresponding to the width between the undercut portions 3a of the gate insulating layer 3 is formed. The etching at this time is isotropic etching, for example, wet etching is preferable, but isotropic dry etching may be used. As a result, an offset gate structure in which the gate electrode 7 is smaller than the channel region 6 is obtained. Here, the length between the side edge of the gate electrode 7 and the source / drain region 5, that is, the offset length, is set in the overhang portion 4a of the gate electrode formation portion 4 corresponding to the undercut portion 3a of the gate insulating layer 3. Almost match. In this method, since the offset length is determined by the etching amount of the overhang portion 4a of the gate electrode forming portion 4, the offset length can be accurately controlled by controlling the etching time, which facilitates the offset length in a self-aligned manner. And it can be formed with high definition.

After the offset gate structure is formed in this way, the interlayer insulating film 8 is formed on the entire surface as shown in FIG. Then, a contact hole 9 is formed in the interlayer insulating film 8 and the gate insulating layer 3 so as to reach the source / drain region 5 of the polysilicon layer 2, and is further connected to the source / drain region 5 through the contact hole 9. The source / drain electrodes 10 are formed. Thus, a thin film transistor having an offset gate structure is completed.

The present invention is not limited to the above embodiment,
For example, by using the gate electrode formation portion 4 formed on the gate insulating film 3 as a mask, a high-concentration impurity is injected into the polysilicon layer 2, and the gate electrode formation portion 4 is etched to form a gate electrode 7 as a mask. When the low-concentration impurity is implanted into the silicon layer 2, the source / drain region 5 becomes a high-concentration impurity region, and the polysilicon layer 2 corresponding to the portions protruding outward from both side ends of the gate electrode 7 between the high-concentration impurity regions. It is possible to obtain a thin film transistor having an LDD structure in which a low-concentration impurity region is formed.

In the above embodiment, the impurities are injected into the polysilicon layer 2 after the gate insulating layer 3 is etched. However, the present invention is not limited to this, and the polysilicon layer 2 is previously doped with the gate electrode forming portion 4 as a mask. After implanting, the gate insulating layer 3 may be etched using the gate electrode forming portion 4 as a mask.

[0013]

As described above, according to the present invention, the undercut portion is formed under the gate electrode forming portion that determines the length of the channel region between the source / drain regions, and the undercut portion is provided. By etching the overhang portion of the gate electrode forming portion, a fine offset length can be formed easily and highly accurately in a self-aligning manner. Therefore, the thin film transistor formed by the method of the present invention can suppress a leak current when a reverse bias is applied and can have a large ON current, and can be used for a driver such as a liquid crystal display. Further, according to the present invention, the photolithography process is performed only once when forming the gate electrode forming portion,
The manufacturing process can be simplified and shortened.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step in one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step that follows FIG. 1 in an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step that follows the step of FIG. 2 in one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step that follows FIG. 3 in one embodiment of the present invention.

[Explanation of symbols]

2 Polysilicon layer 3 Gate insulation layer 4 Gate electrode formation part 4a Overhang part 5 Source / drain regions 6 channel area 7 Gate electrode

Claims (3)

(57) [Claims] 1. After forming a semiconductor layer and a gate insulating layer,
A gate electrode formation portion is formed in a predetermined shape on the gate insulation layer, and the gate insulation layer is etched using the gate electrode formation portion as a mask to form an undercut portion under the gate electrode formation portion. A gate electrode narrower than the gate electrode forming portion by ion-implanting into the semiconductor layer using the gate electrode forming portion as a mask and etching an overhang portion of the gate electrode forming portion corresponding to the undercut portion. Forming a thin film transistor. 2. A high concentration impurity is ion-implanted into the semiconductor layer using the gate electrode forming portion as a mask, and a low concentration impurity is added to the semiconductor layer using the gate electrode formed narrower than the gate electrode forming portion as a mask. 2. The method of manufacturing a thin film transistor according to claim 1, further comprising ion implantation. 3. The method of manufacturing a thin film transistor according to claim 1, wherein after the gate insulating layer is etched using the gate electrode forming portion as a mask, ions are implanted into the semiconductor layer.