JP3370776B2 - PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a codec, receiver,
PLL (Phase Lo) used for clock generators, etc.
cked Loop ) circuit.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional PLL circuit. The PLL circuit includes a phase comparator 10 and a charge pump circuit (hereinafter simply referred to as a charge pump) 2 .
0, a low-pass filter 30, a voltage controlled oscillator (hereinafter, VCO referred.) 40, and a frequency divider 50. The output side of the charge pump 20 is a low pass filter 3
It is connected to 0. The phase comparator 10 has an input terminal In
It is to compare the phase and frequency of the input signal Si and the feedback signal Sr inputted from. The charge pump 20 constitutes a path for charging and discharging the charges to the low-pass filter 30 in accordance with the output of the phase comparator 10, low pass filter 30 is a function of generating an output voltage that is smoothed by charging and discharging the charge Have The charge pump 20 is in series connected PMOS power source <br/> conductive position Vdd to the ground conductive position GND
21 and NMOS 22. Each PMOS 21 and N
The two outputs of the phase comparator 10 are input to the gate of the MOS 22, and the drains of the PMOS 21 and the NMOS 22 are connected at the node N20. The node N20 is connected to the low pass filter 30. Low pass filter 30
Has two resistors 31, 32 and a capacitor 33. One of the two terminals of the resistor 31 has a node N20.
And the other terminal is connected to the output node N30 for the VCO 40. Resistor 32 and capacitor 33
Are connected in series between the output node N30 and the ground potential GND.

Output node N30 of the low-pass filter 30
Is connected to the VCO 40, the output of the VCO 40 of this is output to the outside through the output terminal Out. Also, VCO4
A part of the output of 0 is supplied to the frequency divider 50, and the frequency divider 5
The signal Sr, which is an output of 0, is fed back to the phase comparator 10. The VCO 40 generates an oscillation frequency according to the output voltage of the low pass filter 30, and the frequency divider 50 operates as the VCO 40.
The frequency of the generated oscillation frequency is divided.

Next, the operation of the PLL circuit of FIG. 2 will be described. The phase comparator 10 compares the input signal Si with the feedback signal Sr, and supplies the phase difference signal Su to the gate of the PMOS 21 during the period in which the phase of the input signal Si is advanced with respect to the feedback signal Sr. The phase difference signal Sd is applied to the gate of the NMOS 22 during the period in which the phase is delayed with respect to the feedback signal Sr. The charge pump 20 is the phase comparator 1
Upon receiving the phase difference signals Su and Sd from 0, the PMOS 21 and the NMOS 22 are turned on and off. Therefore, the voltage of the node N20 changes. The capacitor 33 of the low-pass filter 30 charges and discharges the electric charge from the charge pump 20, and the low-pass filter 30 smoothes the voltage change of the node N20 and supplies it to the VCO 40. The VCO 40 oscillates and outputs at a frequency according to the output voltage of the smoothed low-pass filter 30, and also feeds back the oscillation frequency to the phase comparator 10 via the frequency divider 50. In this way, the phase and frequency of the input signal Si and the feedback signal Sr are locked.

In the PLL circuit of FIG. 2, when the PMOS 21 or the NMOS 22 in the charge pump 20 is turned on after locking, ripple noise occurs in the output voltage of the low pass filter 30 . The magnitude of this ripple noise Δv
Is dependent on the output voltage Vo of the low pass filter 30 after being locked, and is expressed by the following equations (1) and (2). However, R1 and R2 in the equations (1) and (2) are the resistance values of the resistors 31 and 32, respectively. When the PMOS 21 is turned on, Δv = R2 (Vdd−Vo) / (R1 + R2) (1) When the NMOS 22 is turned on, Δv = R2 (−Vo) / (R1 + R2) (2)

When the output voltage Vo of the low pass filter 30 after locking is a low voltage, the PMOS of the charge pump 20 is
When 21 is turned on, ripple noise is largely generated in the plus direction. When the NMOS 22 is turned on, ripple noise is small in the negative direction. On the contrary,
If the PMOS 21 of the charge pump 20 is turned on when the output voltage Vo of the low-pass filter 30 after locking is a high voltage, the lip noise is small in the plus direction, and N
When the MOS 22 is turned on, ripple noise is largely generated in the negative direction. The magnitude Δv of these ripple noises is transmitted to the VCO 40, and frequency jitter occurs.

In the conventional PLL circuit of FIG. 2, the drive capability of the charge pump 20 is lowered or the resistance value R1 of the resistor 31 in the low pass filter 30 is increased in order to prevent the occurrence of frequency jitter. By these, the magnitude Δv of the generated ripple noise is reduced.

[0008]

However, the conventional PLL circuit has the following problems. In order to prevent the occurrence of frequency jitter, the drive capability of the charge pump 20 is lowered, and the resistor 31 in the low pass filter 30 is used.
Although the resistance value R1 is increased, the charge / discharge ability of the low-pass filter 30 is impaired in any case. Therefore, there is a problem that the time required to lock the phase and frequency (lock-in time) increases,
There was a limit to the reduction of ripple noise.

[0009]

To solve the previous SL problems SUMMARY OF THE INVENTION The first aspect of the present invention, the input signal and the feedback signal
And a phase difference signal which is the comparison result is generated.
Based on the phase comparator and the phase difference signal,
According to the first potential or the second potential according to the ground potential.
The charge pump for outputting and the first or second potential
Low-pass filter for smoothing, and the low-pass filter
Oscillates at a frequency corresponding to the output potential, the raw pre Symbol feedback signal
And a VCO that outputs the oscillation frequency to the outside
In the provided PLL circuit, the charge pump is
Is configured as follows.

The charge pump includes a first charge transfer path constituted by a first switching element connected between the power supply potential and an output section of the charge pump, and the ground potential and the charge pump. It has a second charge transfer path constituted by a second switching element connected to the output section. And
When the output potential of the low pass filter is higher than a predetermined potential
Kiniwa, the on-resistance of the first switching element is lowered, and the on-resistance value of the second switching element is increased, the output potential of the low-pass filter
Is lower than a predetermined potential, the ON resistance value of the first switching element increases and the ON resistance value of the second switching element decreases.

A second invention relates to the PLL circuit of the first invention.
At the output voltage of the low-pass filter.
There is a bias generator circuit that generates the bias potential.
Depending on the bias potential, the first and second switches
In the configuration where the ON resistance value of the switching element is controlled
Has become.

A third invention is a PLL circuit according to the second invention.
, Based on the input signal and the feedback signal,
Note Sends the detection result of whether the PLL circuit is in the locked state.
A lock detector is provided, and the lock detector is
The conduction state in the first and second charge transfer paths is controlled.
It is designed to be controlled.

A fourth invention provides a PLL circuit according to the third invention.
The charge pump is connected to the power supply potential and the charge
The first switch between the charger pump and the output section.
A third switch connected in parallel with the ching element.
Third charge transfer path constituted by a switching element, and
Between ground potential and the output of the charge pump
Is connected in parallel to the second switching element.
A fourth switching element formed by
Has a charge transfer path, a charge transfer of the third and fourth
The conduction state in the moving path is determined by the lock detection unit.
It is controlled.

A fifth invention is a PLL circuit according to the fourth invention.
Before the PLL circuit is locked, the
The third and fourth charge transfer paths become conductive, and
Note that the first and second charge transfer paths become non-conducting
After the PLL circuit is locked, the third and
The fourth charge transfer path becomes non-conductive, and
And the second charge transfer path becomes conductive.
There is.

According to a sixth aspect, the PLL circuit according to the fourth aspect.
Is the first switch in the first charge transfer path.
Between the switching element and the output of the charge pump
A fifth switching element connected to the second switching element and the second switching element.
In the load transfer path, in front of the second switching element
A sixth connected to the output of the charge pump.
And a switching element of, and the fifth and sixth
ON resistance value of the switching element is
The configuration is controlled by the detection unit.

A seventh invention is a PLL circuit according to the sixth invention.
Before the PLL circuit is locked,
The fifth and sixth switching operations by the lock detector
The on resistance value of the element rises, and the PLL circuit is
After the lock state is reached, the lock detector detects the
The ON resistance values of the fifth and sixth switching elements are
It is configured to descend.

[0017]

According to the first to seventh inventions, as described above, the PL
Since the L circuit is configured, the phase comparator compares the phase and frequency of the input signal and the feedback signal, and generates the phase difference signal according to the comparison result . A charge pump to form a first or second charge transfer path based on the phase difference signal. B over path <br/> pass filter generates a voltage smoothed by charging and discharging the electric charge from the charge pump, oscillates at a frequency the VCO corresponding to the output voltage of the low-pass filter.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a PLL circuit showing an embodiment of the present invention, in which elements common to FIG.

[0019] The PLL circuit 2 and the same position phase comparator 1 0, in addition to having a low-pass filter 3 0, VCO 40 and a frequency divider 50, unconventional lock detector 6 0, the charge pump 70 and the bias A generation circuit 80 is provided . Input signal Si from input terminal In and feedback signal S
r is input to the phase comparator 10, a charge pump 70 is connected to the output side of the phase comparator 10. Also,
Input signal Si and the feedback signal Sr is input to the lock detector 60. The lock signal output from the lock detector 60
Issue step S60 is branched into two, one is via the inverter 65, the input is branched further into two to the charge pump 70
Ru is. The lock signal S output from the lock detector 60
60 other are also further input to the input terminal of the branch directly charge pump 70 into two. Charge pump 70
Of the output side, a low-pass filter 3 for outputting a voltage smoothing the charge and discharge from this charge pump 70
0 is connected . Output No of the low-pass filter 30
De N30, the the VCO40 which oscillates on the basis of the output voltage of the low-pass filter 30 is connected to the input terminal of the bias generating circuit 80. The output side of the VCO 40 is
While being connected to the output terminal Out of this PLL circuit,
It is connected to the frequency divider 50. Divider 50 is VCO 40
The frequency of the oscillation frequency is divided, and the feedback signal Sr output from the frequency divider 50 is fed back to the phase comparator 10 and the lock detector 60. The output node N80 of the bias generation circuit 80 is connected to the charge pump 7
It is connected to the 0 input terminal.

The charge pump 70 comprises four PMOSs 71
.About.74 and four NMOSs 75 to 78. First
The source of the PMOS 71, which is the switching element of the
It is connected to a power supply conductive position Vdd, PMOS 71
The output voltage of the bias generation circuit 80 is input to the gate of
Be done . The drain of the PMOS 71 is the fifth switching element.
It is connected to the source of the child PMOS72,
The lock signal S60 is returned to the gate of 2 by the inverter 65 .
Been rolling is input. P which is the third switching element
The source of MOS73 is connected to the power supply power level Vdd, PM
To the gate of the OS73 lock signal S60 is input.
The drains of PMOS 72 and PMOS 73 are both PMOS
Is connected to the 74 source, the gate of the PMOS74 this, the phase difference signal Su is input outputted from the phase comparator 10
Ru is a force. NMOS 75 which is the second switching element
The source is connected to the ground potential GND Ru second power der, the output node N80 of the bias generating circuit 80 is connected to the gate of the NMOS 75. The drain of the NMOS 75 is connected to the source of the NMOS 76 which is the sixth switching element, and the gate of the NMOS 76 has a lock signal.
Issue S60 is input. The source of the fourth is a switching element NMOS77 is connected to the ground conductive position GND, N
The output of the input of the inverter 65 to the gate of the MOS77
Be done . The drains of the NMOS 76 and the NMOS 77 are both N
Is connected to MOS78 source to the gate of NMOS78 this, the phase difference signal S output from the phase comparator 10
d is are entered. Drains of PMOS74 and NMOS78 is connected with the output node N70, the output node N7
It is connected to the 0 Gallo-pass filter 30.

Here, the power supply potential Vdd and the node 70
The PMOS 71 and 72 connected between the
A load transfer path is formed, and the ground potential GND and the node 70 are connected to each other.
A second by an NMOS 75 and 76 connected between
A charge transfer path is formed, and the power supply potential Vdd and the node 70 are formed.
The third charge transfer is performed by the PMOS 73 connected between
A moving path is formed between the ground potential GND and the node 70.
The fourth charge transfer path by the NMOS 77 connected to the
Is configured.

The low-pass filter 30 includes two resistors 3
1, 32 and a capacitor 33. 2 of resistance 31
One of the terminals is connected to the node N70, and the other terminal is the output node N30 of the low-pass filter 30.
It is connected to the VCO 40 and the bias generation circuit 80 via . The resistor 32 and the capacitor 33 are connected to the output node N3.
It is connected in series between 0 and the ground potential GND. Bias generation circuit 80 has a PMOS81 and NMOS82 connected in series between the ground conductive position GND to the power supply conductive position Vdd. The source of the PMOS81 is connected to the power supply conductive position Vdd, NM Drain PMOS81 the output node N80
It is connected to the drain of the OS 82. The gate of the PMOS 81 is connected to the output node N80. Also, N
The source of MOS82 is connected to the ground conductive position GND, the gate of the NMOS82 is connected to the output node N30
There is. The output node N80 is PM in the charge pump 70.
It is connected to the gates of the OS 71 and the NMOS 75.

Next, the operation of the PLL circuit of FIG. 1 will be described. The phase comparator 10 detects a phase shift between the input signal Si and the feedback signal Sr, and supplies the phase difference signal Su to the gate of the PMOS 74, for example, while the phase of the input signal Si leads the feedback signal Sr. Then, while the phase of the input signal Si is delayed with respect to the feedback signal Sr, the phase difference signal Sd is given to the gate of the NMOS 78. Lock detector 60
Is a circuit for detecting the locked state of the PLL circuit. That is, the lock detection unit 60, if the phase shift between the input signal Si and the feedback signal Sr is less than or equal to the set value, indicates "1" indicating a match, and if it exceeds the set value, indicates a lock signal S60 indicating a mismatch. Is output. When the phases of the input signal Si and the feedback signal Sr do not match, P in the charge pump 70
One of the MOS 74 and the NMOS 78 is turned on based on the phase difference signals Su and Sd to form a charge transfer path. This charges and discharges the capacitor 33,
The voltage smoothed by the low-pass filter 30 is applied to the node N30.
The output from. VCO40 outputs the oscillation frequency oscillates based on <br/> output voltage of the low-pass filter 30 through the output terminal Out, through the frequency divider 50 phase
The feedback signal Sr is fed back to the comparator 10 and the lock detector 60.

When the capacitor 33 is charged and discharged,
Before locking, the PMOS 73 and the NMOS 77 are turned on by the lock signal S60, and the PMOS 72 and the NMOS 76 are turned on.
Is turned off. Conversely, after locking, the PMOS 73 and NM
OS77 is turned off by the lock signal S60, and PMO
The S72 and the NMOS 76 are turned on. As a result, the charge / discharge path of charge, that is, the charge transfer path is switched.
The charge / discharge path after locking includes the PMOS 71 and the NMOS 75 in the ON state, and these operate as a charge limiting element. That is, the on-resistance of the PMOS 71 and the NMOS 75 is controlled by the output voltage of the bias generation circuit 80. The bias generation circuit 80 generates a voltage corresponding to the output voltage of the low pass filter 30. That is, when the voltage of the output node N30 of the low-pass filter 30 is low, NM
The on resistance of the OS 82 rises, and the voltage of the node N80 rises. Therefore, the PMOS 7 in the charge pump 70
The ON resistance of 1 rises, and at the same time, the ON resistance of the NMOS 75 drops. Therefore, after locking, the PMOS 74 is turned on and the ripple noise in the plus direction of the output node N30 of the low pass filter 30 is reduced. Conversely, when the voltage of the output node N30 of the low-pass filter 30 is high, the voltage of the node N80 drops, and the NM in the charge pump 70 is reduced.
The on-resistance of OS75 becomes high. Therefore, even if the NMOS 78 is turned on after the lock, the ripple noise in the negative direction of the output node N30 of the low pass filter 30 is reduced. By reducing these ripple noises, the input voltage of the VCO 40 after locking, that is, the voltage fluctuation of the node N30 is reduced, and the frequency jitter is reduced.

[0025] As described above, in this embodiment, by detecting the locked state by the lock detecting unit 60, switching to give a discharge path for the charge for the low-pass filter 30 before and after the locking, in the bias generation circuit 80 after the lock, Charge pump 70
To control. Therefore, the output voltage of the low pass filter 30 is stabilized and the oscillation frequency of the VCO 40 is stabilized without increasing the lock-in time. Therefore , PL
The frequency jitter in the L circuit can be reduced.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) The frequency divider 50 can be omitted depending on the target frequency band. (2) PMOS 72, 73 and NMOS 76 , 77
Is to switch the charge / discharge path of electric charge according to the detection result of the lock detection unit 60, and even if it is configured by another switching element, the same effect as that of the above-described embodiment can be obtained.

[0027]

As described in detail above, the first to seventh aspects
According to the invention, first selected formation during the locked state
Or the second charge transfer path, Sui varying the on-resistance value
Since the switching element is provided, without increasing the lock-in time, a stable output voltage of the low-pass filter is, the oscillation frequency of the VCO becomes stable.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a PLL circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional PLL circuit.

[Explanation of symbols]

10 phase comparator 30 low-pass filter 40 VCO 60 lock detector 70 charge pump circuits 71 , 75 PMOS , NMOS (charge limiting element) 80 bias generator circuit Si input signal Sr feedback signals Su, Sd phase difference signal

Claims (7)

(57) [Claims] 1. A phase comparator for comparing an input signal and a feedback signal to generate a phase difference signal as a result of the comparison, and a first potential corresponding to a power supply potential based on the phase difference signal,
Alternatively, a charge pump circuit that outputs a second potential according to the ground potential, a low-pass filter that smoothes the first or second potential, and a feedback that oscillates at a frequency according to the output potential of the low-pass filter. In a PLL circuit including a voltage-controlled oscillator that generates a signal and outputs the oscillation frequency to the outside, the charge pump circuit is connected between the power supply potential and an output section of the charge pump circuit. And a second charge transfer path formed by a second switching element connected between the ground potential and the output section of the charge pump circuit. And the output potential of the low-pass filter is higher than a predetermined potential.
When the ON resistance value of the first switching element decreases and the ON resistance value of the second switching element increases, the output potential of the low-pass filter is lower than a predetermined potential.
In this case, the ON resistance value of the first switching element increases and the ON resistance value of the second switching element decreases. 2. The PLL circuit according to claim 1, wherein a bias voltage corresponding to an output potential of the low pass filter is provided.
A bias generation circuit for generating a potential is provided, and the first and second switches are controlled by the bias potential.
The on-resistance value of the ching element is controlled
PLL circuit to be. 3. The PLL circuit according to claim 2 , wherein the PLL is based on the input signal and the feedback signal.
Lock detection that sends the detection result of whether the circuit is in the locked state
An output part is provided, and the lock detection part is provided with the first and second charge transfer paths.
PLL times, characterized in that control the conduction state of
Road. 4. The PLL circuit according to claim 3, wherein the charge pump circuit includes the power supply potential and the char.
The first switch is connected to the output of the zippump circuit.
A third switch connected in parallel with the ching element.
Third charge transfer path constituted by a switching element, and
Between the ground potential and the output section of the charge pump circuit
In parallel with the second switching element
A fourth switching element which is
And the conductive state in the third and fourth charge transfer paths is
It is controlled by the lock detector.
PLL circuit. 5. The PLL circuit according to claim 4 , wherein the third circuit and the third circuit are provided before the PLL circuit is locked.
The fourth charge transfer path is in a conductive state, and
And the second charge transfer path are turned off and the PLL circuit is locked,
And the fourth charge transfer path become non-conductive, and
The first and second charge transfer paths are in a conductive state
PLL circuit to be. 6. The PLL circuit according to claim 4 , wherein the first switch is provided in the first charge transfer path.
Between the switching element and the output section of the charge pump circuit.
A fifth switching element connected to the second switching element and the second switch in the second charge transfer path.
Between the switching element and the output section of the charge pump circuit.
And a sixth switching element connected to the ON resistance of each of the fifth and sixth switching elements.
The value is controlled by the lock detector.
PLL circuit to be. 7. The PLL circuit according to claim 6 , wherein the lock detection is performed before the PLL circuit enters a lock state.
Depending on the output part, the fifth and sixth switching elements are connected.
ON resistance value rises, and after the PLL circuit is locked, the lock circuit is locked.
The detection unit causes the fifth and sixth switching elements to operate.
The PLL resistance is characterized in that the on-resistance value in
Road.