JP3364557B2 - Data processing system and programmable controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data link technique that allows a plurality of programmable controllers connected via a network to mutually refer to the data of each programmable controller.

[0002]

2. Description of the Related Art Conventionally, a control system in which a plurality of programmable controllers 1 are connected via a network 2 as shown in FIG. 10a has been widely used. In such a control system, each programmable controller 1
(ST0-ST3) cooperate to control the plant 3 and so on. Such a control system has a function called a data link in order to mutually exchange the data used for the above-mentioned coordinated control and plant management. The data link function matches all the contents of data in an area called a link area provided on the local memory of each programmable controller 1. The link area is a programmable controller for each divided area.
When the programmable controller 1 writes the data that it wants to send to another programmable controller to the area assigned to itself in the link area, this data is assigned to all other programmable controllers by the data link function. It is duplicated in the corresponding area on the link area of 1. FIG. 10b shows the link area allocation of each programmable controller. In this figure, each link area of each programmable controller is equally divided into four areas, and the top area of each link area is programmable controller ST0.
Shows the case where the second area of each link area is assigned to the programmable controller ST1, the third area of each link area is assigned to the programmable controller ST2, and the bottom area of each link area is assigned to the programmable controller ST3. There is. When such an allocation is made, the programmable controller ST0 writes the data written in the uppermost area of its own link area to the link areas of all other programmable controllers ST1, ST2, ST03 by the data link function. Each is duplicated in the top area.

[0003]

Since the conventional control system in which a plurality of programmable controllers are connected by a network is configured as described above, each programmable controller uses the above-described link data function to be programmable by another programmable controller. The amount of data that can be sent to the controller at one time was limited to the capacity of the link area divided by the number of programmable controllers. Therefore, when one programmable controller wants to send a larger amount of data to another programmable controller, a separate user can use a ladder program or the like to divide this data and use the link data function. Or, the user needs to control the transmission / reception of this data by a ladder program or the like without using the link data function. On the other hand, if the capacity of the link area is increased, the amount of data that can be sent to other programmable controllers by using the link data function also increases. This will increase the processing load of the function and increase the traffic on the network.

Therefore, an object of the present invention is to increase the amount of data that can be collectively transmitted / received by utilizing the link data function without increasing the capacity of the link area so much.

[0005]

[Means for Solving the Problems] In order to achieve the above object,
The present invention is a data processing system in which a plurality of data processing devices are connected via a network, wherein each of the data processing devices includes a processor unit that processes data, and a link area memory accessible by the processor. A link control unit that controls transfer of data between the link area memory and another data processing device via the network, and a storage area of the link area memory is provided in each of the plurality of data processing devices. The link control unit includes a high-speed area consisting of a plurality of areas that are exclusively allocated and one or more low-speed areas, and the link control unit includes all other data in the area of the high-speed area allocated to the own data processing device. Data transferred to a data processing device and data transferred from a high-speed area of another data processing device is de-sourced. Data is stored in the area of the high-speed area allocated to the data processing device, and the low-speed area memory is allocated to one data processing device. When the data stored in the area is transferred to all other data processing devices and the low speed area is assigned to another data processing device, the low speed of the other data processing device to which the low speed area is assigned is low. The data transferred from the area is stored in the low speed area, and the link control units of the respective data processing devices cooperate with each other to allocate the low speed area to only the same data processing device at a time in all the data processing devices. At the same time, the allocation of the low-speed area of the own data processing device is performed so that the data processing devices allocated to the low-speed area are sequentially replaced. To provide a data processing system according to claim Ukoto.

[0006]

In the control system according to the present invention, the data of the area assigned to the own data processing device in the area of each data processing device is the same as that of all other data processing devices as in the case of the conventional link data function. Copied to the high speed area. On the other hand, the data in the low speed area is copied to the low speed areas of all the other data processing apparatuses only when the own data processing apparatus is assigned to the low speed area. Otherwise,
It is used to receive the data transfer in the low speed area of another data processing device. That is, in each data processing device, the low-speed area is used for storing data to be transmitted by using the link data function at one time, and data received by using the link data function from another specific data processing device at some time. Shared time-shared for storage of Therefore,
Link area memory of each data processing device Each area of the same capacity as the low-speed area for storing data to be transmitted by using the link data function and each other programmable controller for storing data to be received by using the data function It is possible to collectively transfer the data for the capacity of the low speed area with a smaller capacity than in the case where each area is secured.

[0007]

EXAMPLES An example of the present invention will be described below.

First, FIG. 1 shows the configuration of a control system according to this embodiment.

In the figure, 1 is a programmable controller (ST0-ST3). Reference numeral 2 denotes a transmission path that connects the programmable controllers in a ring shape, and forms a network used by the programmable controller for data transmission. Reference numeral 3 denotes a controlled system controlled by each programmable controller, such as a plant.

In such a configuration, the transmission path 2 connecting the programmable controllers 1 (ST0-ST3) transmits a frame storing data in one direction (clockwise in the figure). As shown in FIG. 2, each frame includes a destination address 21 that is the address of the programmable controller that is the destination of the frame, a source address 22 that is the address of the programmable controller that is the source of the frame, and data 23. Contains. A predetermined broadcast address can be used as the destination address. The broadcast address indicates that all programmable controllers are destinations of the frame.

When each programmable controller 1 receives a frame from the upstream transmission path 2 in the transmission direction of the frame, it checks whether the source address of the frame is its own address, and if it is its own address, Since it is a frame that has already circulated around the ring of the transmission path after being transmitted, the received frame is discarded. If it is not its own address, check whether the destination address of the frame is its own address or broadcast address. If the destination address of the frame is its own address or broadcast address, the data in this frame Is received, and the received frame is relayed to the downstream transmission path. On the other hand, if it is not its own address or broadcast address, it only relays the received frame to the downstream transmission path, and does not capture the data. In this way, the frames are sequentially relayed around the ring of the transmission path starting from the programmable controller of the transmission source. Further, during this period, the data in the frame is taken in by the programmable controller designated by the destination address of the frame. In the present embodiment, the data in the link area is transmitted from the source programmable controller to all other programmable controllers in a frame in which the broadcast address is the destination address.

One programmable controller (ST0 in this embodiment) of the plurality of programmable controllers 1 (ST0-ST3) is selected as the master station, and the tie timing of transmission of each programmable controller 1 is It is well controlled by the master station. In particular,
The programmable controller of each slave station, when given the transmission right by the polling command from the master station,
Sends a frame containing its own data.

FIG. 3 shows each programmable controller 1
The internal structure of is shown.

As shown in the figure, the programmable controller 1 includes a CPU section 100, a link section 110, a control input / output section 120,
It is composed of an external input / output unit 130.

The CPU section 100 includes a CPU 101 and a main memory 1.
02, the link unit includes a link area memory 111, a link control processor 112, and a communication control unit 113 including a transmission / reception buffer 114. Further, the control input / output unit 120 includes an input circuit 121 that takes in the state signal of the controlled system 3, an output circuit 122 that outputs a control signal for controlling the controlled system 3, and the external input / output unit 130.
It is provided with a user program for externally specifying the process executed by the CPU 101, an input interface 131 for fetching various user operations, and an output interface 132 for outputting and displaying various information and states.
Further, the CPU 101 is configured to be able to directly access the link area memory 111, the input circuit 121, the output circuit 122, the input interface 131, and the output interface 132 via the bus 103. Also,
The communication control unit 113 performs the above-described frame transmission, relay, discard, and frame data capture. As described above, the communication control unit 113 fetches the data from the frame in the transmission / reception data buffer 114 provided therein according to the destination address, and notifies the link control processor 112 of the fact. The link control processor 112 that has received the notification transmits and receives the data buffer 114.
The data taken in by is transferred to the link area memory 111. On the contrary, the data transferred to the link control processor 112 from the link area memory 111 to the transmission / reception buffer 114 and the data written by the link control processor 112 are the destinations specified by the link control processor 112 by the communication control unit 113. It is stored and transmitted in a frame including an address and a transmission source address indicating the address of its own programmable controller 1.

In such a configuration, the CPU 101
Processing is performed in accordance with the user program loaded from the input interface 131 into the main memory 102. In this process, the state of the controlled object is captured via the input circuit 121, the controlled object 3 is controlled via the output circuit 122,
Various input / output through the input interface 131 and the output interface, data acquisition from the link area memory 111, data writing to the link area memory 111, processing of various data, and the like are performed.

Link data processing using the link area memory 111 in this embodiment will be described below.

In this embodiment, the storage space of the link area memory is divided as shown in FIG.

That is, the storage space of each link area memory 111 of each programmable controller 1 is set as a management area 1112, a high speed area 1113, and a low speed area 1114.
And split in the same way. Further, the high speed area is further divided into a number of programmable controllers. Each area obtained by dividing the high speed area is exclusively allocated to each programmable controller 1 one by one. In this embodiment, the top area of each high-speed area is the programmable controller ST0, the second area is the programmable controller ST1, the third area is the programmable controller ST2, and the bottom area is the programmable controller ST3. assign. Here, in the present embodiment, the storage space of the main memory 102 is set for each predetermined capacity.
It is used by dividing it into multiple pages. Then, the capacity of the high speed area and the capacity of the low speed area are made equal to the capacity of this page.

Next, in this embodiment, each area of the link area memory 111 thus divided is associated with each page of the main memory 102 as shown in FIG. Here, it is assumed that all the correspondences in each programmable controller are the same.

In each programmable controller 1, the high speed area 1113 is associated with one page of the main memory 102, and the low speed area 1114 is associated with as many pages as the number of programmable controllers in the control system. In the illustrated example, page 1 is associated with the high speed area 1113 and four pages 2-5 are associated with the low speed area 1114. In addition, the low speed area 111
Each programmable controller (ST0 to ST4) is exclusively allocated to each page allocated to page 4. Here, page 2 is ST0, page 3 is ST1, page 4 is
To ST2 and page 5 to ST3.

FIG. 5 shows the internal structure of the management area 1112.

As shown, the management area 1112 is
Transfer request flag 50, transfer completion flag 51, page number 5
2. It includes an area for describing the total number of pages 53.

Now, such a link area memory 11
The content of 1 is updated by the control of the link control processor 112 every cycle called a refresh cycle. In one refresh cycle, each programmable controller 1 (ST0 to ST3) transmits data once.

In each refresh cycle, the link control processor 1 of the master station programmable controller
03 updates the page number 52 of the management area 111 so as to sequentially represent the number of one page cyclically selected from the pages of the main memory 102 allocated to the low speed area 1114 every refresh cycle. That is, the page number of the management area 111 is set to page 2, page 3, page 4, page 5, page 2, page 3, ...
... and so on, and are sequentially updated every refresh cycle. In each refresh cycle, the link control processor 10 of the master station programmable controller
3 stores the page number set as the page number of the management area 1112 and the data of the area allocated to itself in the high speed area 113 in a frame including a broadcast address as a destination address and transmits the frame. However, if the page number set in the page number of the management area 1112 is the page number assigned to the own programmable controller ST0, the data of the low speed area 1114 is also transmitted. Then, when the transmission is completed, the polling commands are sequentially transmitted to the other slave stations, and the transmission right is sequentially given.

On the other hand, the link control processor 112 of the programmable controller 1 (ST1-ST3) of the other slave station is assigned to itself in the high speed area 113 when the transmission right is given from the master station in each refresh cycle. The data of the area is stored in a frame including a broadcast address as a destination address and transmitted. However, if the page number received earlier from the master station is the page number assigned to the own programmable controller, the data in the low speed area 1114 is also transmitted.

The link control processor 11 of the programmable controller 1 of the master station and the slave stations as described above.
The transmission by 2 is performed via the communication control unit 113 as described above.

In the operation of the refresh cycle as described above, the link control processors 112 of the programmable controllers of the master station and the slave stations are transmitted with the broadcast address as the destination address, and the communication control unit 113 transmits the pure data buffer 114. The data taken in by is transferred to the link area memory 111. The received data of the low-speed area 114 of the other programmable controller is transferred to the low-speed area 1114 of the link area memory 111, and the received data of the high-speed area 1113 of the other programmable controller is the transmission of the relevant data of the link area memory 111. Transfer to the area assigned to the original programmable controller 1. The page number received from the parent station in each child station is transferred to the page number 52 in the management area. That is, in the programmable controller of the destination,
The data will be stored in the same location in the link area memory 112 as the location stored in the link area memory 111 of the programmable controller of the transmission source.

By the operation of the refresh cycle as described above, the data transfer of the link area memories 112 of different programmable controllers as shown in FIG. 6 is realized. In the figure, the white circles represent the transfer source and the black circles represent the transfer destination.

That is, in the first refresh cycle, first, the link area memory 111 of the master station (ST0).
Management area 1112 page number, high-speed area 113 area data assigned to the master station, and low-speed area 1
After the 114 data is transferred to the link area memory 111 of each slave station (ST1, ST2, ST3), each slave station (ST1, ST2, ST3)
The data of the area allocated to the slave station in the high speed area 1113 is transferred to the link area memories 111 of all other slave stations and the master station.

In the second refresh cycle, first, the page numbers of the management area 1112 of the link area memory 111 of the master station (ST0) and the data of each area slave station (ST1, ST1, (ST2, ST3)
Of the slave station (ST
For 2, ST3), same as the first time, high speed area 1113
However, the data of the area allocated to the slave station is transferred to the link area memories 111 of all other slave stations and the master station. For the slave station (ST1), in addition to the data of the area allocated to the slave station (ST1) in the high speed area 113 of the link area memory 111, the link area memory 11
The data of the low speed area 1114 of 1 is also used for other slave stations (ST2, ST
3) and the link area memory 111 of the master station (ST0).

In the third refresh cycle, first, the page number of the management area 1112 of the link area memory 111 of the master station (ST0) and the data of each area slave station (ST1, ST1, (ST2, ST3)
Of the slave station (ST
For 1, ST3), same as the first time, high-speed area 111
The data of the area of No. 3 assigned to the slave station is transferred to the link area memories 111 of all other slave stations and the master station. Regarding the slave station (ST2), in addition to the data of the area allocated to the slave station (ST2) in the high speed area 113 of the link area memory 111, the link area memory 1
The data of 11 low-speed areas 1114 is also used for other slave stations (ST1 S
It is transferred to the link area memory 111 of the master station (ST0).

In the fourth refresh cycle, first, the page numbers of the management area 1112 of the link area memory 111 of the master station (ST0) and the data of each area slave station (ST1, ST1, (ST2, ST3)
Of the slave station (ST
For 1, ST2), same as the first time, high speed area 111
The data of the area of No. 3 assigned to the slave station is transferred to the link area memories 111 of all other slave stations and the master station. For the slave station (ST3), in addition to the data of the area allocated to the slave station (ST3) in the high-speed area 113 of the link area memory 111, the link area memory 1
The data of 11 low-speed areas 1114 is also used for other slave stations (ST1 S
It is transferred to the link area memory 111 of T2) and the master station (ST0).

Similarly, the refresh cycle is repeated like the first refresh cycle, the second refresh cycle, the same refresh cycle, the third refresh cycle, and the like.

As will be understood from FIG. 6, in this embodiment, the data of the area assigned to the own programmable controller in the high-speed area 113 of the link area memory 111 of each programmable controller depends on the conventional link data function. Similar to the case, it is copied to the link area memories 113 of all other programmable controllers every refresh cycle. On the other hand, the data in the low-speed area 1114 is copied once in every refresh cycle corresponding to the number of programmable controllers (in this embodiment, only once in every four refresh cycles, it is copied to the link area memories 113 of all other programmable controllers. According to the embodiment, the CPU 101 uses the link data function provided by the link unit 110 as described above and allocates to the own programmable controller in the high speed area 1113 the data to be transferred to another programmable controller at high speed. Data can be transferred at a high speed by writing in an area in which data is stored, and data that does not require high speed can be transferred collectively by writing in a low speed area 1114. , Sometimes link day To store the data to be transmitted by using the function, to store the data received is time to use the link data function from certain other programmable controller,
Since it is shared by time division, the area for storing data to be transmitted using the link data function, which has the same capacity as the low speed area 111 according to the present embodiment, is stored in the link area memory 111 of each programmable controller. It is possible to collectively transmit and receive a large amount of data with a small capacity, as compared with a case where each area for each programmable controller for storing the data to be received is secured by using the. Therefore, regarding the data required for coordinated control of controlled objects such as plants and emergency data,
Data that is exchanged at high speed between the programmable controllers using the link data function using the high speed area 1113, and has a large amount of data such as daily operation status statistical data, but does not need to be exchanged or aggregated at high speed. For, please use the link data function using the low speed area,
You can transfer them all at once.

The processes of the link control processor 112 and the CPU 100 that realize the link data process described above will be described in detail below.

First, the processing performed by the CPU 101 of the programmable controller 1 of the master station and each slave station will be described.

First, in initial processing such as installation,
The CPU 101 performs the following processing. That is, the total number of pages 53 in the management area 1112 is the number of pages associated with the low speed area 1114 in the initial processing.
Written by the CPU 101. In addition, the page number of the page assigned to its own station in each programmable controller, the area of the high-speed area 1113 assigned to the time station, the number and addresses of programmable controllers of other stations, and the like are managed areas from the CPU 101 to the link control processor 112 in the initial processing. It is transmitted using 1111.

After that, the CPU 101 performs the processing shown in FIG. 7 regarding the link data function.

That is, the CPU 101 periodically executes the processing shown in FIG.

In this process, first, it is checked whether or not the transfer request flag 50 in the management area 112 is set (step 701), and if it is not set, the process ends. On the other hand, if it is set, first, high speed area 1
The data of the area in page 1 of the main memory 102 corresponding to the area is transferred to the area assigned to the own station of 13 and the data of each area not assigned to the own station of the high speed area 113 is handled. The data is transferred to each area of page 1 of the main memory 102 (step 703). Then, it is checked whether or not the page number 52 of the management area 112 is the page number assigned to the own station (step 703), and if it is the page number of the page assigned to the own station, the main memory 102 is displayed. , The page allocated to this own station is transferred to the low speed area 114.
(Step 704). On the other hand, if the page number 50 is not the page number of the page assigned to the own station, the page number is transferred to the page of the main memory 102 indicated by the page number of the low speed area 1114 (step 705).

Finally, the transfer completion flag 51 in the management area 1112 is set, and the processing is ended.

The processing performed by the CPU 101 regarding the link data function has been described above.

Next, the processing performed by the link control processor 112 of the master station programmable controller (ST0) will be described.

FIG. 8 shows a processing procedure of this processing. In this process, first, the parameter N is set to the top page number (2 in this embodiment) of the plurality of pages assigned to the low speed area (step 801). And this N
Is set to the page number 52 of the management area 1112 (step 803). Then, the transfer request flag 50 in the management area 1112 is set (step 803), and the CPU 101 waits for the transfer completion flag 51 to be set (step 804). Then, if set, the transfer request flag 50 and the transfer completion flag 51 are reset (step 805), and the page number 52 of the management area 1112, that is, the value of N and the own station in the high speed area 1113 are assigned. Send area data. Also,
At this time, if the value of N is the page number of the page assigned to the own station, the data of the low speed area 1114 is also transmitted (step 806).

Then, turn to each slave station (step 812)
A transmission right is given to the communication control unit 1 by a polling command (step 807).
The data taken in by 13 is stored in the link area memory 111 as described above (step 808). And
Set the transfer request flag 50 in the management area 1112
(Step 809), wait for the transfer completion flag 51 to be set by the CPU 101 (step 810). If set, the transfer request flag 50 and the transfer completion flag 51 are reset (step 811).

When all the slave stations are processed
The parameter N is incremented by 1 (step 813) (step 814). Then, the transmission and reception (steps 802 to 813) described above are performed for the next page associated with the low speed area 1114. If the processing is completed for the number of pages specified by the total number of pages 53 in the management area 1112,
(Step 815) Then, the process returns to step 801, N is returned to the page number of the first page associated with the low speed area 1114, and the process is repeated from the beginning.

Next, the processing performed by the link control processor of the programmable controller 1 (ST1-ST3) of each slave station will be described.

FIG. 9 shows a processing procedure of this processing.

As shown in the figure, in this process, when the communication control unit 113 takes in the received data (step 90).
1), determine whether the received data is a polling command (step 902), and if it is not a polling command, determine whether it is data received from the master station (ST0),
If it is the data from the master station, the page number included in the data is set to the page number 52 of the management area 1112 (step 904), and the data fetched by the other communication control unit 113 is the link area memory 111. Store as described above. Also, step 90
If it is determined in 3 that the data is not the data from the master station, the data taken in by the communication control unit 113 is simply stored in the link area memory 111 as described above. Then, the transfer request flag 50 of the management area 1112
Is set (step 910), and the transfer completion flag 51 is set to C.
Wait for it to be set by PU 101 (step 91
1). Then, if set, the transfer request flag 5
0, reset the transfer completion flag 51 (step 912)
To do.

On the other hand, when it is determined in step 902 that the data is the polling command, it is determined whether the polling command is a polling command that gives the transmission right to the local station (step 905), and the local station is notified. If the polling command gives a transmission right, the transfer request flag 50 in the management area 1112 is set (step 9
06), and waits for the transfer completion flag 51 to be set by the CPU 101 (step 907). Then, if set, the transfer request flag 50 and the transfer completion flag 51
Is reset (step 908), and the data of the area allocated to the own station in the high speed area 1113 is broadcasted. At this time, if the value of the page number 52 of the management area 1112 is the page number of the page assigned to the own station, the data of the low speed area 1114 is also broadcast (step 909).

The link control processor of each slave station executes the above processing every time the communication control unit 113 fetches the received data according to the destination address thereof.

As described above, in the processing of the link control processor 112 of FIG. 8 and FIG. 9, the link control processor 112 links the data of the link query memory 111 from its own station before the transmission of the data and the data of the reception from other stations. When fetched in the area data memory, the CPU 101 is requested to transfer data between the main memory 102 and the link area memory 111 via the management area 1112 transfer request flag 50. Then, as shown in the processing of FIG. 7, the CPU 101 loads the data sent from the other programmable controller 1 into the link area memory 111 into the main memory 102 in response to this transfer request, and
The data to be transmitted is written in the link area memory 111. At this time, the low speed area 1114 is transferred from the main memory 102 to the link area memory 111 according to the page number managed and controlled by the master station.
Whether to transfer from the link area memory 111 to the main memory 102 is controlled. Similarly, according to the page number managed and controlled by the master station, the low speed area 1114
It is controlled whether or not to receive the received data. Therefore, there is no inconsistency in data transfer between the programmable controllers 1 using the low speed area 1114.

The embodiment of the present invention has been described above.

In the above description, the CPU 101 of FIG.
The processing of No. is described as being performed periodically, but the link control processor 102 requests the CPU 101 to interrupt along with the setting of the transfer request flag 50, and the CPU 101 executes the processing of FIG. 7 in response to this interrupt request. You may Further, in the processing of FIG. 7, the transfer request flag 5
When 0 is set, the main memory 1 is always
02 from the link area memory 111 to the link area memory 111 and from the link area memory 111 to the main memory 102 are both performed, but the transfer request flag is set when the data is transmitted to another station (see FIG. 8 step). 803, step 906 in FIG. 9), only the transfer from the main memory 102 to the link area memory 111 is performed, and the transfer request flag is set when the data from another station is fetched into the link area memory. In the processing in response to (step 809 in FIG. 8 and step 910 in FIG. 9), the link area memory 111 to the main memory 102
Alternatively, only the transfer from to may be performed. For this switching, a flag designating whether to request writing is provided in the management area 1112, the link control processor 112 controls the value of this flag together with the transfer request flag, and the CPU 101 performs processing in accordance with this flag. Should be switched

[0056]

As described above, according to the present invention, it is possible to increase the amount of data that can be collectively transmitted / received by using the link data function without increasing the capacity of the link area. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control system.

FIG. 2 is a diagram showing a structure of a frame to be transmitted.

FIG. 3 is a block diagram showing a configuration of a programmable controller.

FIG. 4 is a diagram showing a configuration and correspondence of a main memory and a link area memory.

FIG. 5 is a diagram showing a configuration of a management area.

FIG. 6 is a diagram showing how data is transferred between programmable controllers.

FIG. 7 is a flowchart showing a processing procedure of processing performed by the CPU of the programmable controller.

FIG. 8 is a flowchart showing a processing procedure of processing performed by the link control processor of the programmable controller of the master station.

FIG. 9 is a flowchart showing a processing procedure of processing performed by a link control processor of a programmable controller of a slave station.

FIG. 10 is a diagram showing a conventional control system.

[Explanation of symbols]

1 programmable controller 2 transmission lines 3 controlled system 102 main memory 111 Link area memory 1111 Management area 1112 high speed area 1114 low speed area

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Ito 46 Tomioka, Nakajo-machi, Kitakanbara-gun, Niigata Prefecture 1 1 Industrial equipment division, Hitachi, Ltd. (72) Tsutomu Sunaga 46 Tomioka, Nakajo-machi, Kitakanbara-gun, Niigata Prefecture Address 1 Hitachi Industrial Co., Ltd. Industrial Equipment Division (72) Inventor Norihiro Aida 46 Tomioka, Nakajo-cho, Kitakanbara-gun, Niigata Prefecture Address 1 Hitachi Industrial Co., Ltd. Industrial Equipment Division (56) Reference JP-A-59-205640 ( JP, A) JP 57-45606 (JP, A) JP 7-13482 (JP, A) Actually open 3-59755 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G05B 19/00-19/16 G06F 15/16-15/177 682

Claims (3)

(57) [Claims] 1. A data processing system in which a plurality of data processing devices are connected via a network, wherein each of the data processing devices includes a processor unit for processing data, and a link area memory accessible by the processor. A link control unit that controls transfer of data via the network between the link area memory and another data processing device, wherein a storage area of the link area memory is one of the plurality of data processing devices. Includes a high-speed area consisting of a plurality of areas exclusively allocated to each other, and one or more low-speed areas, wherein the link control unit includes all other data of the area of the high-speed area allocated to the own data processing device. Other data processing device and the source of the data transferred from the high-speed area of another data processing device Storing in the area of the high speed area allocated to the data processing device and allocation of the low speed area memory to one data processing device, and low speed when the low speed area is allocated to the own data processing device Transfers the data stored in the area to all other data processing devices,
When the low-speed area is assigned to another data processing device, the data transferred from the low-speed area of the other data processing device to which the low-speed area is assigned is stored in the low-speed area, and the link of each data processing device is performed. The control units cooperate with each other,
In all the data processing devices, the low-speed area is assigned only to the same data processing device at a time, and the low-speed area of the own data processing device is assigned so that the data processing devices assigned to the low-speed area are sequentially replaced. A data processing system characterized by the above. 2. The data processing system according to claim 1, wherein the data processing device is a plurality of programmable controllers that respectively control the controlled system, and each programmable controller is used by the processor for data processing. A main memory is provided, and a storage area of the memory is a shared page including a plurality of areas exclusively allocated to each of the plurality of programmable controllers, and a plurality of shared pages exclusively allocated to each of the plurality of programmable controllers. And a dedicated page of the shared page, the processor transfers data from an area assigned to the own programmable controller of the shared page to an area of a high-speed area assigned to the own programmable controller, and is assigned to another programmable controller. High Data is transferred from each area of the high speed area to the area of the shared page allocated to the other programmable controller, and when the low speed area is allocated to the own programmable controller, the low speed is transferred from the dedicated page allocated to the programmable controller. Data is transferred to an area, and when the low speed area is assigned to another programmable controller, the data is transferred from the low speed area to a dedicated page assigned to the other programmable controller. Data processing system. 3. A programmable controller connected to one or more other programmable controllers via a network, the processor processing data, a link area memory accessible by the processor, the link area memory, and the like. A link controller for controlling data transfer between the programmable controller and the programmable controller, and a storage area of the link area memory, the plurality of areas being exclusively assigned to each of the plurality of programmable controllers. The link control unit includes a means for dividing into a high-speed area and a low-speed area, and the link control unit is connected to all other programmable controllers connected via the network of the data of the area of the high-speed area assigned to the own programmable controller. Transfer and
High-speed link data means for storing data transferred from a high-speed area region of another programmable controller connected via a network in the high-speed area region assigned to the programmable controller that is the transmission source of the data, Allocating means for allocating the low-speed area memory to one programmable controller, and when allocating the low-speed area to its own programmable controller, transfers the data of the low-speed area to all other programmable controllers, When the area is assigned to another programmable controller, the low-speed link data means for storing the data transferred from the low-speed area of the other programmable controller to which the low-speed area is assigned in the low-speed area is provided. Means In cooperation with the link controller of another programmable controller which is connected via a network,
In all programmable controllers, the low-speed area is assigned only to the same programmable controller at a time, and the low-speed area of the own programmable controller is assigned so that the programmable controllers assigned to the low-speed area are sequentially replaced. Programmable controller.