JP3354709B2 - Semiconductor booster circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Electrically Erasable and Programmable Read Only M
emory) and a semiconductor booster circuit such as a charge pump circuit used for a flash memory.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits such as EEPROMs and flash memories have a single 5V power supply or a single 3V power supply, the voltage has been boosted inside the integrated circuit. For this purpose, a semiconductor booster circuit such as a charge pump circuit is used.

FIG. 11 shows a configuration of a conventional semiconductor booster circuit.

As shown, N-channel MOS transistors Q _{20 to} Q ₂₄ are connected in cascade to form an n-stage booster circuit. The gate terminal of each transistor Q ₂₀ to Q ₂₄ is connected to the source terminal, also each source terminal N
The ₂₀ to N ₂₄ is the clock signal phi _A or phi _B is input through the capacitance C ₂₀ -C _24.

As shown in FIG. 12, clock signals φ _A ,
φ _B are signals having phases opposite to each other, having a period of 1 / f and an amplitude of Vφ. The clock signals φ _A and φ _B are obtained by passing the clock signal CK through the NAND circuits ND ₁ and ND ₂ and the inverter circuits IV _{1 to} IV ₃ in FIG. 11, and the amplitude Vφ of the clock signals φ _A and φ _B is obtained. Is equal to the power supply voltage _Vdd . In FIG. 11, G is a ground terminal.

As shown in FIG. 11, in this semiconductor booster circuit, a power supply voltage _Vdd is applied as an input signal to a transistor Q _25.
Is input from the source terminal N _27, the output voltage V _POUT is output from the output terminal N ₂₆ as an output signal.

The output voltage V of such a semiconductor booster circuit
_POUT is, for example, "Analysis and Modeling of On-Chip H
igh-voltage Generator Circuits for Use in EEPROM C
ircuits "(IEEE JOURNAL OF SOLID-STATE CIRCUITS, vo
l.24, No.5, OCTOBER 1989),
It is represented by the following equation. _{V POUT = V in -V t +} n [Vφ · C / (C + C s) -V t -I OUT / f (C + C s) ] _{... (1) V t = V} tO + K 2 · [(V _bs + 2φ _f) ^1/2 - ^(2φ _f) ^1/2] (2) where, V _in: input voltage Vφ of the booster circuit: clock amplitude voltage f: clock frequency C: coupling capacitance C _s to the clock signal: boost Parasitic capacitance at each stage of the circuit n: _Number of stages of booster circuit V _POUT : Output voltage at last stage of booster circuit I _OUT : Load current at output stage V _tO : Threshold voltage without substrate bias V _bs : Substrate bias voltage (potential difference between source and substrate or well) φ _f : Fermi potential K ₂ : substrate bias coefficient

From the equation (1), when the load current I _OUT is 0 and C / (C + C _s ) ≒ 1, the output voltage V _POUT is (Vφ
−V _t ) and the number n of stages of the booster circuit. In the conventional booster circuit shown in FIG.
Since the clock amplitude voltage Vφ is equal to the power supply voltage _Vdd ,
The output voltage V _POUT increases in proportion to the number n of values and the step-up circuit (V _dd -V _t).

[0009]

[0007] However, the conventional boosting circuit, the output according to the voltage V _POUT increases, the body effect, the threshold voltage V _t of the transistors Q ₂₀ to Q ₂₄ is (2) As shown in FIG.

[0010] Therefore, when the substrate effect constitutes a boost circuit discrete was prevented from being generated, the output voltage V _POUT is become larger in proportion to the number of stages n of the step-up circuit, the transistors Q ₂₀ when formed on the same substrate to Q ₂₄ are integrated, since the substrate effect occurs,
The value of (V _dd -V _t ) decreases as the number n of stages of the booster circuit increases.

As a result, as shown in FIG. 13, as the number n of stages of the booster circuit increases, the output voltage _VPOUT decreases from a value obtained when there is no _body effect, and ( _Vdd- V
_When the value of _t ) becomes 0, the output voltage V _POUT is saturated. This indicates that no matter how large the number of stages n of the booster circuit is, there is a limit to the output voltage V _POUT obtained. FIG. 14 shows the relationship between the power supply voltage _Vdd and the maximum output voltage when the number of stages n of the booster circuit is infinite. When the number of stages n of the booster circuit is infinite, if there is no substrate effect, the obtained output voltage _VPOUT becomes theoretically infinite. However, if there is a substrate effect, the output voltage V _POUT is determined by the power supply voltage _Vdd . Can only be obtained up to a certain value. That is, in the conventional booster circuit, when the power supply voltage _Vdd is low, the desired output voltage V
There was a problem that _POUT could not be obtained.

For example, in the conventional booster circuit shown in FIG. 11, a power supply voltage _Vdd is 2.5 V, and a threshold voltage V _tO when there is no substrate effect is 0.6 V (substrate bias is 0 V).
V), 20 V could be obtained as the output voltage V _POUT when the number of stages n of the booster circuit was set to 20, but when the power supply voltage _Vdd was 2.0 V, the number of stages n of the booster circuit was increased to 100.
Even in the stage, only 12 V could be obtained as the output voltage _VPOUT .

Meanwhile, in JP-A-61-254078, it is lower than the threshold voltage V _t of the front side of the MOS transistor threshold voltage V _t of significant second-stage MOS transistors of the substrate effect Discloses a cockloft-type booster circuit in which a reduction in output voltage due to the substrate effect is improved.

[0014] However, in this arrangement, rises itself of the threshold voltage V _t due to the substrate effect can not be suppressed, for example, when the power supply voltage V _dd becomes about half (V
_(dd = 1 to 1.5 V), a desired output voltage _VPOUT cannot be obtained regardless of the value of the number n of stages of the booster circuit. Also, the threshold voltage V of the MOS transistor
_In order to set a plurality of _t , for example, it is necessary to add an extra step of a photomask and ion implantation, which has a disadvantage that the manufacturing process becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor booster circuit which can obtain a desired output voltage even when a power supply voltage is low without requiring a particularly complicated manufacturing process.

[0016]

In order to solve the above-mentioned problems, in a semiconductor booster circuit according to the present invention, each stage has a first MOS transistor and one end connected to a drain terminal of the first MOS transistor. The first MOS transistors are connected in cascade, the respective stages are connected, and the source terminal of the first MOS transistor and the substrate in each stage are electrically connected to each other. And the substrate portion is electrically insulated from the substrate portion of the first MOS transistor in another stage.

In one embodiment of the present invention, the first MOS transistor is a P-channel transistor formed in an N-type well region.
An OS transistor, wherein the N-type well region is electrically insulated and separated for each stage.

In one embodiment of the present invention, in each stage, a second capacitance having one end connected to a gate terminal of the first MOS transistor is provided, and a gate terminal and a source terminal of the first MOS transistor are provided. Are connected to each other via a second MOS transistor, and the gate terminal of the second MOS transistor is connected to the one end of the first capacitance.

In one embodiment of the present invention, a pair of first phases having opposite phases to each other are connected to the other ends of the two successive stages of the first capacitance.
Clock signals are input respectively, and two consecutive
A pair of second clock signals having different pulse timings are respectively input to the other end of the second capacitance of the stage.

In one embodiment of the present invention, in each stage, the gate terminal of the first MOS transistor is connected to the one end of the first capacitance in the subsequent stage, and the first capacitance in the continuous two stages is connected. , A pair of clock signals having phases opposite to each other are input to each other.

In one embodiment of the present invention, each stage comprises a MOS transistor and a capacitance having one end connected to a drain terminal of the MOS transistor.
Each stage is connected by connecting the S transistors in cascade, and the gate terminal and the source terminal of the MOS transistor in each stage are electrically connected to each other, and the source terminal and the substrate are electrically connected to each other. And the substrate portion is electrically insulated from the substrate portion of the MOS transistor in another stage.

In one embodiment of the present invention, a pair of clock signals having mutually opposite phases are input to the other ends of the two successive capacitances, respectively. In one aspect of the invention, the MO
The S transistor is an N-channel MOS transistor formed in a P-type well region, and the P-type well region is electrically insulated and separated for each stage.

[0023]

According to the present invention, the substrate portion of the MOS transistor forming each stage of the booster circuit is electrically insulated and separated from the substrate portion of the other MOS transistor, and the substrate portion of the MOS transistor is connected to the source in each stage. By electrically connecting the terminals to each other, the substrate portion of the MOS transistor is fixed at the source potential, and M
The increase in the threshold voltage of the OS transistor is suppressed.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a first embodiment of the present invention; FIG.

FIG. 1 shows a configuration of a semiconductor booster circuit according to a first embodiment of the present invention.

As shown in FIG. 1, n P-channel MOs
The S transistors Q ₁ , Q ₃ , Q ₅ , Q ₇ ,..., Q ₉ are connected in cascade to form an n-stage booster circuit. The substrates of the transistors Q ₁ , Q ₃ , Q ₅ , Q ₇ ,..., Q ₉ are electrically separated from each other, and the substrates are respectively connected to the transistors Q ₁ , Q ₃ , Q ₅ , Q ₇ ,. ..., it is connected to the source terminal of Q _9. The drain terminals of the transistors Q ₁ , Q ₃ , Q ₅ , Q ₇ ,..., Q ₉ (represented by nodes N ₁ , N ₃ , N ₅ , N ₇ ,..., N ₉ ).
, And C ₁ , C ₃ , C ₅ , C ₇ ,.
_The clock signal φ _1A or φ _1B shown in FIG.

The transistors Q ₁ , Q ₃ , Q ₅ , Q
_7, ..., the gate terminal (node N ₂ of _{Q 9, N 4, N 6} ,
N _8, ..., represented by N _10. ) Receives the clock signal φ _2A or φ _2B shown in FIG. 3 via the capacitances C ₂ , C ₄ , C ₆ , C ₈ ,..., C _{10 respectively} .

The transistors Q ₁ , Q ₃ , Q ₅ ,
Q _7, ..., gate terminal of _{Q 9 N 2, N 4,} N 6, N 8,
..., N ₁₀ and the source terminal (node _{N 3, N 5, N 7} ,
N _11, ..., represented by N _12. ) Between the, P-channel MOS transistors _{Q 2, Q 4, Q 6} , Q 8, ..., Q 10
Are respectively connected, and these transistors Q ₂ , Q ₄ , Q
_6, Q _8, ..., gate terminal of Q _10, the transistor Q _{1,
Q 3, Q 5, Q 7} , ..., drain terminal N ₁ of Q _{9,
N 3, N 5, N 7} , ..., are respectively connected to the N _9.

In the booster circuit of this embodiment, the power supply voltage _Vdd is _supplied as an input signal to the N-channel MOS transistor Q.
_12, (indicated by the node N _0.) The source terminal of Q ₁₃ to the transistor Q _1, the source terminal N ₁ of Q _3, N ₃ are respectively input from, as the output signal, the output voltage V _POUT, N-channel MOS transistor through Q ₁₁ are outputted from the output terminal (. represented by the node N _13). As shown, the gate terminals of the transistors Q ₁₂ and Q ₁₃ are respectively connected to the source terminal N _0.
It is connected to the. Further, the source terminal of the transistor Q ₁₁ (. Represented by the node N ₁₂₎ is a capacitance C
₁₁ through, the clock signal phi _1A shown in FIG. 3 is input. Furthermore, the gate terminal of the transistor Q ₁₁ is connected to the drain terminal (. Represented by the node N _13).

As shown in FIG. 3, clock signals φ _1A , φ
_1B are signals having phases opposite to each other, and the clock signals φ _2A , φ
_2B is a pulse-like signal that is turned off during a period in which the clock signals φ _1A and φ _1B are turned on.

Next, the operation of the semiconductor booster circuit according to the first embodiment will be described with reference to FIGS.

FIG. 2 is a circuit diagram showing two successive stages (first and second stages) of the semiconductor booster circuit of FIG. Also,
FIG. 4 is a diagram showing FIG. 2 during the periods (I) to (VI) shown in FIG.
Shows the voltage waveform at the node N _A to N _D circuits. Further, FIG. 5 is a diagram showing each of the periods (I) to (VI) shown in FIG.
It is a circuit diagram for explaining the conduction state of the transistor M ₁ ~M _4.

First, in the period (I), as shown in FIG. 3, the clock signal φ _1A changes from the ground potential 0 V to the power supply voltage _Vdd , and the potential of the drain terminal N _A of the transistor M ₁ shown in FIG. , As shown in FIG.
_It increases by the voltage of _dd .

Further, the clock signal phi _1B is from the power supply voltage V _dd to the ground potential 0V, the potential of the source terminal N _B of the transistor M _1, as shown in FIG. 4 (b), the power supply voltage V _dd
Of the voltage.

At this time, the source terminal N of the transistor M _1
The charge carried from the previous stage is accumulated in the capacitance C _A2 connected to _B , and the transistor M ₁
The potential of the source terminal N _B is boosted by the voltage of the charge that is accumulated in the capacitance C _A2.

The gate terminal N _{A of the} transistor M ₂
The potential becomes higher than the potential of the source terminal N _B, the transistor M _2, as shown in FIG. 5 (I), the OFF state from the ON state.

[0037] At this time, as described later, the PN junction formed between the drain terminal N _A and the source terminal N _B of the transistor M ₁ is biased in the forward direction,
Substrate of the transistor M ₁ connected to a source terminal N _B is held from the potential of the drain terminal N _A to the potential obtained by subtracting the forward bias voltage of the PN junction.

Further, as shown in FIG. 4 (c), the potential of the gate terminal N _C of the transistor M ₁ is lowered to the same potential of the drain terminal N _A, but the transistor M ₁ is FIG. 5 (I) As shown in FIG.

Further, the clock signal phi _1A is accompanied become the power supply voltage V _dd from the ground potential 0V, the potential of the source terminal N _D of the transistor M _3, as shown in FIG. 4 (d), the supply voltage V _It increases by the voltage of _dd .

At this time, the charge carried from the preceding stage is accumulated in the capacitance C _A3 , and the transistor M
The source potential of the terminal N _{D 3} is boosted by the voltage of the charge stored in the capacitance C _A3.

Further, when the clock signal phi _1B becomes the power supply voltage V _dd to the ground potential 0V, the potential of the gate terminal N _B of the transistor M ₄ is lowered, the transistor M ₄ is turned on from the OFF state , the potential of the gate terminal N _E of the transistor M ₃ are, the source terminal of the transistor M ₃ N
The potential becomes the same as the potential of _D. At this time, as shown in FIG. 5 (I), the transistor M ₃ represents remain off.

Next, in the period (II), the clock signal phi _2A is a power supply voltage V _dd to the ground potential 0V, the potential of the gate terminal N _C of the transistor M _1, as shown in FIG. 4 (c), The voltage drops by the power supply voltage _Vdd .

[0043] Therefore, as shown in FIG. 5 (II), the transistor M ₁ is turned on, the source terminal N _B from the drain terminal N _A of the transistor M _1, a drain terminal N
Current flows until the potential of the _A and the source terminal N _B equal.

That is, charge transfer is performed from the capacitance C _A1 to the capacitance C _A2 , and as shown in FIG. 4A, the potential of the drain terminal N _A of the transistor M ₁ decreases, and as shown in FIG. as shown, the potential of the source terminal N _B of the transistor M ₁ is increased.

The source terminal N _{D of the} transistor M ₃
The same applies to the case of the drain terminal N _A of the transistor M ₁ , and the potential of the source terminal N _D falls as shown in FIG.

[0046] At this time, the clock signal phi _2A for the transistors M ₁ to the ON state is supplied from the outside via the capacitance C _B1, the drain terminal N _A and the source terminal when the transistor M ₁ in an on state since the voltage drop does not occur between the N _B, boosting capability is improved as compared with the prior art. That is, this state is in the aforementioned equation (1), per the state where deemed V _t = 0V in parentheses can be performed much more efficiently boost.

Next, in the period (III), the clock signal phi _2A becomes the power supply voltage V _dd from the ground potential 0V, the potential of the gate terminal N _C of the transistor M _1, as shown in FIG. 4 (c), It increases by the power supply voltage _Vdd .

[0048] Therefore, as shown in FIG. 5 (III), the transistor M ₁ is turned off.

Further, as shown in FIG. 4 (a) (b) ( d), the drain terminal N _A of the transistor M _1, a source terminal N _B, the potential of the source terminal N _D of the transistor M ₃ unchanged.

Next, in the period (IV), the clock signal phi _1A becomes the ground potential 0V from the power supply voltage V _dd, the potential of the drain terminal N _A of the transistor M ₁ is, attempts to lowering voltage of the power supply voltage V _dd Suruga, in the first stage, the transistor Q ₁₂ in FIG. 1 is turned on, as shown in FIG. 4 (a), a potential of (V _dd -V _t).

[0051] Further, since the clock signal phi _1B from the ground potential 0V to the power supply voltage V _dd, the potential of the source terminal N _B of the transistor M _1, as shown in FIG. 4 (b), the power supply voltage V _dd
Rise by the voltage of

[0052] At this time, the capacitance C _A2 is the charge that has been carried from the previous stage is accumulated, the potential of the source terminal N _B of the transistor M ₁ is the capacitance C _A2
Is boosted by the voltage of the electric charge stored in the memory.

The gate terminal N _{A of the} transistor M ₂
The potential lower than the potential of the source terminal N _B, the transistor M _2, as shown in FIG. 5 (IV), consisting of OFF state to the ON state.

[0054] Therefore, the potential of the gate terminal N _C of the transistor M _1, as shown in FIG. 4 (c), rises to the same potential as the source terminal N _B of the transistor M _1.

[0055] Further, as the clock signal phi _1A is made from the power supply voltage V _dd to the ground potential 0V, the potential of the source terminal N _D of the transistor M _3, as shown in FIG. 4 (d), the supply voltage V _It drops by the voltage of _dd .

At this time, the charge carried from the previous stage is accumulated in the capacitance C _A3 , and the source terminal N _D
Is boosted by the voltage of the charge stored in the capacitance C _A3 .

[0057] Therefore, the potential of the drain terminal N _B of the transistor M ₄ is higher than the potential of the source terminal N _D,
Transistor M _4, as shown in FIG. 5 (IV), the OFF state from the ON state.

[0058] Also, as in the case of the transistor M ₁ described above, since the PN junction formed between the drain terminal N _B and the source terminal N _D of the transistor M ₃ is biased in the forward direction, a source terminal N _D substrate portion of the connected transistors M ₃ are, are held from the potential of the drain terminal N _B to the voltage obtained by subtracting the forward bias voltage of the PN junction.

Next, in the period (V), the clock signal phi _2B becomes the ground potential 0V from the power supply voltage V _dd, the potential of the gate terminal N _E of the transistor M ₃ are, lowered voltage of the power supply voltage V _dd.

[0060] Therefore, as shown in FIG. 5 (V), the transistor M ₃ are turned on, the source terminal N _D from the drain terminal N _B of the transistor M _3, the drain terminal N
Current flows until the potential of the _B and the source terminal N _D is equal.

[0061] That is, is performed passing the charge from the capacitance C _A2 to the capacitance C _A3, as shown in FIG. 4 (b), the potential of the drain terminal N _B of the transistor M ₃ are lowered, in FIG. 4 (d) as shown, the potential of the source terminal N _D of the transistor M ₃ are increased.

[0062] Further, the transistor M ₂ is kept on, the drain terminal N _B of the gate terminal N _C and the transistor M ₃ of the transistor M ₁ is at the same potential, 4
(C), the transistors M ₁ gate terminal N
The potential of _C falls.

[0063] At this time, the clock signal phi _2B for the transistor M ₃ and the ON state is supplied from the outside via the capacitance C _B2, the drain terminal N _B and the source terminal when the transistor M ₃ to the ON state since the voltage drop does not occur between the N _D, boosting capability is improved as compared with the prior art.

Next, in the period (VI), the clock signal φ
_2B becomes the power supply voltage V _dd from the ground potential 0V, the potential of the gate terminal N _E of the transistor M ₃ are, increases voltage of the power supply voltage V _dd.

[0065] Therefore, as shown in FIG. 5 (VI), the transistor M ₃ are turned off.

As shown in FIGS. 4A to 4D,
The potential of the node N _A to N _D is unchanged.

In the above-described operation, the source terminals of the transistors M ₁ and M ₃ are boosted in the later stages, so that the substrate effect normally occurs. as such, the threshold voltage V _t of the transistors M _1, M ₃ is going to rise. However, in this embodiment, as shown in FIG. 2, since the substrate portions of the transistors M ₁ and M ₃ are connected to the source terminals,
The substrate effect does not occur, and the transfer of charges from the preceding stage to the subsequent stage is performed efficiently.

FIG. 6 is a schematic sectional view showing the element structure of the transistors M ₁ and M ₃ in FIG.

As shown in FIG. 6, N well regions 11 insulated from each other are formed in a P-type semiconductor substrate 10, and each N well region 11 has a polycrystalline silicon layer formed through a gate oxide film 15. Having layer 16 as a gate electrode;
MOS having P ⁺ diffusion layer 12 as source / drain
A transistor is formed.

P ⁺ diffusion layer 1 on the source side of each transistor
2 is electrically connected to the N well region 11 in which the transistor is formed via the N ⁺ diffusion layer 14, and the source of the preceding transistor is connected to the drain of the subsequent transistor.

As a result, the N-well region 11 serving as the substrate of each transistor is fixed at the source potential of each transistor, and the substrate effect is prevented.

Further, P ⁺ on the drain side of each transistor
PN formed between diffusion layer 12 and N well region 11
When the junction is in the state shown in FIG. 5 (I) or (IV), it is forward biased, and through this PN junction, from the N well region 11 of the substrate through the N ⁺ diffusion layer 14, the node N _A →
N _B, can deliver the charge of N _B → N _D. In this case, the forward junction bias voltage V of the PN junction independent of the threshold voltage V _t of the MOS transistor
Will be utilized potential difference _F (usually about 0.7 V) to the booster, it is using V _F instead of V _t of the aforementioned (1) (2). The forward junction bias voltage V of this PN junction
_{Since F} is not affected by the substrate effect, it is possible to realize a booster circuit in which the boosting capability does not decrease due to the substrate effect even when the number of stages of the booster circuit increases.

[0073] As described above, in the semiconductor booster circuit according to the first embodiment of the present invention, MOS transistors _{Q 1, Q 3, Q 5} , Q 7 of FIG. 1, ..., electrically from each other substrates of Q ₉ By electrically connecting each substrate to source terminals N ₃ , N ₅ , N ₇ , N ₁₁ ,..., N ₁₂ , an increase in threshold voltage V _t due to the body effect is prevented. Preventing. Therefore, an output voltage V _POUT that increases in proportion to the number of stages n of the booster circuit can be obtained, and a semiconductor booster circuit having a higher boosting capability than conventional can be provided.

In this embodiment, as shown in FIG. 6, the N well regions 11 where the transistors are formed are formed separately, and the N ⁺ impurity regions 14 of the N well regions 11 and the N ⁺ impurity regions 14 are formed. It suffices to electrically connect the P ⁺ impurity region 12 on the source side of the transistor, and there is no need for a process for making the threshold voltage of each transistor different from the conventional case. Absent.

By electrically connecting the substrate of each transistor to the source terminal, a PN junction formed at the boundary between the drain and the substrate is formed in parallel between the source and the drain of each transistor. The structure is connected.
When the charge is sent to the next stage in the booster circuit, the PN junction is turned on, so that the potential of the substrate of each transistor is reduced to the forward junction bias voltage V _F of the PN junction (typically about 0.7 V). Can be fixed to the potential difference of
This can also suppress the influence of the substrate effect.

As shown in FIG. 5, the gate signals N _C and N _E of the transistors M ₁ and M ₃ are connected to the clock signals φ _1A and φ _1B input to the drain terminals N _A and N _B , respectively. Since independent clock signals φ _2A and φ _2B can be input to turn on the transistors without causing a potential difference between the source and the drain of each of the transistors M ₁ and M ₃ , When sending charges to the stage, the charges can be sent so that a voltage drop of the potential difference between the source and the drain does not occur. Therefore, in equation (1), since the threshold voltage V _t can be put to zero, can boost efficiency as compared with the conventional circuit, the number of stages n and the power supply voltage V _dd of the booster circuit is the circuit identical to the prior art Even in this case, a higher output voltage _VPOUT can be obtained. If the output voltage V _POUT is the same, the booster circuit of the present embodiment can take a larger load current I _OUT .

For example, when the power supply voltage _Vdd is 2.5 V and the number of stages n of the booster circuit is 20, the capacitance ratio C / (C
+ C _s ) is 0.9, the absolute value of the threshold voltage | V _t | is 0.6 V, and the load current I _OUT at the output stage is 0. In the conventional circuit, only 20 V is obtained as the output voltage V _POUT. Was not possible, but in the circuit according to the present embodiment, 47 V
The value of the degree was able to be obtained.

Further, in the semiconductor booster circuit according to the present embodiment, a desired output voltage can be obtained even at a low power supply voltage _Vdd which cannot be boosted by the conventional circuit. That is, in the conventional circuit, as shown in FIG. 14, the maximum output voltage is limited to a predetermined value by the power supply voltage _Vdd regardless of the value of the number n of stages of the booster circuit. In the semiconductor booster circuit according to the above, there is practically no such limitation.

For example, when the power supply voltage V _dd is 2.0 V, the capacitance ratio C / (C + C _s ) is 0.9, the absolute value of the threshold voltage | V _t | Load current I
_Assuming that _OUT is 0, in the conventional circuit, the output voltage _VPOUT could only be obtained at 12 V even when the number of stages n of the booster circuit was 50, but in the circuit according to the present embodiment, the number of stages n of the booster circuit was 20. , A value of about 37 V was obtained, and when the number of stages n of the booster circuit was 50, a value of about 91 V was obtained.

[0080] In the semiconductor booster circuit according to the present embodiment, the absolute value of the threshold voltage | V _t | when the a 0.6V, the lower limit of the booster can be the power supply voltage V _dd is approximately 0.7 V.

Next, a semiconductor booster circuit according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a second embodiment of the present invention.

Referring to FIG. 7, n P-channel MOS transistors Q _{30 to} Q ₃₄ are connected in cascade to form an n-stage booster circuit. Substrate portion of each of the transistors Q ₃₀ to Q ₃₄ may together are electrically isolated, the substrate portion and the gate terminal connected to each source terminal N ₃₁ to N _35. And, to the terminal N ₃₀ ~N ₃₅ of each capacitance C ₃₀ ~C
Through _35, the clock signal phi _A or phi _B shown in FIG. 8 is input.

In the booster circuit of this embodiment, the power supply voltage _Vdd is applied as an input signal to the P-channel MOS transistor Q _36.
Is input from the source terminal N ₃₇ to the drain terminal N ₃₀ of the transistor Q _30, as an output signal, the output voltage V _POUT is P
Output terminal N ₃₆ via channel MOS transistor Q ₃₅
Output from

As shown in FIG. 8, clock signals φ _A and φ _B are signals having phases opposite to each other, and have an amplitude of voltage Vφ.

The transistors Q _{30 to} Q _{30 of} this embodiment
The element structure of ₃₄ may be similar to that of FIG. That is, an N-well region 11 is formed in a P-type semiconductor substrate 10, each N-well region 11 has a polycrystalline silicon layer 16 formed via a gate oxide film 15 as a gate electrode, and P ⁺
A MOS transistor having the diffusion layer 12 as a source / drain is formed.

P ⁺ diffusion layer 1 on the source side of each transistor
2 is connected to the N well region 11 via the N ⁺ diffusion layer 14, and the source of the preceding transistor is connected to the drain of the following transistor. As a result, the N well region 11 serving as the substrate of each transistor is fixed at the source potential of each transistor, and the substrate effect is prevented.

Further, P ⁺ on the drain side of each transistor
PN formed between diffusion layer 12 and N well region 11
When the junction is forward-biased, the N ⁺ diffusion layer 1 is removed from the N well region 11 of the substrate through this PN junction.
The transfer of the electric charges at the nodes N _A → N _B and N _B → N _D is performed via the switch 4. In the case of this embodiment, the first
As shown in FIGS. 5 (II) and (V) of the embodiment, there is no state where each transistor is substantially completely conducting, and the transfer of electric charge from the preceding stage to the succeeding stage is performed through the PN junction described above. Therefore, in the case of this embodiment, the potential difference of the forward junction bias voltage V _F (usually about 0.7 V) of the PN junction independent of the threshold voltage V _t of the MOS transistor is used for boosting. V in the above equations (1) and (2)
V _F will be used instead of _t . This forward junction bias voltage V _F of the PN junction is not affected by the body effect, it is possible to realize a booster circuit does not cause a reduction in the boosting capability due to the substrate effect increasing the number of stages of the booster circuit.

More specifically, in this embodiment, as shown in FIG. 7, by electrically connecting the substrate portions of the transistors Q _{30 to} Q ₃₄ to the source terminals N _{31 to} N ₃₅ , between the source and the drain of Q ₃₀ ~Q _34, PN is formed at the boundary between the drain and the substrate portion
The structure is such that the junctions are connected in parallel. When the charge is sent to the next stage in the booster circuit, this PN
By turning the junction on, each transistor Q
Because it can fix the potential of the substrate of ₃₀ to Q ₃₄ to the potential difference between the forward junction bias voltage V _F of the PN junction (usually about 0.7 V), it can suppress the influence of the substrate effect by this.

[0090] That is, in the semiconductor booster circuit according to the second embodiment of the present invention, in the above-mentioned (1) (2), can be used forward junction bias voltage V _F in place of the threshold voltage V _t in particular, in the case the threshold voltage V _t is larger than the forward junction bias voltage V _F, the voltage drop upon delivery of the charge to the next stage in the booster circuit, the threshold voltage V _t and the forward junction bias voltage since decreasing by the voltage difference between V _F, it is possible to improve the boosting capability of the booster circuit. That is, the voltage drop at the time of sending the electric charge to the next stage is
It depends smaller one of the threshold voltage V _t and the forward junction bias voltage V _F.

For example, when the power supply voltage _Vdd is 2.5 V and the number of stages n of the booster circuit is 20, the capacitance ratio C / (C
+ C _s ) is 0.9, the absolute value of the threshold voltage | V _t | is 0.6 V, the load current I _OUT at the output stage is 0 A, and the forward junction bias voltage V _F of the PN junction is 0.7 V. At this time, in the conventional circuit, only 20 V could be obtained as the output voltage V _POUT , but in the circuit according to the second embodiment of the present invention, ₃₃ V was obtained.
The value of the degree was able to be obtained.

For example, when the power supply voltage V _dd is 2.0 V, the capacitance ratio C / (C + C _s ) is 0.9, the absolute value of the threshold voltage | V _t | The load current I _OUT at 0 A, the forward junction bias voltage V _{F of the} PN junction
Is 0.7 V, in the conventional circuit, the number of stages n of the booster circuit is n.
Although the output voltage V _POUT could only be obtained at 12 V even at 50 stages, the circuit according to the second embodiment of the present invention could obtain a value of about 23 V at 20 stages of the booster circuit, When the number of stages n of the booster circuit was 50, a value of about 56 V could be obtained.

In the semiconductor booster circuit according to the second embodiment of the present invention, the forward junction bias voltage V _F of the PN junction is set to 0.7.
V, when the capacitance ratio C / (C + C _s) 0.9, the lower limit of the booster can be the power supply voltage V _dd is approximately 0.8V.

Next, a semiconductor booster circuit according to a third embodiment of the present invention will be described with reference to FIGS.

FIG. 9 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a third embodiment of the present invention.

[0096] In FIG. 9, n pieces of N-channel MOS transistor Q ₄₀ to Q ₄₄ constitute a booster circuit cascade has been n stages. Substrate portion of each of the transistors Q ₄₀ to Q _44, together are electrically isolated, the substrate portion and the gate terminal connected to each source terminal N ₄₀ to N _44. Then, the terminal N ₄₀ to N ₄₄ of each capacitance C ₄₀ -C
Through _44, the same clock signal phi _A or phi _B as shown in FIG. 8 is input.

[0097] In accordance with the step-up circuit in this embodiment, as the input signal, the power supply voltage V _dd is input from the source terminal N ₄₇ of N-channel MOS transistor Q ₄₅ to the terminal N _40, as an output signal, the output voltage V _POUT is N-channel is output from the output terminal N ₄₆ via the MOS transistor Q _44.

The transistors Q _{40 to} Q ₄₄ according to this embodiment
FIG. 10 shows the element structure of FIG.

In FIG. 10, a P-type semiconductor substrate 50
A well region 51 is formed, and each P well region 51 has
A MOS transistor having a polycrystalline silicon layer 56 formed via a gate oxide film 55 as a gate electrode and having an N ⁺ diffusion layer 52 as a source / drain is formed.

N ⁺ diffusion layer 5 on the source side of each transistor
2 is electrically connected to the P well region 51 in which the transistor is formed via the P ⁺ diffusion layer 54, and the source of the preceding transistor is connected to the drain of the subsequent transistor.

As a result, the P well region 51 serving as the substrate of each transistor is fixed at the source potential of each transistor, and the substrate effect is prevented.

The N ⁺ on the drain side of each transistor
A PN junction is formed between the diffusion layer 52 and the P well region 51. When a forward bias is applied to the PN junction during operation, the substrate region of each transistor becomes PN junction.
Since the junction is fixed by the forward bias, this also prevents the substrate effect.

As described above, in the semiconductor booster circuit according to the third embodiment of the present invention, the substrate portions of the MOS transistors are electrically insulated and separated from each other, and the substrate portions are electrically connected to the source terminals of the MOS transistors. by connecting, it is possible to prevent an increase in the threshold voltage V _t due to the substrate effect, it is possible to obtain the output voltage V _POUT proportional to the number of stages n of the semiconductor booster circuit.

Further, as shown in FIG.
P-well region 5 the transistors Q ₄₀ to Q ₄₄ are formed
1 may be formed separately, and the P ⁺ impurity region 54 of each P well region 51 and the N ⁺ impurity region 52 on the source side of each of the transistors Q _{40 to} Q ₄₄ may be electrically connected. The process does not increase.

[0105] Also, by connecting the substrate of the transistor Q ₄₀ to Q ₄₄ source terminal N ₄₀ to N ₄₄ and electrically, between the source and the drain of each transistor Q ₄₀ to Q _44, drain PN junction formed at the boundary between the substrate and the substrate is connected in parallel. Then, at the time of delivery of the charge to the next stage in the boosting circuit, by turning on the PN junction, the transistors Q ₄₀ to Q ₄₄
Of the PN junction is applied to the forward junction bias voltage V
_Since the potential difference can be fixed to _F (normally about 0.7 V), the effect of the substrate effect can be suppressed by this as well.

[0106] That is, in the semiconductor booster circuit according to the third embodiment of the present invention can be used in the above-mentioned (1) (2), the forward junction bias voltage V _F in place of the threshold voltage V _t . In particular, when the threshold voltage V _t is larger than the forward junction bias voltage V _F is the voltage drop at the time of delivery of the charge to the next stage in the boosting circuit is reduced, improving the boosting capability of the booster circuit Can be.
That is, the voltage drop upon delivery of the charge to the next stage is determined by smaller one of the threshold voltage V _t and the forward junction bias voltage V _F.

For example, when the power supply voltage _Vdd is 2.5 V and the number of stages n of the booster circuit is 20, the capacitance ratio C / (C
+ C _s ) is 0.9, the absolute value of the threshold voltage | V _t | is 0.6 V, the load current I _OUT at the output stage is 0 A, and the forward junction bias voltage V _F of the PN junction is 0.7 V. At this time, in the conventional circuit, only 20 V could be obtained as the output voltage V _POUT , but in the circuit according to the third embodiment of the present invention, ₃₃ V was obtained.
The value of the degree was able to be obtained.

For example, when the power supply voltage V _dd is 2.0 V, the capacitance ratio C / (C + C _s ) is 0.9, the absolute value of the threshold voltage | V _t | The load current I _OUT at 0 A, the forward junction bias voltage V _{F of the} PN junction
Is 0.7 V, in the conventional circuit, the number of stages n of the booster circuit is n.
Although the output voltage V _POUT could only be obtained at 12 V at 50 stages, the circuit according to the third embodiment of the present invention could obtain a value of about 23 V at 20 stages of the booster circuit, When the number of stages n of the booster circuit was 50, a value of about 56 V could be obtained.

In the semiconductor booster circuit according to the third embodiment of the present invention, the forward junction bias voltage V _F of the PN junction is set to 0.7.
V, when the capacitance ratio C / (C + C _s) 0.9, the lower limit of the booster can be the power supply voltage V _dd is approximately 0.8V.

While the semiconductor booster circuits according to the first to third embodiments of the present invention have been described above, the circuit according to the first embodiment reduces the voltage drop when sending charges to the next stage substantially to zero.
Therefore, the circuit has a larger boosting capability than the circuits according to the second and third embodiments. In particular, 0.8-
At a power supply voltage _Vdd of about 2.0 V, the difference between the boosting capabilities becomes remarkable.

In particular, a power supply voltage V of about 0.8 to 2.0 V
_{In dd} , in order to obtain a desired output voltage, in the circuits according to the second and third embodiments, it is necessary to increase the number n of stages of the booster circuit due to a voltage drop at the time of sending charges to the next stage. However, this is not necessary in the circuit according to the first embodiment. For example, when the power supply voltage _Vdd is 2.0 V, in the circuits according to the second and third embodiments, the output voltage V _POUT
The number of stages n of the booster circuit required to obtain 23 V
Although there are zero stages, the circuits according to the second and third embodiments may have twelve stages.

On the other hand, the circuits according to the second and third embodiments have a simpler structure than the circuit according to the first embodiment.
There is an advantage that only two types of clock signals are required.

[0113]

According to the present invention, a gate terminal and a source terminal of a MOS transistor are electrically connected to each other, and the source terminal and a substrate are electrically connected to each other. Since the stage is electrically insulated from the substrate of the MOS transistor, one stage can be realized with a simple configuration including only one MOS transistor and one capacitance, and the substrate effect can be prevented, and high boosting can be achieved. You can gain the ability.

Further, there is no need for a particularly complicated manufacturing process.

Further, when obtaining the same boosting ability as the conventional one,
The number of stages of the booster circuit can be reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of two consecutive stages of the semiconductor booster circuit according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram showing clock timing of the semiconductor booster circuit according to the first embodiment of the present invention.

FIG. 4 is a waveform diagram showing voltage waveforms at each node of the semiconductor booster circuit according to the first embodiment of the present invention.

FIG. 5 is a conceptual diagram for explaining an operation of the semiconductor booster circuit according to the first embodiment of the present invention.

FIG. 6 is a schematic sectional view showing an element structure of the semiconductor booster circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a second embodiment of the present invention.

FIG. 8 is a waveform diagram showing clock timing of a semiconductor booster circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a third embodiment of the present invention.

FIG. 10 is a schematic sectional view showing an element structure of a semiconductor booster circuit according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a conventional semiconductor booster circuit.

FIG. 12 is a waveform diagram showing clock timing of a conventional semiconductor booster circuit.

FIG. 13 is a graph showing the relationship between the number of stages and the output voltage of a conventional semiconductor booster circuit.

FIG. 14 is a graph showing a relationship between a power supply voltage and a maximum output voltage of a conventional semiconductor booster circuit.

[Explanation of symbols]

_{Q 1 ~Q 11, Q 30 ~Q} 36, M 1 ~M 4 P -channel MO
S transistor _{Q 12 ~Q 13, Q 40 ~Q} 45 N -channel MOS transistor _{C 1 ~C 11, C 30 ~C} 35, C 40 ~C 44, C A1 ~C A3, C
_B1, C _B2 capacitance V _dd supply voltage V _pout output voltage _{φ 1A, φ 1B, φ 2A} , φ 2B, φ A, φ B clock signal _{N 0 ~N 12, N 30 ~N} 37, N 40 ~N 47, N _A to N _D node 10 P-type semiconductor substrate 11 N-well region 12 and 51 P ⁺ impurity regions 14 and 52 N ⁺ impurity regions 15 and 55 the gate oxide film 16, 56 a polysilicon layer 50 N-type semiconductor substrate 51 P-well region

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/07 H01L 27/10

Claims (3)

(57) [Claims] 1. Each of the stages includes a MOS transistor and the M transistor.
Consists of a capacitance having one end to the drain terminal is connected to OS transistor, said MOS transistors are each stage connected by being cascaded, the gate terminal and the source terminal and the electrical each other of said MOS transistors in each stage Wherein the source terminal and the substrate are electrically connected to each other, and the substrate is electrically insulated from the substrate of the MOS transistor in another stage. circuit. 2. The method according to claim 1 , further comprising the step of :
A pair of clock signals having phases opposite to each other are input to the ends, respectively.
The semiconductor booster circuit according to claim 1, wherein 3. The MOS transistor is an N-channel MOS transistor formed in a P-type well region,
3. The semiconductor booster circuit according to claim 1, wherein the P-type well region is electrically insulated and separated for each stage.