JP3352246B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refractory metal film, a silicon carbide film, and a semiconductor device having electrodes or wirings using the silicon film and a method of manufacturing the same.

[0002]

2. Description of the Related Art Hitherto, the speeding up of semiconductor devices such as LSIs has been promoted by the reduction (scaling) of element dimensions based on miniaturization technology. However, in the sub-micron generation, speeding up by scaling is already a limit, and it is necessary to reduce internal wiring resistance by introducing new materials.

In particular, word lines in which an RC delay is remarkable exhibit a polycide gate structure composed of two layers of a refractory metal silicide and a polycrystalline silicon film to reduce wiring resistance. Particularly widely used tungsten silicide (WSi _x) is this type of gate material, about one order of magnitude lower resistance compared to conventional polycrystalline silicon film.

However, as miniaturization advances, even the resistance of the polycide gate cannot be ignored. If the wiring width is 0.25μ due to the polycide structure
When a gate electrode having a m and a sheet resistance of 1 Ω / □ or less is realized, the thickness of the silicide layer is about 1 μm, and the aspect ratio of the gate electrode is very high, 4 to 5. As a result, it becomes difficult to process a gate electrode pattern and to form an interlayer film on the electrode. Therefore, it is necessary to use a material having a lower specific resistance than metal silicide as a gate electrode material.

As an attempt to reduce the resistance, a polymetal gate having a two-layer structure of a refractory metal film and a polycrystalline silicon film has attracted attention. For example, tungsten (W) film resistance of about 1 order of magnitude lower than that WSi _x its silicide, significant reduction in the RC delay can be expected.

FIGS. 4A to 4C show an n-type MO using a stacked structure of a tungsten film / polycrystalline silicon film for a gate electrode.
FIG. 4 is a cross-sectional view of the SFET for each process, and a method for manufacturing the SFET will be described below.

First, LOCOS (Lo) is formed on a silicon substrate 1.
wcal Oxidation of Silicon
A field insulating film 10 is formed by a method or the like, and a silicon oxide film 2 having a thickness of about 7 nm is formed on the surface of the substrate 1 surrounded by the field insulating film 10 by thermal oxidation or the like. Further LP
CVD (Low Pressure Chemical Chemical)
Vapor Deposition method, etc.
A polycrystalline silicon film 3 is formed to a thickness of about 100 nm. Thereafter, n-type impurities such as A
s, P, etc. are added to the polycrystalline silicon film 3. Subsequently, FIG.
As shown in (a), a dangsten film 4 is formed to a thickness of about 100 nm by a sputtering method. Next, a resist pattern (not shown) is formed by a lithography process, and using this as a mask, the tungsten film 4, the polycrystalline silicon film 3, and the oxide film 2 are subjected to RIE (Reactive I
patterning into a gate shape by an on-etching method or the like. This RIE method uses a mixed gas of SF ₆ and Cl ₂ , a high frequency applied power of 0.7 W / cm ² and a pressure of 10 m.
Torr, flow rate SF ₆ / Cl ₂ = 40/10 SCCM, and the electrode is maintained at 70 ° C.

After that, an n-type impurity such as As is ion-implanted into the surface of the substrate 1, and RTA (Rapiel Thermo) is performed.
By performing a heat treatment at 1000 ° C. for 20 seconds according to the method described in FIG.
The drain diffusion layer 5 is formed.

Subsequently, an insulating film such as an oxide film is formed on the surface of the substrate 1 by a CVD method or the like.
An opening for contact is formed. Then, as shown in FIG. 4C, a metal wiring 7 of Al or the like is formed in this opening,
The conventional MOSFET is completed.

However, a high melting point metal film such as W is deposited on a polycrystalline silicon film, and after processing the gate electrode, heating at about 600 ° C. or more to increase the thickness of the edge of the gate insulating film causes silicide. turned into, the changes to the WSi _x, resistance there is a problem that the rise. In order to prevent this silicidation reaction, a structure has been proposed in which a metal compound such as titanium nitride (TiN) is inserted as a reaction preventing layer between a high melting point metal film and a polycrystalline silicon film. However, when the three-layer structure is processed into a wiring pattern and then subjected to a process of selectively oxidizing only silicon without oxidizing W, a granular titanium oxide (100 to 1000 angstroms) is formed directly on the sidewall of TiN. TiO ₂ ) is formed. Therefore, an insulating film such as a silicon oxide film or a silicon nitride film is vapor-phase grown thereon (C
There is a problem that it is difficult to form a uniform film when depositing by the VD) method.

Therefore, in order to realize a polymetal gate, a reaction prevention layer for suppressing the reaction of high melting point metal silicon is required. This reaction prevention layer needs to have oxidation resistance such as an insulating film. Here, it is known that when the insulating film is present on the silicon surface, the reaction between the refractory metal and silicon is suppressed. However, insulators such as silicon oxide act as barriers for electrons and holes, and may cause an increase in contact resistance between the metal and the polycrystalline silicon film. This contact resistance risks increasing the RC delay.

Therefore, it is desirable that the reaction preventing layer not only suppresses the reaction between the high melting point metal and the polycrystalline silicon but also has a low contact resistance and excellent conductivity. On the other hand, with the miniaturization of elements, dimensional control and processing shapes have become very problematic. In particular, since the dimensions of the gate electrode significantly affect the performance of the element itself, a processing technique having a small difference in dimensional conversion during processing and having an excellent shape is essential.

In the dry etching step such as the RIE method among the above-described manufacturing steps, etching is performed for a time corresponding to the actual film thickness of the film to be processed + α. The time corresponding to α is called over-etching. This is because there is a step in the actual substrate to be processed, and the apparent film thickness increases at the step in dry etching which proceeds in the vertical direction. Inevitably, it is necessary to overetch by the film thickness caused by the step.

However, since there is no selectivity of the tungsten film 4 with respect to the underlying polycrystalline silicon film 3, the polycrystalline silicon film 3 is largely removed when the tungsten film 4 is over-etched.

In the above-described step of etching the tungsten film 4, the tungsten film 4 has a thickness of about 180 nm / min.
, While the polycrystalline silicon film 3 is about 70
Since the etching was performed at 0 mm / min, the selectivity between the tungsten film 4 and the polycrystalline silicon film 3 was about 0.3.
Although the description has been given of the polycrystalline silicon film here, the selectivity of single crystal silicon is a low value of 1 or less. This makes it impossible to form a good electrode pattern for the MOS transistor.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a low-resistance electrode or semiconductor device having an excellent processed shape and a method of manufacturing the same.

[0017]

In order to solve the above problems, the present invention provides a silicon film formed on a gate insulating film,
A metal film formed on the silicon film and a gate electrode of a laminated structure comprising a reaction prevention layer of a silicon carbide film containing an excessive amount of carbon atoms formed between the silicon film and the metal film, The silicon carbide film has 50 atoms of carbon atoms.
Provided is a semiconductor device characterized by being contained in a range of more than ic% and 75 atomic% or less.

The silicon carbide film may contain an electrically active impurity. The silicon carbide film may have a thickness of 5 nm or more. The metal film may be a tungsten film. A silicon nitride film may be further formed on the metal film.

Further, the present invention provides a step of depositing a silicon film on a semiconductor substrate, and adding 5 carbon atoms to the surface of the silicon film.
A step of forming a silicon carbide film containing more than 0 atomic% and not more than 75 atomic%, and selectively anisotropically etching the silicon film, the silicon carbide film and the metal film to form a gate electrode having a laminated structure or Forming a wiring, and a method for manufacturing a semiconductor device. In the step of forming the silicon carbide film, a carbon film is formed on the silicon film, and ions are implanted from the carbon film to form carbon atoms and silicon atoms at the interface between the carbon film and the silicon film. A mixing step may be provided. The ions are
It may be an electrically active impurity.

[0020]

In the above-mentioned structure, it is possible to realize a wiring or an electrode having sufficient heat resistance and low resistance by inserting a silicon carbide film between the high melting point metal film and the silicon film. is there. That is, the silicon carbide film is a material that is extremely stable thermally and chemically, and has a diffusion rate in silicon carbide that is about two orders of magnitude lower than that of silicon. Therefore, it can be expected to be used as a reaction prevention layer for suppressing mutual diffusion. Further, since it is electrically a semiconductor, it can be a reaction prevention layer having excellent conductivity.

Further, with the structure of the refractory metal film / silicon carbide film / silicon film, it is possible to selectively etch the refractory metal film with respect to the silicon carbide film, and to perform etching with an excellent processed shape. It is possible to do.

[0022]

Embodiments of the present invention will be described below.
FIG. 1H is a completed sectional view when the embodiment of the present invention is applied to a gate electrode of a MOSFET. The gate portion is composed of a polycrystalline silicon film 12a, a silicon carbide film 15a, a tungsten film 13a, a silicon nitride film 17a, and the like. Since the gate portion has the silicon carbide film 15a inserted between the polycrystalline silicon film 12a and the tungsten film 13a, the gate portion functions as a reaction preventing layer between the heat-treated polycrystalline silicon film 12a and the tungsten film 13a, Low resistance has been achieved. Also, the presence of the silicon carbide film 15a when etching the tungsten film causes the polycrystalline silicon film 1
2a is not etched and has little influence on the polycrystalline silicon layer 12a, so that it has a good gate shape.

Here, FIGS. 1A to 1H are cross-sectional views for respective steps when the present embodiment is applied to a MOSFET, and a manufacturing method thereof will be described below. First, FIG.
As shown in FIG.
(Film thickness: 7 nm) is deposited to a thickness of 100 nm, and an electrically active impurity is added to the polycrystalline silicon film 12 by a vapor phase diffusion method.

Thereafter, as shown in FIG. 1B, the polycrystalline silicon film is heated to about 800 ° C. in a carbon-based gas such as C _{2 in a} hydrocarbon-based gas atmosphere such as C ₃ H ₈ gas. A silicon carbide film 15 (10 nm thick) was formed on the substrate 12.

Further, as shown in FIG. 1C, a tungsten film 13 (100 nm thick) is formed by sputtering.
m) was deposited. Here, as a result of measuring the resistance after the heat treatment at 900 ° C., no increase in the resistance was observed, but the resistance was decreased. This means that the silicon carbide film 15 functions as a reaction preventing layer, and the tungsten film 13 and the polycrystalline silicon film 12 do not react.

Thereafter, the silicon nitride film 1 is formed by a CVD method or the like.
7 (150 nm) is deposited. Next, as shown in FIG. 1D, a photoresist is applied on the silicon nitride film 17 by a spin coating method (thickness: about 1 μm), exposed and developed through a photomask, and a predetermined resist pattern 18 is formed. You.

Next, using a dry etching apparatus,
The silicon nitride film 17, the tungsten film 13, the polycrystalline silicon film 12, and the like are etched along the resist pattern 18.

The apparatus includes an etching chamber 1 as shown in FIG.
, A preparatory chamber 200 and a preparatory discharge chamber 300.
And the preliminary discharge chamber 300 are separated by a gate valve. The substrate to be etched 101 is introduced from the gate valve 202 disposed in the preliminary introduction chamber 200 while the etching chamber 100 is kept in a vacuum, and the gate valve 30 disposed in the preliminary discharge chamber 300.
By discharging the substrate to be etched 101 from 2, it is possible to avoid the adverse effects of the air atmosphere and dry-etch the substrates one by one in a short time. Further, in the preliminary chambers 200 and 300, the substrate mounting tables 202, 3
03 are respectively installed.

The etching chamber 100 includes an electrode 102 on which a substrate 101 to be etched is placed.
Reference numeral 02 includes a cooling pipe 103 for controlling the substrate 101 to be etched at a desired temperature. Further, the electrode 102
Is connected to a high frequency power supply 106 via a blocking capacitor 104 and a matching device 105 so as to apply 13.56 MHz high frequency power for plasma excitation.

A reaction gas is supplied from the reaction gas supply line 400 into the etching chamber 100 after being adjusted to a desired flow value by the valve 401 and the flow controller 402.
Further, the etching chamber 100 is controlled by the control valve 403.
The inside is maintained at a constant pressure.

The inner wall (upper wall) of the etching chamber 100
Is grounded, and a high-frequency voltage is applied between the electrode 102 and the electrode 102. A permanent magnet 107 is provided above the upper wall of the etching chamber 100 and is rotated around a rotation shaft 108 by an electromagnetic motor. The magnetic field of about 200 gauss generated by the permanent magnet 107 is configured to be able to generate and maintain a high ion density plasma even in a high vacuum of the order of 10 ⁻³ Torr. A large amount of ions are irradiated on the substrate 101 to be etched from the high ion density plasma generated in this manner, and etching is performed.

Using such an etching apparatus, FIG.
As shown in FIG. 3E, the silicon nitride film 17 is formed using CHF ₃ and CF _{4 using the} resist pattern 18 as an etching mask.
Then, the resist pattern 18 is removed by oxygen plasma.

Next, as shown in FIG. 1F, using the silicon nitride film 17 as an etching mask,
Was anisotropically etched using a mixed gas of SF ₆ and chlorine. Etching conditions are high frequency applied power 0.7 W / cm
² , pressure 10 mTorr, flow rate SF ₆ / Cl ₂ = 40 /
At 10 SCCM, the electrodes were kept at 70 ° C. Under this etching condition, the tungsten film 13 has a thickness of about 180 nm /
Minute, while the silicon nitride film 17 is etched at about 60 nm / min.
And the selectivity of the silicon nitride film 17 was about 3. On the other hand, since the silicon carbide film 15 was etched at 35 nm / min, the selectivity between the tungsten film 3 and the silicon carbide film 15 was about 5.

It is assumed that the thickness of the tungsten film 13 (100
In the case where overetching is performed for a time corresponding to 30% of (nm), the thickness of the silicon carbide film 15 under the tungsten film 13 is about 6 nm. Therefore, the silicon carbide film 15 becomes the tungsten film 1
Because of the selectivity to 3, the polycrystalline silicon film is not greatly shaved.

Thereafter, as shown in FIG. 1 (g), the silicon carbide film 15 is etched using a mixed gas of CF ₄ , H ₂ and O ₂ using the silicon nitride film 17 as an etching mask. Etching conditions are high frequency applied power 0.7 W / cm
² , pressure 10 mTorr, flow rate CF ₄ / H ₂ / O ₂ = 4
The electrode was kept at 70 ° C. with 0/10/1 SCCM. Under these etching conditions, silicon carbide film 15 has a thickness of about 18 nm /
Minute, while the silicon nitride film 17 is etched at about 100 nm / min.
And the selectivity of the silicon nitride film 17 was about 2.

Since the selectivity with respect to the lower polycrystalline silicon film 12 is about 2, the overetching of the silicon carbide film 15 does not affect the polycrystalline silicon film 12 so much. Further, the polycrystalline silicon film 12 is anisotropically etched with a mixed gas of HBr and O _{2 using} the silicon nitride film 17, the tungsten film 13, and the silicon carbide film 15 as an etching mask, and has a polymetal structure (W / SiC / polySi). A gate electrode pattern is formed. Finally, the source / drain region 18 is formed by ion implantation or the like and heat treatment, and the interlayer insulating film 19 and the wiring 20 for the source / drain electrode are formed to form the MOSFET according to the present embodiment as shown in FIG. Complete.

As described above, by sandwiching the silicon carbide film between the high melting point metal film and the polycrystalline silicon film, the high melting point metal film can be selectively and anisotropically etched. The silicon carbide film inserted in this embodiment will be described in detail below. The silicon carbide film has a stoichiometrically stable composition (S
i: C = 1: 1) and a state in which excess Si atoms or C atoms and SiC phases are mixed.

As described above, a film containing an excessive amount of C atoms is preferable for use as a reaction prevention layer. This is because the diffusion constant of C atoms in the metal film is extremely small, and is less likely to react with a high melting point metal such as W than Si atoms.
In addition, since the film containing excessive C atoms has a high density, the film also has an effect of preventing diffusion of Si atoms which easily react with the high melting point metal.

On the other hand, when the C atoms in the film are 75 atomic%
If the amount is increased, there is a property that the oxidation resistance is deteriorated when heated. The silicon carbide film used from the above is preferably a film containing carbon atoms in the range of 50 to 75 atomic%.
Particularly, a film in which carbon atoms are around 50 atomic% is most suitable.

Further, the resistance of the silicon carbide film can be reduced by adding an electrically active impurity which is a semiconductor. When a silicon carbide film is formed by performing a heat treatment in a C ₃ H ₈ gas atmosphere as described above, by introducing PH ₃ gas together with C ₃ H ₈ gas, the resistance of the silicon carbide film is 100 to several thousand Ω.
/ □ value was obtained. This is almost the same resistance value as the polycrystalline silicon film. The electrically active impurities include n-type N, As, Sb and the like such as P in PH ₃ , and B, Al, Ga and the like for the P-type. By introducing the gas containing these active species simultaneously with the C ₃ H ₈ gas,
A low-resistance silicon carbide film can be formed. Further, it is also possible to add an impurity to the underlying polycrystalline silicon film in advance, or to perform thermal diffusion using the contained polycrystalline silicon film.

The method of forming the silicon carbide film 15 is not limited to the method described above, but may be a method of discharging a gas containing carbon to generate plasma and exposing the surface of the polycrystalline silicon film 12 to plasma. Further, a method of depositing the silicon carbide film 15 on the polycrystalline silicon film 12 in a mixed gas atmosphere containing carbon and silicon is also possible.

Next, an embodiment of another method for forming an electrode having a tungsten / silicon carbide / polycrystalline silicon structure of a MOS type field effect transistor will be described. First, FIG.
1A, a thin silicon oxide film 21 (thickness: 7 nm) is formed on a substrate 20 made of single-crystal silicon, and a polycrystalline silicon film 22 (thickness: 10 nm) is formed thereon by a CVD method.
0 nm). Thereafter, an electrically active impurity is added to the polycrystalline silicon film 22 by a vapor phase diffusion method.

Next, as shown in FIG. 2B, a carbon film 26 (100 nm) is formed on the polycrystalline silicon film 22 by sputtering.
m). Further, as shown in FIG. 2C, silicon ions (Si ⁺ ) are implanted from above the carbon film 26 under the conditions of, for example, an acceleration voltage of 50 keV and an implantation amount of 5 × 10 ¹⁵ cm ⁻³ . This acceleration voltage is set so that the projected range of the implanted ion species overlaps the vicinity of the interface between the polycrystalline silicon film 22 and the carbon film 26. With the ion implantation, atomic mixing occurs at the interface between the polycrystalline silicon film 22 and the carbon film 26, and the silicon carbide film 25
(10 nm) is formed. The composition of this film was such that C atoms were formed at a rate of about 60%.

Here, the thickness of the silicon carbide film 25 depends on the ion implantation amount. When the implantation amount is less than 5 × 10 ¹⁵ cm ⁻³ , the film thickness to be formed becomes 5 nm or less, and C Since the proportion of atoms is larger than 75%, it cannot be used as the above-mentioned reaction preventing layer. Thus, the necessary implantation dose for silicon (mass number about 28) ions can be 5 × 10 ¹⁵ cm ⁻³ or more. This is almost inversely proportional to the mass number of the implanted ion species,
In the case of As (mass number about 75), it is about 2 × 10 ¹⁵ cm ⁻³ or more.

On the other hand, the injection amount of silicon ions is 1 × 10 ¹⁷
If it is larger than cm ^-3 , the concentration of Si atoms increases in the depth direction, but the ratio of C atoms directly under the refractory metal film is 50%.
Since it falls within the range of ~ 75%, it is effective as a reaction preventing layer.

Thereafter, as shown in FIG. 2D, the carbon film 26 is formed in an oxygen plasma or an oxidizing atmosphere at about 600 ° C.
Is peeled off. The silicon carbide film 25 formed here has high oxidation resistance and is not peeled off even when exposed to the above oxidizing atmosphere.

Next, as shown in FIG. 2E, a tungsten film 23 (100 nm thick) is formed by sputtering.
m) was deposited. Thereafter, even after a heat treatment at 800 to 900 ° C., the wiring resistance of the present structure did not deteriorate. Therefore, it is understood that the silicon carbide film 25 formed by the atomic mixing accompanying the ion implantation is effective as the reaction preventing layer.

It should be noted that by selecting an electrically active impurity ion as an ion implantation species in the above steps, it can be used together with doping of the polycrystalline silicon film 22, and by selecting the conductivity type of the impurity ion, a desired type can be obtained. It is possible to obtain a resistance value. Further, after the atoms are mixed by ion implantation, a heat treatment is performed so that the dense silicon carbide film 25 is formed.
Can be formed, and the effect of the reaction preventing layer increases.

Then, following FIG. 2E, FIGS.
The gate electrode of this embodiment is formed by processing the gate electrode by etching, forming source / drain diffusion layers, forming an interlayer insulating film and the like in the same manner as in the first embodiment shown in FIG. You. Here, since the etching apparatus and gas type used for the etching are the same, the first embodiment is referred to. The effect of the etching selectivity can be obtained in the same manner as described in the first embodiment.

In each of the above embodiments, the tungsten film and the polycrystalline silicon film have been described as the laminated films in which the silicon carbide film is inserted. However, the present invention is not limited to tungsten, and the selectivity with the underlying silicon film is small and about 600 ° C. Any metal that produces a metal silicide by heat treatment is applicable, and is not limited to a polycrystalline silicon film. Even if the film is made of amorphous silicon or the like, the above effects can be sufficiently obtained.

Further, in each of the above embodiments, the MOSF
Although the ET gate electrode has been described, it can be used as an electrode material for other transistors such as a bipolar transistor.
It can be used as a wiring material for a semiconductor memory device, a semiconductor integrated circuit, and the like. These devices have particularly high demands for miniaturization, and have low resistance as in the present invention, and a structure with good processing control can satisfy these requirements.

[0052]

According to the present invention, a wiring or a gate electrode having excellent heat resistance and low resistance can be realized, and a high melting point metal film can be selectively processed.
A good processed shape without dimensional conversion difference can be obtained. As described above, the RC delay caused by the wiring resistance is greatly reduced, and the miniaturization and high speed of the semiconductor device can be achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a MOSFET to which an embodiment of the present invention is applied according to process.

FIG. 2 is a sectional view for explaining a method of forming a gate electrode according to another embodiment of the present invention.

FIG. 3 is a configuration diagram for explaining an etching apparatus used in an embodiment of the present invention.

FIG. 4 is a sectional view for explaining a related art of the present invention, which is performed by each process.

[Explanation of symbols]

 1, 10, 20: silicon substrate 2, 11, 21, silicon oxide film 3, 12, 22, polycrystalline silicon film 4, 13, 23: tungsten film 5, 105: source / drain diffusion layer 15, 25: silicon carbide Film 7, 17 Silicon nitride film 18 Resist pattern 6, 19 Interlayer insulating film 7, 20 Source / drain electrode 26 Carbon film 100 Etching chamber 101 Substrate to be etched 102 Electrode 103 Cooling tube 106 High frequency Power supply 200: introduction spare room 300: exhaust spare room 400: gas supply line 405: flow controller

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768 H01L 21/28-21/288 H01L 21 / 44-21/445 H01L 29/40-29/43 H01L 29/47 H01L 29/872

Claims (8)

(57) [Claims] A silicon film formed on the gate insulating film;
A gate electrode having a laminated structure including a metal film formed on the silicon film and a reaction prevention layer of a silicon carbide film containing an excessive amount of carbon atoms formed between the silicon film and the metal film, A semiconductor device, wherein the silicon carbide film contains carbon atoms in a range of more than 50 atomic% and 75 atomic% or less. 2. The semiconductor device according to claim 1, wherein said silicon carbide film contains an electrically active impurity. 3. The semiconductor device according to claim 1, wherein said silicon carbide film has a thickness of 5 nm or more. 4. The semiconductor device according to claim 1, wherein said metal film is a tungsten film. 5. The semiconductor device according to claim 1, wherein a silicon nitride film is further formed on said metal film.
The semiconductor device according to any one of the above. 6. A step of depositing a silicon film on a semiconductor substrate; a step of forming a silicon carbide film containing carbon atoms in a range of more than 50 atomic% and 75 atomic% or less on the surface of the silicon film; Forming a gate electrode or a wiring having a laminated structure by selectively anisotropically etching the silicon carbide film and the metal film. 7. The step of forming the silicon carbide film includes forming a carbon film on the silicon film, and implanting ions from above the carbon film to form carbon atoms at an interface between the carbon film and the silicon film. 7. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of mixing silicon and silicon atoms. 8. The semiconductor device according to claim 7, wherein said ions are electrically active impurities.