JP3346323B2 - Display device drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a display device, and more particularly, to a driving circuit for a display device which performs multi-tone display.

[0002]

2. Description of the Related Art Many circuits have been proposed as drive circuits for driving a display device that performs multi-tone display.

For example, Japanese Patent Laid-Open Publication No. Hei 5-260417 discloses an N-bit shift register, an M-bit N latch circuit for storing image data, and a data signal held in each latch circuit. A drive circuit for a liquid crystal matrix display device including N switch circuits for selecting a combination of power supplies and an addition amplifier circuit for adding a voltage is proposed.

Japanese Patent Application Laid-Open No. Hei 9-101501 discloses that
The four reference voltages are combined two by two and a total of three combinations are output to two reference voltage lines at each of the three times, and each reference voltage line is provided with two analog switches for generating voltage, and these analog switches are provided. A drive device for a display device, in which a switch is turned on / off in any one of the above three times based on 8-bit 3-bit display data for a time shorter than the three times to apply an oscillating voltage to a source line, is proposed. are doing. According to this driving device, a low-pass filter function caused by the capacitance and resistance of the source line can be effectively used.

[0005] Japanese Patent Application Laid-Open No. Hei 9-138670 discloses that
A first bus line for sequentially scanning pixels in the liquid crystal display panel, and a second bus line for supplying a gradation voltage obtained by superimposing a staircase voltage for displaying image data to a selected pixel on the first bus line And a drive circuit for a liquid crystal display device including a staircase voltage generation unit that generates a staircase voltage from a plurality of reference power supplies.

The staircase voltage generating section is composed of a resistor voltage dividing means for dividing the voltage between each reference power supply by a plurality of divided resistors, and a set of a pair of switch elements provided at both ends of each divided resistor for switching the level of the staircase voltage. Step voltage level switching means. In the first period, one of a pair of switch elements at both ends of each divided resistor is made conductive,
In the second period, both of the switch elements are turned on.

Japanese Unexamined Patent Publication No. Hei 10-240192 discloses a method of applying a gamma correction voltage so that potential differences between adjacent terminals and taps of a series of string resistors are all equal, and a string between the adjacent terminals and taps. A multi-gradation liquid crystal driver has been proposed in which all the resistance values of the resistors are set substantially equal.

Japanese Patent Application Laid-Open No. Hei 10-301439 discloses a multi-value voltage generating means for generating a plurality of voltages, and a selecting circuit for selecting a voltage necessary for driving from the voltages generated by the multi-value voltage generating means. Proposed a drive circuit for a liquid crystal display device including an output circuit that inputs a voltage selected by the selection circuit and outputs a desired voltage to a drive circuit output terminal. An output circuit in the drive circuit includes an output circuit input terminal for inputting a selection voltage of the selection circuit, a drive circuit output terminal, a first voltage source, a second voltage source, and an input terminal and an output terminal. It comprises a connected switch, a PMOS transistor having a drain connected to the ground, a gate connected to the input terminal, a source connected to the output terminal, and a switch connected between the output terminal and the voltage source.

Also, "Society for Inf"
operation Display (SID) Int
electronic symposium dige
st of technical ”(S. Saito,
K. Kitamura), Vol. 26, 1995, 2
FIG. 1 also shows an example of a driving circuit of a liquid crystal display device.

FIG. 13 is a block diagram showing the configuration of the driving circuit. This drive circuit is a drive circuit for 240-output 6-bit digital video data.

The driving circuit shown in FIG. 13 includes a 90-bit shift register circuit 30, a data register circuit 31,
A data latch circuit 32, a ROM decoder circuit 33,
And an amplifier 34. The ROM decoder circuit 33
It is composed of an enhancement type transistor and a depletion type transistor.

When the sampling pulse signal is input to the shift register circuit 30, the shift register circuit 30 causes the digital video data D00-for 6 bits and three outputs.
D05, D10-D15, and D20-D25 are sequentially stored in the data register circuit 31.

Next, when the latch signal STB is input to the data latch circuit 32, the digital video data stored in the data register circuit 31 is transferred to the data latch circuit 32 all at once, and Is held.

According to the transferred digital video data,
One of the 64 gradation voltages V1-V64 in the ROM decoder circuit 33 is selected. The selected gradation voltage is subjected to impedance conversion by the amplifier 34, whereby a predetermined voltage is applied to the liquid crystal.

The 64-level gradation voltages in the ROM decoder circuit 33 are equivalent to 8-level gradation voltages V0-V7 input from the outside.
Can be obtained by dividing the voltage with a resistor.

As described above, a method of obtaining a gradation voltage by dividing a gradation voltage input from the outside by a resistor is generally called a "resistor string method". Among the above prior arts, the multi-tone liquid crystal driver disclosed in Japanese Patent Application Laid-Open No. H10-240192 also uses the resistance string method.

[0017]

According to the above-described conventional driving apparatus or driving method, a 6-bit (64 gradation) driving circuit can be realized without any problem. Then, the following problem occurs.

The first problem is that the chip size is increased when the semiconductor integrated circuit is manufactured. The reason for this is that, for example, according to the resistor string method, the size of the gray scale selection circuit section particularly increases as the number of gray scales increases. For example, a 64 gradation driver requires 64 ROM decoders per output. In contrast, 256
The grayscale driver requires 256 ROM decoders per output, that is, four times as many ROM decoders as the 64 grayscale driver, so that the element area increases and the chip size increases.

The second problem is that the test time in the inspection process of the semiconductor integrated circuit increases. When a multi-gradation driver is constituted by a plurality of ROM decoders, it is necessary to confirm the operation of all decoders. For example,
The 64-gradation driver has 64 ROM decoders, and it is necessary to confirm the operation of the 64 ROM decoders. Similarly, in the 256 gradation driver, it is necessary to confirm the operation of the 256 ROM decoders, so that the test time is four times that in the case of the 64 gradation driver.

As described above, the test time increases as the number of grayscale drivers increases, and the test cost increases accordingly.

The present invention has been made in view of the above-mentioned problems in the driving circuit of a conventional display device, and has been developed in view of the fact that an 8-bit display is used for a thin film transistor transistor liquid crystal display device and other display devices in multi-tone display. It is an object of the present invention to provide a drive circuit of a display device which realizes a reduction in the number of elements and a reduction in the element area of the digital drive circuit as described above, and can realize a reduction in the chip size of a semiconductor integrated circuit.

[0022]

According to the present invention, there is provided a driving circuit for a display device which displays a plurality of gradations in accordance with digital video data. A grayscale voltage generating circuit that divides a plurality of grayscale voltages input from the outside and generates a plurality of voltages between the plurality of grayscale voltages; A first selection circuit for selecting a first voltage in the adjustment voltage generating circuit, an operational amplifier for impedance-converting the first voltage, and an offset voltage for the operational amplifier according to a lower bit of the digital video data. The operational amplifier includes a differential circuit, and the offset voltage control circuit allows the offset voltage control circuit to control the digital video data to be zero. In some cases, it outputs the first voltage, when the digital video data is 1,
A voltage obtained by adding an offset voltage to the first voltage or a voltage obtained by subtracting an offset voltage from the first voltage is output, and the offset voltage control circuit includes a transistor,
A first switch and a second switch that are connected to and detachable from the transistor, and when the digital video data is at a low level, the first switch is on and the second switch is off. When a current does not flow through the transistor and the digital video data is at a high level, the first switch is turned off and the second switch is turned on, thereby providing a drive circuit of a display device in which a current flows through the transistor. .

The offset voltage control circuit in the present drive circuit may be configured such that the offset voltage is controlled by changing the value of a current flowing through one of the differential input transistors constituting the differential circuit. It can be configured to change the value of the voltage.

As the operational amplifier in the present drive circuit, for example, a voltage follower type operational amplifier can be selected.

[0025]

According to the drive circuit of the present invention, the first selection circuit selects one voltage Vk from a plurality of gradation voltages according to the upper bits of the digital video data. in this case,
For example, if a voltage follower type amplifier is selected as the operational amplifier, the operational amplifier outputs a voltage Vk. Usually, the two differential input transistors constituting the operational amplifier are designed so that the same current flows, and are designed so that the offset voltage becomes zero (however, when the semiconductor integrated circuit is manufactured, the offset voltage is actually reduced). Varies.)

The drive circuit according to the present invention includes an offset voltage control circuit capable of arbitrarily varying the offset voltage of the operational amplifier according to the lower bits of the digital video data.

As will be described later with reference to FIG. 2, the offset voltage control circuit includes, for example, the first switch SW1,
It can be composed of the second switch SW2 and the transistor Q1.

First switch SW1 and second switch SW
2 is controlled by the lower 1 bit of the digital video data.

For example, when the digital video data is 0, the offset voltage control circuit turns on the first switch SW1 and turns off the second switch SW2, and sets a potential at which no current flows through the transistor Q1. . That is, the offset voltage control circuit sets the offset voltage to 0.
Is output. At this time, the transistor Q1 is N
In the case of a channel transistor, the gate voltage of the transistor Q1 is connected to the lower voltage.

On the other hand, when the digital video data is 1,
The offset voltage control circuit turns off the first switch SW1 and turns on the second switch SW2 to set a potential at which a current flows through the transistor Q1. At this time, a voltage (Vk + ΔV) to which the offset voltage ΔV is added is output from the operational amplifier.

As described above, the lower one of the digital video data
By controlling the offset voltage of the operational amplifier according to the bits, multi-gradation display driving of the display device can be realized.

According to a fourth aspect of the present invention, there is provided a driving circuit of a display device for displaying a plurality of gray scales in accordance with digital video data, wherein a plurality of gray scale voltages inputted from outside are provided. And a grayscale voltage generating circuit for generating a plurality of positive and negative voltages between the plurality of grayscale voltages, and the grayscale voltage generating circuit according to an upper bit of the digital video data. A first selection circuit that selects a first voltage of a positive polarity, and a second selection circuit that selects a second voltage of a negative polarity in the gradation voltage generation circuit according to the upper bits of the digital video data, A first output circuit that outputs the first voltage as it is or outputs a voltage obtained by adding an offset voltage to the first voltage, according to a lower bit of the digital video data; Depending on the output of the second voltage as it is, or a second output circuit that outputs a voltage obtained by adding an offset voltage to the second voltage, the output from the first output circuit or the second output circuit And a polarity selection circuit for selecting any one of the outputs from the first and second output circuits, the first output circuit and the second output circuit are provided with differential input stages of different conductivity types, the digital video data of There is provided a drive circuit of a display device in which ON / OFF of a current flowing through a transistor constituting the differential input stage is controlled according to a lower bit.

In this drive circuit, the first output circuit and the second output circuit are connected to the first selection circuit, the second selection circuit, and the polarity selection circuit. Each can be arranged in between.

Alternatively, the polarity selection circuit is disposed between the first selection circuit and the second selection circuit and the first output circuit and the second output circuit. be able to.

According to a seventh aspect of the present invention, there is provided a method of driving a display device for displaying a plurality of gray scales in accordance with digital video data. A first step of dividing the plurality of grayscale voltages to generate a plurality of voltages between the plurality of grayscale voltages, and a second step of selecting a first voltage among the plurality of voltages according to upper bits of the digital video data. And a third step of impedance-converting the first voltage, a fourth step of applying an offset voltage at the time of the impedance conversion according to the lower bits of the digital video data, When the value is 0, the first voltage is output, and when the digital video data is 1, a voltage obtained by adding an offset voltage to the first voltage or an offset from the first voltage. A fifth step of outputting a voltage obtained by subtracting a voltage, wherein the fifth step is performed by an operational amplifier having a differential circuit, and provides the offset voltage according to a lower bit of the digital video data. Provided is a method for driving a display device which controls on / off of a current flowing through a transistor included in an offset voltage control circuit.

Further, according to the present invention, in a driving method of a display device for displaying a plurality of gray scales in accordance with digital video data, a plurality of gray scale voltages inputted from outside are provided. A first step of generating a plurality of positive and negative voltages between the plurality of grayscale voltages, and according to upper bits of the digital video data,
A second step of selecting a first positive voltage of the plurality of voltages, and a third step of selecting a negative second voltage of the plurality of voltages according to upper bits of the digital video data And outputting the first voltage as it is, according to the lower bits of the digital video data, or
A fourth step of outputting a voltage obtained by adding an offset voltage to the first voltage, and according to the lower bits of the digital video data, outputting the second voltage as it is, or an offset voltage to the second voltage A fifth step of outputting a voltage obtained by adding the second step, and a sixth step of selecting either the output in the fourth step or the output in the fifth step, and the fourth step and The fifth step is performed through a differential input stage of a different conductivity type, and turns on a current flowing through a transistor constituting the differential input stage according to a lower bit of the digital video data. -To provide a driving method of a display device whose off is controlled.

[0038]

FIG. 1 is a block diagram of a driving circuit of a display device according to a first embodiment of the present invention. The drive circuit according to the present embodiment is an 8-bit digital input driver.

The drive circuit according to the present embodiment includes a shift register circuit 1 to which a start pulse signal SP and a clock signal CLK are input, a data buffer circuit 4 to which digital video data D _{00 to} D _XX are input, and a data buffer A data register circuit 2 having a register connected to each buffer line of the circuit 4, a data latch circuit 3 connected to each register of the data register circuit 2, a latch Shinkago STB and a polarity signal POL. Is input, a latch control circuit 5 for controlling the operation of the data latch circuit 3, a grayscale voltage generating circuit 6 for generating a plurality of positive and negative grayscale voltages, and a plurality of grayscale voltage values. First gradation voltage selection circuit 7 for selecting one gradation voltage of positive polarity
A second gradation voltage selection circuit 8 for selecting one gradation voltage of a negative polarity from a plurality of gradation voltage values, and a first output circuit 9 connected to the first gradation voltage selection circuit 7. A second output circuit 10 connected to the second gradation voltage selection circuit 8, and a polarity selection circuit 11 for selecting one of the output from the first output circuit 9 and the output from the second output circuit 10. And, it consists of.

Hereinafter, a case will be described in which the driving circuit according to the present embodiment drives a liquid crystal, in particular, a thin film transistor (TFT) liquid crystal by dot inversion.

The gradation voltage generation circuit 6 includes ten gradation power supply voltages VX0, VX1,.
8. By dividing the voltage of VX9, 128 × 2 grayscale voltages of positive polarity and negative polarity are generated.

FIG. 7 shows an example of the structure of the gradation voltage generating circuit 6. The gradation voltage generation circuit 6 has ten gradation power supply voltages V
X0-VX9 is connected to 127 resistors (+ R1, + R2, + R
3, ..., + R126, + R127 or -R127,
−R126, −R125,..., −R2, −R1), and the internal gradation voltages + V0, + V of 128 values of positive polarity
2, + V4, ..., + V250, + V252, + V2
54 and negative 128-level internal gradation voltages V0, -V
2, -V4, ..., -V250, -V252, -V2
54 and a total of 128 × 2 gray-scale voltages are generated.

The 128 gray-scale voltages of positive polarity generated by the gray-scale voltage generation circuit 6 are input to the 7-bit first gray-scale voltage selection circuit 7. The first gradation voltage selection circuit 7 selects a voltage value of one polarity value from the 128 gradation values of positive polarity according to the upper 7 bits of the digital video data D ₀₀ -D _XX .

Similarly, the negative-polarity 128-value gradation voltage generated by the gradation voltage generation circuit 6 is input to the 7-bit second gradation voltage selection circuit 8. The second gradation voltage selection circuit 8 selects one negative gradation voltage value from 128 negative gradation values in accordance with the upper 7 bits of the digital video data D ₀₀ -D _XX .

FIGS. 8 and 9 show examples of the structures of the first gradation voltage selection circuit 7 and the second gradation voltage selection circuit 8, respectively.

As shown in FIGS. 8 and 9, each of the first gradation voltage selection circuit 7 and the second gradation voltage selection circuit 8 is composed of 128 switches. in this case,
As shown in FIG. 10, the 128 switches can be made very small in chip size by being constituted by a ROM type decoder. The ROM type decoder outputs P
It is composed of channel enhancement type and depletion type transistors. Conversely, when a voltage lower than the liquid crystal common voltage is output, it is composed of N channel enhancement type and depletion type transistors.

The first output circuit 9 and the second output circuit 10
It is controlled by the least significant bit of the digital video data D ₀₀ -D _XX. That is, the first output circuit 9 and a second output circuit 10 in accordance with the least significant bit, the digital video data D ₀₀ -D _XX Accept outputs a voltage selected by the upper 7 bits of, or offset voltage to the voltage Outputs the voltage to which is added.

One example of the structure of the first output circuit 9 and the second output circuit 10 is shown in FIGS. 2 and 3, respectively.

As shown in FIG. 2, the first output circuit 9 includes a first differential transistor Q1, a second differential transistor Q2, and a third differential transistor Q3. The three differential transistor Q3 is connected in parallel to the second differential transistor Q2.

In the first output circuit 9, the first differential transistor Q1, the second differential transistor Q2 and the third differential transistor Q3 are all N-channel transistors, and the second differential transistor Q2 and the third The differential transistor Q3 has the same transistor size.

The first switch SW1 and the second switch SW2 are connected to the gate of the first differential transistor Q1, respectively. The first switch SW1 interrupts the connection between the lower potential and the first differential transistor Q1, and the second switch S1
W2 is intermittent between the output stage and the first differential transistor Q1. First differential transistor Q1 and first switch SW1
And the second switch SW2 constitute an offset control circuit 20.

When the digital video data is 0, the first switch SW1 is turned on and the second switch SW2 is turned off. In this case, since the first switch SW1 is connected to the lower potential, the current flowing through the first differential transistor Q1 becomes 0, and the offset voltage control circuit 20 outputs a voltage having an offset voltage of 0. That is, if the gray scale voltage selected by the first gray scale voltage selection circuit 7 is V,
The offset voltage control circuit 20 outputs the gradation voltage V as it is.

On the other hand, when the digital video data is 1,
The first switch SW1 is turned off, and the second switch SW2
Turns on. In this case, since the second switch SW2 is connected to the output stage, a current flows through the first differential transistor Q1, and the offset voltage control circuit 20 outputs a voltage obtained by subtracting the offset voltage ΔVp. That is, the offset voltage control circuit 20 outputs the voltage (V−ΔVp).

In this case, the offset voltage ΔVp becomes ｛(+
V126) − (+ V128)｝ / 2.

The liquid crystal display device has a relationship between transmittance and voltage as shown in FIG. 12, and this relationship is linearly approximated in a halftone region.

FIG. 4 is a diagram showing the relationship between gradation and voltage in a black or white region, and FIG. 5 is a diagram showing the relationship between gradation and voltage in an intermediate region.

According to the present embodiment, uniform gradation display can be performed in the halftone area. However, in the black or white region, the offset voltage is ΔV
Although gradation display is not uniform at about p, at least monotonic increase can be ensured.

As shown in FIG. 3, the second output circuit 10
Fourth differential transistor Q4, fifth differential transistor Q5
And a sixth differential transistor Q6. The fourth differential transistor Q4 and the sixth differential transistor Q6 are connected in parallel to the fifth differential transistor Q5.

In the second output circuit 10, the fourth differential transistor Q4, the fifth differential transistor Q5 and the sixth differential transistor Q6 are all P-channel transistors, and the fifth differential transistor Q5 and the sixth The differential transistor Q6 has the same transistor size.

The third switch SW3 and the fourth switch SW4 are connected to the gate of the fourth differential transistor Q4, respectively. The third switch SW3 interrupts the connection between the higher potential and the fourth differential transistor Q4,
W4 is intermittent between the output stage and the fourth differential transistor Q4. Fourth differential transistor Q4 and third switch SW3
And the fourth switch SW4 constitute the offset control circuit 21.

When the digital video data is 0, the third switch SW3 is turned on and the fourth switch SW4 is turned off. In this case, since the third switch SW3 is connected to the higher potential, the current flowing through the fourth differential transistor Q4 becomes 0, and the offset voltage control circuit 21 outputs a voltage having an offset voltage of 0. That is, if the gray scale voltage selected by the second gray scale voltage selection circuit 8 is V,
The offset voltage control circuit 21 outputs the gradation voltage V as it is.

On the other hand, when the digital video data is 1,
The third switch SW3 is turned off, and the fourth switch SW4
Turns on. In this case, since the fourth switch SW4 is connected to the output stage, a current flows through the fourth differential transistor Q4, and the offset voltage control circuit 21 outputs a voltage obtained by adding the offset voltage ΔVn. That is, the offset voltage control circuit 20 outputs the voltage (V + ΔVn).

In this case, the offset voltage ΔVn becomes ｛(−
V128) − (− V126)｝ / 2.

FIG. 6 shows the correspondence between digital video data and output voltages. As shown in FIG. 6, the offset voltage control circuit 20 or 21 responds to the digital video data
Generates positive and negative output voltages.

As described above, in the first embodiment, two output circuits (or operational amplifiers) 9 and 10 having differential input stages of different conductivity types are alternately applied to the display device in time series. Thus, a so-called dot inversion driving method is realized.

According to the present embodiment, the digital video data is divided into upper 7 bits and lower 1 bits, and the upper bits are of the resistor string type and the lower bits are of the offset type, so that the multi-gradation display of the display device can be realized. Making it possible.

FIG. 11 is a block diagram showing a driving circuit of a display device according to the second embodiment of the present invention.

As is apparent from a comparison between FIG. 1 and FIG. 11, which are block diagrams of the drive circuit of the display device according to the first embodiment of the present invention, the drive circuit according to the present embodiment shown in FIG. Are the same as those of the drive circuit according to the first embodiment shown in FIG.

The drive circuit according to the present embodiment is different from the drive circuit according to the first embodiment in that the first output circuit 9 and the second output circuit 10 including the operational amplifier are rail-to-rail. (Rail) type, and the point that the polarity selection circuit 11 is arranged between the first output circuit 9 and the second output circuit 10 and the gradation selection circuit 11.

According to the present embodiment, N-line inversion driving can be realized.

[0071]

According to the present invention, the following effects can be obtained.

The first effect is that the number of elements can be reduced.

The reason is as follows. For example, according to the 8-bit resistor string method, R
The number of elements in the OM decoder section is 8 × 2 × 256 = 4096. On the other hand, by using the resistor string method for the upper 7 bits and the offset method for the lower 1 bit as in the present invention, the number of elements of the ROM decoder section controlled by the upper 7 bits is 7 × 2 × 128 = 1792. Thus, the number of elements can be reduced to 4096-1792 = 2304. Since a circuit controlled by the lower 1 bit can be composed of at least 30 elements, a maximum of 2304 is obtained by subtracting the increase in the number of elements in this circuit.
-30 = 2274 elements can be reduced.

As described above, according to the present invention, the number of elements can be greatly reduced, and the chip size can be reduced.

The second effect is that the test cost can be reduced.

Since it is necessary to confirm the operation of 256 ROM decoders with 8 bits, it is necessary to perform 256 function tests. On the other hand, if the upper 7 bits are of the resistor string type and the lower 1 bit is of the offset type as in the present invention, the number of ROM decoders requiring operation confirmation is 128. Is 1
28 times. Confirmation of the offset method of the lower 1 bit can be completed by two function tests.
2 = 130 function tests may be performed.

As described above, according to the present invention, the number of function tests can be reduced by 256-130 = 126 times,
As a result, the test cost can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a drive circuit of a display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a first output circuit which is a component of the drive circuit shown in FIG.

FIG. 3 is a block diagram of a second output circuit which is a component of the drive circuit shown in FIG.

FIG. 4 is a diagram illustrating the relationship between 128 gray levels and 256 gray levels near 0 gray level.

FIG. 5 is a diagram showing the relationship between 128 gradations and 256 gradations near a halftone.

FIG. 6 is a diagram showing the relationship between digital video data and output voltage.

FIG. 7 is a circuit diagram of a grayscale voltage generation circuit which is a component of the drive circuit shown in FIG.

8 is a circuit diagram of a first gradation voltage selection circuit which is a component of the drive circuit shown in FIG.

FIG. 9 is a circuit diagram of a second gradation voltage selection circuit which is a component of the drive circuit shown in FIG.

FIG. 10 is a circuit diagram showing a structure of a gray scale voltage selection circuit constituted by a ROM decoder.

FIG. 11 is a block diagram of a drive circuit of a display device according to a second embodiment of the present invention.

FIG. 12 is a graph showing a relationship between transmittance and voltage in a liquid crystal display device.

FIG. 13 is a block diagram showing the structure of a conventional 6-bit digital drive circuit.

[Description of Signs] 1 shift register circuit 2 data register circuit 3 data latch circuit (including level shift circuit) 4 data buffer circuit 5 latch control circuit 6 gradation voltage generation circuit 7 first gradation voltage selection circuit 8 second gradation Voltage selection circuit 9 First output circuit 10 Second output circuit 11 Polarity selection circuit 20, 21 Offset voltage control circuit 30 Shift register circuit 31 Data register circuit 32 Data latch circuit 33 ROM decoder circuit 34 Amplifier SP Start pulse signal CLK Clock signal D _{00 to} Dxx Digital video data STB Latch signal POL Polarity signal VX0-VX9 Gray scale power supply voltage + V0, + V2, + V4,..., + V254 Internal gray scale voltage (positive polarity) -V0, -V2,- V4,..., -V254 internal gradation voltage ( Polar) + R1, ···, + R127 resistor -R1, ···, -R127 resistor Q1, Q2, Q3, Q4, Q5, Q6 transistor ΔV offset voltage ΔVP positive polarity side offset voltage ΔVN negative side offset voltage

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133

Claims (8)

(57) [Claims] 1. A driving circuit of a display device for displaying a plurality of gray scales in accordance with digital video data, wherein a plurality of gray scale voltages input from outside are divided, and a plurality of gray scale voltages are divided between the plurality of gray scale voltages. A gray-scale voltage generating circuit for generating a voltage, a first selecting circuit for selecting a first voltage in the gray-scale voltage generating circuit according to an upper bit of the digital video data, and impedance conversion of the first voltage And an offset voltage control circuit that applies an offset voltage to the operational amplifier in accordance with the lower bits of the digital video data. The operational amplifier includes a differential circuit, and the differential circuit Accordingly, the offset voltage control circuit outputs the first voltage when the digital video data is 0, and outputs the first voltage when the digital video data is 1. And outputting a voltage obtained by adding an offset voltage to the first voltage or a voltage obtained by subtracting an offset voltage from the first voltage , wherein the offset voltage control circuit includes a transistor and the transistor.
The first switch and the
And when the digital video data is at a low level,
The first switch is on and the second switch is off.
When no current flows through the transistor and the digital video data is at a high level,
The first switch is off and the second switch is on.
A driving circuit for a display device , wherein a current flows through the transistor . 2. The offset voltage control circuit changes an offset voltage value by changing a value of a current flowing through one of the differential input transistors constituting the differential circuit. The drive circuit for a display device according to claim 1. 3. The driving circuit according to claim 1, wherein the operational amplifier is a voltage follower type operational amplifier. 4. A driving circuit of a display device for displaying a plurality of gray scales according to digital video data, wherein a plurality of gray scale voltages inputted from outside are divided, and a positive polarity is applied between the plurality of gray scale voltages. And a grayscale voltage generation circuit that generates a plurality of voltages of negative polarity, and a first selection circuit that selects a first voltage of positive polarity in the grayscale voltage generation circuit according to an upper bit of the digital video data. A second selection circuit that selects a second negative voltage in the grayscale voltage generation circuit according to an upper bit of the digital video data; and the first voltage according to a lower bit of the digital video data Or a first output circuit that outputs a voltage obtained by adding an offset voltage to the first voltage, and whether to output the second voltage as it is in accordance with lower bits of the digital video data Alternatively, a second output circuit that outputs a voltage obtained by adding an offset voltage to the second voltage, and a polarity selection circuit that selects one of an output from the first output circuit and an output from the second output circuit , wherein the first output circuit and the second output circuit includes a differential input stage of a different conductivity type to each other, depending on the lower bits of the digital video data, the difference
Of the current flowing through the transistor constituting the dynamic input stage
A driving circuit of a display device whose off is controlled . 5. A method according to claim wherein the first output circuit and the second output circuit is characterized in that it is arranged between said first selection circuit and the second selection circuit and the polarity selection circuit 4 4. A driving circuit for a display device according to claim 1. 6. The circuit according to claim 1, wherein the polarity selection circuit is disposed between the first selection circuit and the second selection circuit and the first output circuit and the second output circuit.
5. The drive circuit of the display device according to 4 . 7. A method of driving a display device for displaying a plurality of gray scales in accordance with digital video data, comprising: dividing a plurality of gray scale voltages inputted from outside; A first step of generating a voltage, a second step of selecting a first voltage among the plurality of voltages according to an upper bit of the digital video data, and a third step of impedance-converting the first voltage And a fourth step of providing an offset voltage at the time of the impedance conversion in accordance with the lower bits of the digital video data, and outputting the first voltage when the digital video data is 0, When the digital video data is 1, a fifth step of outputting a voltage obtained by adding an offset voltage to the first voltage or a voltage obtained by subtracting the offset voltage from the first voltage, The fifth step is performed by an operational amplifier having a differential circuit, and the fifth step is performed according to a lower bit of the digital video data.
Configure an offset voltage control circuit that gives the offset voltage.
A method for driving a display device, which controls on / off of a current flowing through a transistor . 8. A method of driving a display device for displaying a plurality of gray scales in accordance with digital video data, comprising: dividing a plurality of gray scale voltages input from outside; And a first step of generating a plurality of voltages of negative polarity, and a second step of selecting a first voltage of positive polarity among the plurality of voltages according to upper bits of the digital video data, A third step of selecting a negative second voltage among the plurality of voltages according to upper bits of the video data; and outputting the first voltage as it is according to lower bits of the digital video data. Or a fourth step of outputting a voltage obtained by adding an offset voltage to the first voltage, and according to the lower bits of the digital video data, outputting the second voltage as it is, or the second voltage A fifth step of outputting a voltage to which an offset voltage is added, and a sixth step of selecting either the output in the fourth step or the output in the fifth step, the fourth step process and the fifth process all SANYO performed via the differential input stage of a different conductivity type to each other, depending on the lower bits of the digital video data, the difference
Of the current flowing through the transistor constituting the dynamic input stage
A method for driving a display device whose off is controlled .