JP3345939B2 - Control Method of Nonlinear Processor in Echo Canceller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling a nonlinear processor used in an echo canceller.
In particular, the present invention relates to a control method for reducing noise at the start of operation of a nonlinear processor.

[0002] The most common telephone lines have two subscriber lines.
The line is composed of four lines. A hybrid transformer is inserted between the two-wire line and the four-wire line,
The voice is transmitted from the subscriber line to the transmission-side relay line, and the voice signal of the reception-side relay line is transmitted only to the subscriber line.
However, due to the imbalance of the characteristics of the hybrid transformer itself and the impedance mismatch between the hybrid transformer and the line, the sound signal of the receiving-side relay line wraps around to the transmitting-side relay line. The phenomenon that an audio signal is called an echo) occurs. The echo passes through the transmission line, the far-end hybrid transformer, and the far-end subscriber line to reach the far-end telephone handset. Again, this is the voice of the far end talker,
The far end talker is talking while listening to his or her own voice delayed by a time equal to the delay of one round trip of the trunk line. In Japan, this delay time is on the order of tens of milliseconds and does not cause any discomfort to the caller, but in the case of international calls, this delay time can reach hundreds of milliseconds, and the caller is extremely Placed in an environment where speaking is difficult.

In a teleconferencing system using a communication line, the space of the conference room corresponds to a hybrid transformer and two subscriber lines. In this case, the far-end sound comes out of the near-end speaker, enters the near-end microphone by the reverberation of the room, and is transmitted to the far-end side. Enter the microphone at the end. When the loop gain exceeds 1, a so-called sound (howling) occurs. If howling occurs, it will not be possible to reduce the level of difficulty in speaking, and it will not be possible to continue the remote conference.

In order to solve such a problem, an echo canceller that generates a pseudo echo and subtracts it from the echo from the receiving side to the transmitting side is used. echo·
In addition to the above, cancellers are also used in two-way repeaters for two-wire relay, mobile phone systems, etc.
Applications are expanding.

The non-linear processor suppresses non-subtractable components when the echo canceller is used, and further improves the speech characteristics when the echo canceller is used.

[0006]

2. Description of the Related Art FIG. 9 shows an echo canceller.
FIG. 9 is a diagram illustrating the principle of a conventional nonlinear processor.

In FIG. 9, 11 is a control circuit, 12 is a center clipper, and 11 and 12 constitute a conventional non-linear processor. 13 is a pseudo echo calculation circuit, 14 is a subtraction circuit, and 15 is a hybrid transformer. The echo canceller is constituted by 11 to 15.

The pseudo echo calculation circuit 13 receives the received signal, estimates the transfer characteristic of the echo path, generates a pseudo echo, and subtracts the pseudo echo from the echo in the subtraction circuit 14. The signal is taken into the pseudo echo calculation circuit again, and the pseudo echo is continuously calculated so as to reduce the residual echo output from the subtraction circuit.

However, an error due to noise or an accuracy limit of pseudo echo calculation remains as a residual echo. A non-linear processor is used to remove such residual echoes and improve speech quality. The control circuit 11 determines that the signal power on the receiving side is equal to or higher than a first predetermined level (about the lowest level during a call) and that the level input to the subtraction circuit is a second predetermined level (the first predetermined level). When the signal is equal to or less than the level at which the signal wraps around as an echo), the center clipper 12 is operated to suppress the residual echo.

FIG. 10 shows the transmission characteristics of the center clipper. As shown in FIG. 10, the center clipper operates as a circuit having a gain of 1 for a signal of a predetermined level or higher, and operates as a circuit of a gain of 0 for a signal having a level lower than the predetermined level.
With this transfer characteristic, the speech signal is passed as it is, and the residual echo is suppressed.

FIG. 11 is a diagram showing the relationship between the input signal level and the output signal level, showing the characteristics of the center clipper. FIG. 11 illustrates a change in the output level of the center clipper, assuming that a signal whose level decreases linearly with time (indicated by a broken line) is input to the center clipper. When the input signal drops to the second predetermined level, the center clipper operates and the gain changes suddenly from 1 to 0. Therefore, the output level of the center clipper is as shown by the thick solid line. In addition to this, the characteristics of the line, the handset, and the ear are added to the human auditory nerve. Since the frequency characteristic from the line to the ear increases in low frequency and high frequency, and has a band-pass characteristic in which the loss is small in the intermediate band, it is felt as smoothed as shown by the thin solid line in FIG. Even so, the volume changes for a short time, so it can be clearly felt by the ears. Therefore, the far end talker suddenly hears the background noise being interrupted, giving a sense of discomfort.

[0012]

SUMMARY OF THE INVENTION The present invention addresses such a problem and alleviates a sudden change in level when a non-linear processor operates, thereby reducing the sense of discomfort experienced by a far-end talker. An object of the present invention is to provide a control method of a nonlinear processor.

[0013]

FIG. 1 is a block diagram representation of an entire echo canceller for explaining an embodiment of the present invention.

In FIG. 1, 1a and 1b are power calculation circuits, 2 is an operation determination circuit, 3 is a counter, 4 is a suppression amount instruction circuit, 5 is a memory, 6 is a multiplication circuit, and 1a, 1b and 2 to 6 Configure a non-linear processor. 7 is a pseudo echo generation circuit, 8 is a subtraction circuit, and 9 is a hybrid transformer. Then, echo 1a, 1b and 2-9
Configure the canceller.

A feature of the present invention is that when the operation determination circuit 2 detects the operating condition of the non-linear processor, the subtraction circuit 8
Is multiplied by a constant C1 smaller than ₁ to output a multiplied signal, and the above operation is continued at a constant period while the operation determination circuit detects the operation condition.

[0016]

[Action] The operating condition of the nonlinear processor is detected.
Output signal of the subtraction circuit at the time (this amplitude is assumed to be 1)
And a constant C smaller than 1 at a constant period₁Is multiplied and output
Is done. Therefore, the amplitude after one cycle is C₁, After two cycles
Width is C₁ ^Two, After n cycles ₁ ⁿOutput level
It will be cheap. Now, suppose C₁= 0.5, one cycle later
Is 0.5, 0.25 after two cycles, 0.125 after three cycles
Amplitude. That is, the operation of the nonlinear processor
Sudden level changes at the start of the work are mitigated, and
To my ears, it feels like this smooth waveform
When the nonlinear processor starts operation
But the caller is no longer harsh.

[0017]

FIG. 2 is a flowchart of an embodiment of the present invention. Hereinafter, the operation of the embodiment of the present invention will be described in detail with reference to FIG.

(A) The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer. (I) It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. If this condition is not satisfied (No), the procedure returns to (A).

(C) When the above condition is satisfied (Ye
In s), the counter is brought into a countable state. (E) The input level of the multiplier is stored, and the count of the counter is advanced.

(3) The constant C ₁ for determining the amount of suppression is read out from the memory and given to the multiplier, and the stored input level of the multiplier is multiplied by C ₁ . (F) Output and store the multiplication result.

(G) The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer. (C) It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. If this condition is not satisfied (No), the procedure returns to (A) (the operation of the nonlinear processor is stopped). If the above condition is still satisfied (Yes), the process returns to (E) and the operation of the nonlinear processor is continued.

FIG. 3 is a diagram for explaining the characteristics of the nonlinear processor of the present invention. The vertical axis in FIG.
The horizontal axis is time. Then, as shown by a broken line, an input signal that decreases linearly with time is assumed. If the input signal becomes equal to the second predetermined level (then, if the power on the receiving side of the hybrid transformer is equal to or higher than the first predetermined level), the operation determination circuit detects this and the non-linear processor operates. Start. This time is set to t _0, and the second predetermined level at this time is set to 1 temporarily. Assuming that the period of the clock signal of the counter is τ, the time (t ₀ +
In τ), the count value of the counter advances by one, and the multiplier multiplies the input level by a constant C ₁ . Therefore, the output amplitude of the time is C _1, stores the amplitude multiplication circuit. Similarly the time (t ₀ + 2τ) output amplitude is the C ₁ ^2, and the when the have passed nτ become C ₁ ^n, slide into asymptotically to zero. The output level becomes a staircase waveform at every time τ, but the change in the output level is smoothed as shown by the thin solid line in FIG.
_{Since the} level is fixed at the time t ₀ between ₀ and the time (t ₀ + τ), the differential coefficient at the time t ₀ is small. Therefore, according to the nonlinear processor of the present invention, the level change at the start of the operation Is hard to feel. this is,
In the case of the center clipper, it is a significant improvement in call quality as compared to the case where the effect is still noticeable even when the band limiting effect is added.

FIG. 4 is a block diagram illustrating a second embodiment of the present invention. In FIG. 4, 1
a, 1b, 1c are power calculation circuits, 2 is an operation determination circuit, 3
Is a counter, 4a is a suppression amount instruction circuit, 5 is a memory, 6 is a multiplication circuit, and 1a, 1b, 1c and 2 to 6 constitute a non-linear processor. 7 is a pseudo echo generation circuit, 8
Is a subtraction circuit, and 9 is a hybrid transformer. An echo canceller is constituted by 1a, 1b, 1c and 2 to 9.

The feature of the second embodiment is that the output of the power calculator 1c is taken into the suppression amount indicator 4a, and when the output level of the multiplying circuit 6 drops below the third predetermined level, the suppression amount indicator is activated. the constants to be imported from the memory 17, instead of the constant C ₂ representing a third predetermined level, and thereafter lies in fixing the output level of the multiplying circuit at a constant level C _2. In the above-described embodiment, while the operation determiner detects the operating condition, the constant C ₁ is multiplied infinitely. However, the minimum audible level is determined for the human ear, Since noise is present in the device, there is no practical significance in infinitely multiplying to an infinitely low level. That is, in the second embodiment, when the signal level becomes lower than the minimum audible level, the multiplication function is stopped and the level is maintained at a constant level. This also provides an advantage that power consumption can be reduced by stopping the operation, particularly when the nonlinear processor is formed of CMOS.

FIG. 5 is a flowchart for explaining the operation of the second embodiment of the present invention. Hereinafter, the operation of the second embodiment will be described with reference to FIG. I. The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer.

B. It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. If this condition is not satisfied (No), the process returns to step a.

C. When the above conditions are satisfied (Yes)
, The counter is brought into a countable state. D. The input level of the multiplier is stored, and the count of the counter is advanced.

E. Constant C ₁ to determine the amount of suppression applied to the multiplier are read from the memory, multiplying the C ₁ to the input level of multiplier stored. F. The level of the multiplication result is output and stored.

G. It is determined whether or not the power of the input signal of the multiplier circuit indicated by the power calculator 1c is equal to or lower than a third predetermined level. If not below the third predetermined level (No), h. The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer.

Re. It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. If this condition is not satisfied (No), the process returns to (a), and if it is satisfied (Yes), the process returns to (d).

If it is determined in step (f) that the level is equal to or lower than the third predetermined level (Yes), nu. It reads the constant C ₂ different from the memory, to fix the level of multiplication circuit outputs a level corresponding to C _2.

Le. A fixed level is output from the multiplication circuit.ヲ. The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer.

W. It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. If this condition is not satisfied (No), the process returns to a; if it is satisfied (Yes), the process returns to null.

FIG. 6 is a block diagram illustrating a third embodiment of the present invention. In FIG. 6, 1
a, 1b, 1d are power calculation circuits, 2 is an operation determination circuit, 3
Is a counter, 4b is a suppression amount instruction circuit, 5 is a memory, 6 is a multiplication circuit, and 1a, 1b, 1d and 2 to 6 constitute a non-linear processor. 7 is a pseudo echo generation circuit, 8
Is a subtraction circuit, and 9 is a hybrid transformer. Then, 1a, 1b, 1d and 2 to 9 constitute an echo canceller.

The feature of the third embodiment of the present invention is that the input level and the output level of the subtraction circuit are determined by the power calculation circuits 1a and 1d.
And a third constant C for specifying the amount of suppression in the output level of the subtraction circuit in the multiplication circuit.
_The point is to multiply 3 by a value obtained by multiplying (input power) ÷ (output power) at that time. That is, when the residual echo is large, the signal is attenuated quickly, and when the residual echo is small, the signal is attenuated slowly. Therefore, it has the advantage that the convergence time is reduced,
Further, the same effects as those of the above two embodiments are provided.

FIG. 7 is a flowchart for explaining the operation of the third embodiment of the present invention. Hereinafter, the operation of the third embodiment will be described in detail with reference to FIG. A. The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer.

B. It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. If this condition is not satisfied (No), the process returns to step a.

C. When the above conditions are satisfied (Yes)
, The counter is brought into a countable state. D. The input level of the multiplier is stored, and the count of the counter is advanced.

E. The ratio between the input power of the subtraction circuit and the input power of the multiplication circuit is calculated. F. Subjected to levels which stores the input and output ratio and a constant C _3. G. FIG. The multiplication result is output and stored.

H. The power calculator calculates the input power of the subtraction circuit and the power of the receiving side of the hybrid transformer. I. It is determined whether the power on the receiving side of the hybrid transformer is higher than a first predetermined level and whether the input power of the subtraction circuit is lower than a second predetermined level. When this condition is not satisfied (No), the process returns to A, and when this condition is satisfied (Yes), the process returns to D.

FIG. 8 is a diagram for explaining a fourth embodiment of the present invention. 8, 1a, 1b, 1c, and 1d are power calculation circuits, 2 is an operation determination circuit, 3 is a counter, 4b is a suppression amount instruction circuit, 5 is a memory, 6 is a multiplication circuit, and 1a,
1b, 1c, 1d and 2 to 6 constitute a non-linear processor. 7 is a pseudo echo generation circuit, 8 is a subtraction circuit,
9 is a hybrid transformer. And 1a, 1
b, 1d and 2 to 9 constitute an echo canceller.

In the fourth embodiment, when the output level of the multiplying circuit falls below the third predetermined level in the third embodiment, similar to the second embodiment, the multiplying circuit is thereafter turned off. Output a certain level.

Although the functions of the present invention can be realized by hardware, program control, or a compromise thereof, at present, the most common method is to use a processor dedicated to signal processing. The present invention
It can be applied to any of these.

Although not specifically mentioned in the above description,
In the present invention, the form of the transmission signal and the reception signal, that is, whether the signal is an analog signal or converted to a digital signal is not limited.

[0045]

As described above in detail, according to the present invention, when the nonlinear processor starts operation, it can be heard by the far-end talker and suppresses a sudden change in the volume level that gives the far-end talker a sense of discomfort. It becomes possible to do. This leads to an improvement in the subjective quality of the telephone by the line using the echo canceller, and this effect is great.

[Brief description of the drawings]

FIG. 1 illustrates an embodiment of the present invention.

FIG. 2 is a flowchart of an embodiment of the present invention.

FIG. 3 shows characteristics of the nonlinear processor of the present invention.

FIG. 4 is a diagram illustrating a second embodiment of the present invention.

FIG. 5 is a flowchart of a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a third embodiment of the present invention.

FIG. 7 is a flowchart of a third embodiment of the present invention.

FIG. 8 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 9 is a view for explaining the principle of a conventional nonlinear processor.

FIG. 10 shows transmission characteristics of a center clipper.

FIG. 11 is a diagram illustrating characteristics of a center clipper.

[Explanation of symbols]

 1a, 1b Power calculation circuit 2 Operation determination circuit 3 Counter 4 Suppression amount instruction circuit 5 Memory 6 Multiplication circuit 7 Pseudo echo generation circuit 8 Subtraction circuit 9 Hybrid transformer

Continuation of front page (56) References JP-A-5-22195 (JP, A) JP-A-60-260235 (JP, A) JP-A-60-76823 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H04B 3/20

Claims (4)

(57) [Claims] 1. A method for controlling a non-linear processor in an echo canceller, wherein a counter (3) is counted when an operation start condition of the non-linear processor is detected (2) according to a calculation result of a power calculating circuit (1a, 1b). Each time the counter advances by one, the first constant read from the memory (5) is sent to the multiplier circuit (4), and the level stored in the multiplier circuit is multiplied by the first constant. And outputting the level of the multiplication result from the multiplication circuit and storing the multiplication result in the multiplication circuit. 2. The method according to claim 1, wherein when the output level of the multiplication circuit reaches a predetermined level, the level output from the multiplication circuit is fixed to the predetermined level and output. A method for controlling a non-linear processor. 3. The method for controlling a non-linear processor according to claim 1, wherein a ratio between an input level and an output level of the subtraction circuit (9) is calculated, and a product of the level ratio and a third constant is multiplied by the multiplication circuit. A method of controlling a non-linear processor, comprising multiplying a stored level, outputting a level of a multiplication result, and storing the multiplication result in a multiplication circuit. 4. A method according to claim 3, wherein when the output level of the multiplication circuit reaches a predetermined level, the level output from the multiplication circuit is fixed to the predetermined level and output. A method for controlling a non-linear processor.