JP3344078B2 - Insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor such as a MOS field effect transistor (MOSFET), and more particularly to a buried channel type field effect in which a source / drain region and a channel region have the same conductivity type. The present invention relates to a device structure suitable for use in a transistor.

[0002]

As is well known, such a buried channel type MOSFET is a surface channel type MOSFET in which a channel region has a conductivity type opposite to that of a source / drain region.
, The electric field strength near the drain is lower, and the device structure has a strong resistance to the hot carrier effect.

Further, the buried channel type MOSFET generally has a feature that the mobility is less deteriorated and the internal noise is smaller than the surface channel type MOSFET.

FIG. 5 shows such a buried channel type MO.
1 shows a basic device structure as an SFET. FIG. 5
As shown in FIG. 1, a buried channel type MOSFET is basically formed on an n-type silicon (Si)
+ Type source / drain region 2 and p− type channel region 3
Are formed, and an n + type gate electrode 5 is provided via a gate oxide film 4 on the surface of the well 1. The film 6 covering the gate electrode 5 is a sidewall oxide film.

In the buried channel type MOSFET, the source / drain region 2 and the channel region 3 are of the same conductivity type (p-type in the example of FIG. 5). Less and
Device characteristics with low internal noise are realized.

[0006]

As described above, the buried channel type MOSFET has a device characteristic with a small deterioration of mobility and a small internal noise. And the cause of internal noise.

[0007] The causes of the mobility degradation are mainly caused by an increase in the electric field strength in the vertical direction applied to the channel region, and an increase in the gate oxide film /
This is considered to be due to carrier scattering due to lattice defects near the silicon (Si) well interface.

On the other hand, it is considered that the cause of the internal noise is mainly due to random capture and emission of carriers due to lattice defects near the gate oxide film / silicon (Si) well interface.

For this reason, a buried channel type MOSFE
The characteristic that the mobility of T is small and the internal noise is small is considered to be due to the following reasons. (1) In the buried channel type MOSFET, the drain current spreads and flows from the gate oxide film / silicon (Si) well interface into the channel region due to the structure in which the source / drain region and the channel region have the same conductivity type. . (2) For this reason, the influence of lattice defects near the gate oxide film / silicon (Si) well interface, which is a common cause of the mobility degradation and internal noise, can be reduced.
As a result, the deterioration of the mobility is small and the internal noise is small.

Therefore, the buried channel type MOSF
In order to further reduce the mobility degradation and further reduce the internal noise in order to further improve the performance of the ET, the path of the drain current is further distant from the gate oxide film / silicon (Si) well interface. It is clear that this should be done.

The buried channel type M shown in FIG.
In the OSFET, in order to keep the drain current path away from the interface, the junction depth of the p − type channel region 3 with the n type silicon (Si) well 1 may be further increased.

Normally, the junction depth of the p-type channel region 3 can be increased by increasing the ion implantation energy of boron (B) when forming the p-type channel region 3.

FIG. 7 shows the buried channel type MOSF.
Silicon (Si) from the gate oxide film / silicon (Si) well interface of two types of p-type channel regions formed by changing the ion implantation energy of boron (B) in ET
A simulation result is shown for the transition of the absolute value of the total impurity concentration value with respect to the distance in the depth direction of the well.

Here, the absolute value of the total impurity concentration is expressed as | ND-NA |, where the n-type impurity concentration is ND and the p-type impurity concentration is NA.

Further, the simulation is as follows: 20 n on an n-type silicon (Si) well having an impurity concentration of 1.0 × 10 16 / cm 3 (“＾” represents a power)
m oxide film is formed, and boron (B) is ion-implanted from above. After the ion implantation, the oxide film is peeled off, and a new oxide film of 10 nm is formed as a gate oxide film. Thereafter, a heat treatment at 950 ° C. is performed for 20 minutes. It was performed under such conditions.

In the above ion implantation, two types of implantation energy are used: (a) 30 KeV and (b) 80 KeV, and the implantation amount is 1.4 × 10 {12 / cm}.
2 (“＾” represents a power).

The threshold values Vth of the two buried channel type MOSFETs thus obtained are both substantially -0.6 V. In FIG. 7, the solid line represents the above p (p) with the ion implantation energy of 30 KeV.
The transition of the absolute value of the total impurity concentration value in the MOSFET having the negative type channel region is shown, and the broken line is the same as that in the above (b) when the ion implantation energy is 80 KeV.
6 shows the transition of the absolute value of the total impurity concentration value in a MOSFET having a negative channel region.

As is apparent from FIG. 7, as the implantation energy of boron (B) is increased, the junction depth of the p-type channel region formed with the silicon (Si) well is increased.

FIG. 8 shows the two buried channel MOSFETs having -2.
When a voltage of 0 V is applied (gate voltage Vg = −2.0
V) shows the simulation result of the change in hole concentration with respect to the distance from the gate oxide film / silicon (Si) well interface to the depth direction of the silicon (Si) well in each p− type channel region. It is.

According to FIG. 8, it is better to form the p-type channel region by increasing the ion implantation energy as described in (b) above, that is, the junction of the p-type channel region with the silicon (Si) well. It can be seen that as the depth increases, the hole concentration also increases in the depth direction of the n-type silicon (Si) well. That is, in this case, the drain current is further away from the gate oxide film / silicon (Si) well interface.

As described above, the buried channel type MOS
In order to further improve the performance of FET, boron (B)
It is effective to increase the ion implantation energy to increase the junction depth of the p − -type channel region with the silicon (Si) well.

However, for example, in the conventional buried channel type MOSFET shown in FIG. 5, when the junction depth of the p− type channel region 3 to the silicon (Si) well 1 is increased, the following two problems occur. It is a new occurrence.

One is that when the junction depth of the p − -type channel region 3 is increased, the n-type impurity concentration of the n-type silicon (Si) well 1 in the vicinity of the lower portion of the source / drain region 2 is reduced. Such a phenomenon occurs.

The punch-through means that the depletion layer at the drain end and the depletion layer at the source end are formed even at a small drain-source voltage because the n-type impurity concentration near the lower part of the source / drain region 2 is reduced. As a result, the internal current that cannot be controlled by the gate voltage
It is a phenomenon that flows between sources.

If the drain-source voltage at which the punch-through occurs is lower than the power supply voltage for driving the MOSFET, the MOSFET cannot be used. The other is, as is clear from FIG. 7, that the ion implantation energy is increased and the junction depth of the p − -type channel region 3 with the n-type silicon (Si) well 1 is increased as in (b) above. If the depth is increased, the surface concentration of the p-type channel region 3 necessarily decreases.

In general, the concentration in the vicinity of the surface of a silicon (Si) well does not always become an accurate value due to a complicated manufacturing process of a MOSFET, but varies greatly.

Therefore, in the process of manufacturing a MOSFET, the surface concentration is usually determined by ion implantation when forming the channel region. However, as shown in FIG. 7, when the surface concentration of the p− type channel region 3 in the buried channel type MOSFET is reduced in this manner, the surface concentration of the MOSFET is also reduced to the level of the n type silicon (Si) well 1. Inevitably, it is affected by the above-mentioned large uneven surface density.

As a result, the threshold value Vth of the MOSFET itself varies, and as a result, the yield is remarkably reduced as a product. As described above, for example, when forming the p − -type channel region, increasing the ion implantation energy of boron (B) to increase the junction depth increases the performance of the buried channel type MOSFET. Above is certainly promising. However, as a matter of fact, the above two problems are significant, and as a result, such a method has not been adopted.

In recent years, for example, Japanese Patent Publication No. 4-82064
As disclosed in Japanese Unexamined Patent Application Publication No. 2000-214, in order to miniaturize such a buried channel type MOSFET to a submicron region, a high concentration impurity which suppresses the potential growth due to drain voltage is provided in a part immediately below the channel region and on the side of the source / drain region. In some cases, a layer is formed. FIG.
The device structure of the MOSFET is shown for reference.

That is, this buried channel type MOSF
As shown in FIG. 6, the ET is different from the MOSFET structure shown in FIG. 5 in that the channel region 3 is located immediately below the channel region 3 and on the side of the source / drain region 2.
Is selectively covered, and the structure further includes an n-type high-concentration impurity layer 7.

According to such a device structure, even if the junction depth of the p − type channel region 3 to the n type silicon (Si) well 1 is increased, the source / drain region 2
The decrease in the concentration of the n-type impurity in the vicinity of the lower portion is suitably suppressed. That is, as long as the high-concentration impurity layer 7 is appropriately designed, the above-described phenomenon such as punch-through can be favorably avoided.

However, even in the device structure, if the junction depth of the p-type channel region 3 is increased in order to further reduce the above-described mobility degradation and further reduce the internal noise, the same channel region can be obtained. The surface concentration of No. 3 is inevitable. That is, the buried channel type MOSFE
In order to further improve the performance as T, as described above, the threshold value Vth of the MOSFET itself varies, and as a result, the yield as a product decreases.

In the above description, for convenience, a p-channel MOSFET
Has been described as an example.
T or MOS (metal-oxide-semiconductor)
Not only the structure but also the insulated gate field-effect transistor adopting a so-called MIS (metal-insulator-semiconductor) structure, since it is configured as a buried channel type, such a situation is generally common. ing.

The present invention has been made in view of the above-mentioned circumstances, and even if the junction depth of the channel region is increased, the occurrence of punch-through and the variation in the threshold voltage can be suitably suppressed, and the buried channel type It is an object of the present invention to provide an insulated gate type field effect transistor capable of further improving the performance as a device.

[0035]

In order to achieve the above object, according to the first aspect of the present invention, in a buried channel type insulated gate field effect transistor having the above-mentioned device structure, the channel region is formed by the thickness of a semiconductor substrate. A high-concentration impurity layer of the same conductivity type as the semiconductor substrate that selectively covers the channel region is provided on the side of the source / drain region immediately below the channel region. It has a structure to be equipped.

Further, the channel region is formed such that a surface impurity concentration forming an interface with the gate insulating film is equal to or higher than an impurity concentration of the semiconductor substrate in total impurity concentration.
The impurity concentration is set.

According to the second aspect of the present invention, under the conditions of the first aspect of the present invention, the channel region is formed between the first region provided on the interface side with the gate insulating film and the first region. 1 is disposed at a position deeper than the
And a second region having a higher impurity concentration than the region.

According to the third aspect of the present invention, in each of these device structures, the junction depth between the high-concentration impurity layer and the semiconductor substrate is larger than the junction depth between the channel region and the same semiconductor substrate. It should be placed in a deeper position.

[0039]

In the device structure according to the first aspect of the present invention,
The layer disposed on the surface side of the channel region formed as a laminated structure of at least two layers, that is, the interface side with the gate insulating film acts to prevent a decrease in surface concentration as the channel region.

Further, the layer disposed closer to the inside of the semiconductor substrate in the channel region acts to increase the junction depth of the channel region to the semiconductor substrate. Therefore, the above-described contradictory phenomena, such as a decrease in the surface concentration of the channel region when the junction depth of the channel region is increased, are favorably eliminated by such a channel region structure formed as a laminated structure of at least two layers. become.

On the other hand, even if the junction depth with respect to the semiconductor substrate is set to be deeper through the layer provided in the semiconductor substrate in the direction closer to the inside of the semiconductor substrate, the presence of the high-concentration impurity layer lowers the source / drain region. A decrease in the substrate impurity concentration in the vicinity is suitably suppressed. For this reason, the occurrence of the above-described punch-through can be avoided well.

As described above, according to the device structure of the first aspect of the present invention, the junction depth of the channel region with the semiconductor substrate can be increased without lowering the concentration on the surface of the channel region or causing punch-through. Will be able to As a result, the path of the drain current described above also moves away from the interface with the gate oxide film, and as a result, the deterioration of the mobility is further suppressed and the internal noise is further reduced. That is, as the buried channel type insulated gate field effect transistor, its stability is sufficiently ensured and further higher performance can be achieved.

The laminated structure of the channel region composed of at least two layers has, for example, two layers having different implantation energies.
It can be realized by ion implantation more than once. Further, in the device structure of the present invention of such claim 1, - wherein the channel region, so that the surface impurity concentration to form an interface between the gate insulating film is equal to or higher than the impurity concentration of said semiconductor substrate at a total impurity concentration The impurity concentration is set. If this is the case, the surface concentration of the channel region can be maintained sufficiently high so as not to be affected by the greatly varied surface concentration of the semiconductor substrate.

Therefore, the threshold value Vth of the field effect transistor does not vary, and the yield does not decrease. Further, in the device structure according to the first aspect of the present invention, as in the second aspect of the present invention, it is preferable that: the channel region includes a first region provided on an interface side with a gate insulating film; And a second region which is disposed at a position deeper than the first region and has a higher impurity concentration than the first region. If this is the case, it is possible to more efficiently increase the junction depth of the channel region with the semiconductor substrate while suitably avoiding the variation in the threshold value Vth. That is, the above-described region having a high hole concentration in the channel region spreads more inside the semiconductor substrate, and the path of the drain current also more effectively moves away from the interface with the gate oxide film. .

In each of these device structures,
According to the third aspect of the present invention, the high-concentration impurity layer is disposed at a position where the junction depth with the semiconductor substrate is deeper than the junction depth with the semiconductor substrate in the channel region. In this case, the decrease in the impurity concentration of the semiconductor substrate in the vicinity of the lower portion of the source / drain regions described above is reliably suppressed through the high concentration impurity layer. That is, the occurrence of the punch-through described above is more reliably prevented.

[0046]

FIG. 1 shows a device structure of an embodiment of an insulated gate field effect transistor according to the present invention.

The insulated gate field effect transistor of this embodiment further suppresses the deterioration of the mobility in the buried channel type p channel MOSFET shown in FIG.
In addition, even if the junction depth of the channel region is increased in order to further reduce the internal noise, the device is configured to be able to appropriately suppress the occurrence of the punch-through and the variation in the threshold value described above.

That is, in the buried channel type MOSFET of this embodiment, basically, the p + type source / drain region 2 is formed on the n type silicon (Si) well 1.
And an n + -type gate electrode 5 via a gate oxide film 4 on the surface of the well 1.
Is arranged.

In the MOSFET of this embodiment, in particular, the channel region includes a first channel region 31 provided on the interface side with the gate oxide film 4 and a lower portion (at a deeper position) of the first channel region 31. ) Has a two-layer structure with the second channel region 32 disposed in the first region.

In the channel region having such a two-layer structure, the first channel region 31 has an impurity concentration on the surface forming the interface with the gate oxide film 4 in the n-type silicon (Si) well 1 with a total impurity concentration. The impurity concentration is set so as to be equal to or higher than the concentration. As described above, the setting of the impurity concentration in the channel region makes it less likely to be affected by the surface concentration of the well 1 which varies greatly, and the threshold value Vth of the MOSFET takes a stable value.

In the same channel region, the other second
The channel region 32 is a region provided to increase the junction depth with the well 1 as a channel region. In the MOSFET of the embodiment, the impurity concentration is higher than the impurity concentration of the first channel region 31. Is formed as a layer having

Therefore, when the junction depth of the channel region is increased, the surface concentration of the channel region decreases, and the above-mentioned contradictory phenomena are caused by the channel having the two-layer structure of the first and second channel regions 31 and 32. It can be solved well by the region structure.

Moreover, since the second channel region 32 is formed as a layer having a higher impurity concentration than the first channel region 31, the path of the drain current can be more effectively separated from the interface with the gate oxide film 4. You can do it.

As shown in FIG. 1, the MOSFET of this embodiment further selectively covers the channel regions 31 and 32 on the side of the source / drain region 2 immediately below the channel regions 31 and 32. An n-type high concentration impurity layer 7 is provided.

Therefore, even if the junction depth as a channel region is set deep through the second channel region 32, the presence of the high concentration impurity layer 7 causes n of the well 1 near the lower portion of the source / drain region 2. The decrease in the concentration of the type impurity is suitably suppressed. Therefore, the occurrence of the above-described punch-through and the like can be satisfactorily avoided.

Incidentally, in the MOSFET of the embodiment,
The film 6 is a sidewall oxide film 6 that covers the side surface of the gate electrode 5. FIG. 2 shows the buried channel type p of such an embodiment.
An example of a manufacturing process of a channel MOSFET is shown. Next, a manufacturing method of the MOSFET of the embodiment will be described with reference to FIG.

The buried channel type p-channel MOSFET of this embodiment shown in FIG. 1 can be manufactured through the steps listed below. (1) First, according to a well-known ordinary process, the impurity concentration is 1.0 × 10 16 / cm 3 (“＾” represents a power).
After forming the n-type silicon (Si) well 1, a 20-nm-thick oxide film is formed thereon. (2) Next, through the 20 nm oxide film,
Boron (B) for forming the channel region 31 is implanted with an implantation energy of 30 KeV and an implantation amount of 0.5 × 10 12 / cm 2.
(“＾” represents a power). (3) Subsequently, the boron (B) for forming the second channel region 32 is implanted through an oxide film of the same thickness of 20 nm at an implantation energy of 80 KeV and an implantation amount of 0.9 × 10 12 / cm 2.
(“＾” represents a power). (4) After that, the 20 nm oxide film is peeled off, and a 10 nm thick gate oxide film 4 is formed in its place. The cross-sectional structure of the device after these steps (1) to (4) is shown in FIG.
The embodiment shown in FIG. (5) Next, as shown in FIG. 2B, after forming n + type polysilicon, patterning is performed including the gate oxide film 4 to form a gate electrode 5. (6) Then, phosphorus (P) is implanted in a self-aligning manner with an implantation energy of 180 KeV and an implantation amount of 1.0 × 10 ＾ 12 / cm.
Ion implantation is performed at ＾ 2 (“＾” represents a power) to form an n-type high-concentration impurity layer 7 immediately below the p − -type first and second channel regions 31 and 32. (7) Next, after depositing silicon dioxide (SiO2) using a chemical vapor deposition method, so-called CVD method, the silicon dioxide (SiO2) is removed by etching, and the side wall oxide film 6 is removed in the manner shown in FIG. Form. (8) Then, also in a self-aligned manner, boron difluoride (BF2) was implanted at an implantation energy of 40 KeV and an implantation amount of 3.0 × 10 @ 15 / cm @ 2 ("" represents a power).
Ion implantation at the p + -type source / drain region 2
To form

Through the above steps, a buried channel p-channel MOSFET having the structure shown in FIG. 1 can be obtained. Although not shown for convenience, the buried channel type p-channel MOSFET device is completed through a well-known ordinary MOSFET manufacturing process thereafter.

FIG. 3 shows the MO of the embodiment thus manufactured.
A simulation result is shown for the transition of the absolute value of the total impurity concentration value with respect to the distance from the interface of the gate oxide film 4 / n-type silicon (Si) well 1 to the depth direction of the well 1 in the SFET.

The absolute value of the total impurity concentration value is n
As described above, when the type impurity concentration is ND and the p-type impurity concentration is NA, it is expressed as | ND -NA |.

As is apparent from comparison with the simulation result shown in FIG. 7, FIG. 3 shows that: (1) boron (B) is implanted at an energy of 30;
The junction depth of the p-type channel regions (31, 32) with the well 1 is deeper than in the case where ions are implanted with KeV. As described in (b) above, boron (B) is implanted at an energy of 80.
The surface impurity concentration of the p-type channel regions (31, 32) is maintained at a higher concentration than in the case of ion implantation at KeV. That is, the impurity concentration of the n-type silicon (Si) well 1 (ND = 1.0 × 10 ＾ 16 / cm ＾ 3)
) Or higher. You can see that.

FIG. 4 shows an MO of the same embodiment.
FIG. 5 shows a simulation result of a change in hole concentration with respect to a distance from an interface between a gate oxide film 4 and an n-type silicon (Si) well 1 to a depth direction of the SFET in the SFET.

Here, the voltage Vg applied to the gate electrode 5 is -2.0 V. As apparent from comparison with the simulation result shown in FIG.
According to the above, as described in (a), boron (B) is implanted at an energy of 30
The hole concentration of the p-type channel regions (31, 32) is more widened in the depth direction of the n-type silicon (Si) well 1 than in the case of ion implantation with KeV. You can see that. This means that the gate oxide film 4 / silicon (S
i) As described above, it means that the drain current flows more distant from the well 1 interface, and thus, it is less susceptible to lattice defects existing near the interface.

As described above, according to the buried channel type MOSFET of this embodiment, the semiconductor substrate (the n-type silicon (Si) well 1 ) Can be made deeper.

As a result, the path of the drain current also moves away from the interface with the gate oxide film 4, and as a result, the deterioration of the mobility is further suppressed and the internal noise is further reduced. That is, the embedded channel type M
As the stability of the OSFET,
Further higher performance can be achieved.

In the MOSFET of this embodiment, the channel regions are divided into the first channel region 31 and the second channel region 3.
However, as long as the impurity concentration on the surface is properly maintained through the first channel region 31, a further multi-layer structure is also possible. According to such a structure, the junction depth of the channel region can be further increased.

In the MOSFET of the embodiment, the second
It is assumed that the channel region 32 is formed as a layer having a higher impurity concentration than the first channel region 31. However, depending on the impurity concentration conditions surrounding the region including the channel region, it is not always necessary that the impurity concentration of each of these layers is different or that the deeper the layer, the higher the impurity concentration. In any case, if the channel region structure has two or more layers, the same effect as above can be expected.

[0068]

The method of manufacturing the MOSFET of the above-described embodiment is merely an example. For example, the formation of the channel region having the above structure is not limited to the ion implantation, and the channel region may be formed by a method such as thermal diffusion.

The MOSF of the embodiment shown in FIG.
Like the ET, the high-concentration impurity layer 7 is provided at a position where the junction depth with the semiconductor substrate (well 1) is deeper than the junction depth with the semiconductor substrate (well 1) in the channel region. Is desirable. However, the presence of the high-concentration impurity layer 7 itself suppresses a decrease in the concentration of the n-type impurity near the lower portion of the source / drain region 2, so that the same effect can be expected even if the condition is not always satisfied.

In this embodiment, the device structure of the buried channel type p-channel MOSFET has been described for convenience. However, it is to be understood that the insulated gate field effect transistor according to the present invention is not limited to such a p-channel MOSFET. Of course. In addition, a buried channel type n-channel MOSFET or M
Not only an OS (metal-oxide-semiconductor) structure but also an insulated gate field-effect transistor adopting a so-called MIS (metal-insulator-semiconductor) structure, since it is configured as a buried channel type, The configuration according to the present invention can be applied in a manner similar to the above, and further higher performance can be achieved.

[0072]

As described above, according to the present invention, the junction depth of the channel region with the semiconductor substrate can be increased without causing a decrease in the concentration on the surface of the channel region or occurrence of punch-through. Become like

That is, as a buried channel type insulated gate field effect transistor, its stability is sufficiently ensured, and the deterioration of mobility is further suppressed.・ Internal noise is further reduced. For example, higher performance can be achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a device structure of an embodiment of an insulated gate field effect transistor according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the insulated gate field effect transistor of the same embodiment.

FIG. 3 is a graph showing a simulation result of an absolute value change of a total impurity concentration value with respect to a distance from a gate oxide film / well interface to a well depth direction in the insulated gate field effect transistor of the example. is there.

FIG. 4 is a graph showing a simulation result of a change in hole concentration with respect to a distance from a gate oxide film / well interface to a well depth direction in the insulated gate field effect transistor of the same example.

FIG. 5 is a sectional view showing a basic device structure of a buried channel type p-channel MOSFET.

FIG. 6 shows a conventional buried channel type p-type MOSFET which is improved to miniaturize the MOSFET shown in FIG.
FIG. 3 is a cross-sectional view illustrating a device structure of a channel MOSFET.

FIG. 7 shows the total impurity concentration of two types of p − -type channel regions formed by changing the ion implantation energy of boron in the above-mentioned buried channel type MOSFET with respect to the distance from the gate oxide film / well interface to the well depth direction. 9 is a graph showing a simulation result of a change in an absolute value of a value.

FIG. 8 is a graph showing a simulation result of a change in hole concentration with respect to a distance in a depth direction of a well from a gate oxide film / well interface in the two types of p − -type channel regions.

[Explanation of symbols]

1 ... n-type silicon (Si) well, 2 ... p + type source
Drain region, 3, 31, 32... P-type channel region,
4 gate oxide film, 5 n + type gate electrode, 6 sidewall oxide film, 7 n-type high concentration impurity layer.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-196170 (JP, A) JP-A-61-160975 (JP, A) JP-A-63-95672 (JP, A) JP-A-55-195672 16480 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (3)

(57) [Claims] 1. A gate electrode provided on a surface of a semiconductor substrate of a conductivity type via a gate insulating film, and a source selectively formed on the semiconductor substrate by a conductivity type opposite to the substrate. A buried channel type insulated gate field effect transistor having a drain region and a channel region formed between the source / drain regions and having the same conductivity type as the source / drain regions, wherein the channel region is The semiconductor substrate has a laminated structure of at least two layers laminated in the thickness direction of the semiconductor substrate, and has the same conductivity type as that of the semiconductor substrate which selectively covers the channel region on the side of the source / drain region immediately below the channel region. Wherein the channel region has a surface impurity concentration forming an interface with the gate insulating film, which is higher than a total impurity concentration. An insulated gate field effect transistor, wherein the impurity concentration is set so as to be equal to or higher than the impurity concentration of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the channel region is provided at a first region provided on an interface side with the gate insulating film, and at a position deeper than the first region. 2. The insulated gate field effect transistor according to claim 1, comprising a second region having a high impurity concentration. 3. The high-concentration impurity layer according to claim 1, wherein a junction depth with the semiconductor substrate is greater than a junction depth of the channel region with the semiconductor substrate. Insulated gate field effect transistor.