JP3340906B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an output circuit using a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, an output circuit of a semiconductor integrated circuit is
There was something like that shown in Figure 8. Hereinafter, a conventional output circuit will be described with reference to FIG.

A conventional output circuit includes a signal input terminal 1, an enable signal input terminal 2, an inverter 3, and a two-input NAND circuit.
4, 2-input NOR circuit 5, PMOS transistors P1, NM
It comprises a power supply terminal 6 to which a power supply potential of the OS transistor N1 and 3V is applied, a ground terminal 7 to which a ground potential is applied, and an output terminal 8.

A signal input terminal 1 is connected to one input terminal of each of a two-input NAND circuit 4 and a two-input NOR circuit 5,
The enable signal input terminal 2 is connected to the other input terminal of the two-input NAND circuit 4 and the input terminal of the inverter circuit 3. The output terminal of the inverter circuit 3 is a 2-input NOR circuit
5 is connected to the other input terminal. The output terminals of the two-input NAND circuit 4 and the two-input NOR circuit 5 are PMO
It is connected to the gate electrodes of the S transistor P1 and the NMOS transistor N1. The PMOS transistor P1 is connected between the power supply terminal 6 (3V) and the output terminal 8, and is connected to the PMOS transistor P1.
The N well which is the substrate of the transistor P1 is a 3V power supply terminal
Connected to 6. The NMOS transistor N1 is connected between the ground terminal 7 and the output terminal 8, and the substrate (P well) of the NMOS transistor N1 is connected to the ground terminal 7.

Next, the operation of this circuit will be described. First, when an “L” level (0 V) signal is input to the enable signal input terminal 2 as an input signal, a two-input NAND circuit
Since the outputs of the 4- and 2-input NOR circuits 5 become "H" level and "L" level, respectively, the PMOS transistor P
1. The NMOS transistor N1 is turned off. As a result, the output terminal 8 is in a floating state regardless of the input signal to the signal input terminal 1.

Next, when an "H" level signal is input to the enable signal input terminal 2 as an input signal, and when an "L" level signal is input to the signal input terminal 1, the PMOS is output.
Transistor P1 is off, NMOS transistor N1
Is turned on. As a result, the output terminal 8 outputs an "L" level signal. On the other hand, when an "H" level signal is input to the signal input terminal 1, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off. As a result, the output terminal 8 outputs an "H" level signal.

[0007]

However, in the conventional output circuit shown in FIG. 8, when an external element having a power supply voltage higher than 3 V, for example, a bus to which a signal of 5 V is applied is connected to the output terminal 8, the output is When a voltage of 5V applied to the bus is applied to the output terminal 8 while the terminal 8 is in a floating state, the drain (P active) of the PMOS transistor P1 becomes 5V. Since the substrate (N-well) of the PMOS transistor P1 is connected to the 3V power supply terminal 6, a forward voltage is applied to the diode between the drain (P-active) and the substrate (N-well). Current flows through the diode. As described above, when a voltage of 5 V is applied due to the influence of a bus to which a 5 V signal is applied to the output terminal 8, a bus to which a 5 V signal is applied → the output terminal 8 → the drain of the PMOS transistor P 1 → the substrate of the PMOS transistor P 1 → There has been a case where a leakage current of a unit of several mA flows through the path of the power supply terminal 6 of the output circuit, and improvement has been desired.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a typical one thereof is the first one.
A first MOS transistor having a gate connected to the first node, one terminal connected to a first power supply terminal having a first potential, and another terminal connected to a second node, A second MOS transistor formed in a floating well having a gate connected to one node, one terminal connected to the second node, and the other terminal connected to the output terminal; The first with the first potential
A gate formed in a floating well having a gate connected to the power supply terminal, one terminal connected to the first node, and the other terminal connected to the output terminal.
An output circuit comprising three MOS transistors.

[0009]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention. Parts common to those in FIG. 8 are denoted by the same reference numerals. Hereinafter, the output circuit of the present invention will be described with reference to FIG.

A signal input terminal 1 is connected to one input terminal of each of a two-input NAND circuit 4 and a two-input NOR circuit 5,
The enable signal input terminal 2 is connected to the other input terminal of the two-input NAND circuit 4 and the input terminal of the inverter circuit 3. The output terminal of the inverter circuit 3 is a 2-input NOR circuit 5
Is connected to the other input terminal. The output terminal of the two-input NAND circuit 4 is connected to the gate electrode of the PMOS transistor P1 and the source of the NMOS transistor N11. The source of the PMOS transistor P1 is connected to the power supply terminal 6 (3
V), the drain is connected to the source of the PMOS transistor P12 and the source of the PMOS transistor P13. The gate electrode of the NMOS transistor N11 is a power supply terminal
6 (3V), the drains are connected to the gate electrodes of the PMOS transistors P12 and P13 and the source of the PMOS transistor P14. The drain of the PMOS transistor P12 is connected to the N well B1, which is the substrate of the PMOS transistors P12, P13 and P14. This PMOS
The N well B1, which is the substrate of the transistors P12, P13 and P14, is not connected to the power supply terminal 6 (3V), and the whole well is in a floating state. In other words, the PMOS transistors P12, P13, and P14 are transistors formed in the floating N-well B1. The drain of the PMOS transistor P13 and the PM
The drain of the OS transistor P14 is connected to the output terminal 8. The gate electrode of the PMOS transistor P14 is connected to the power supply terminal 6 (3V). 2-input NOR circuit 5
Is connected to the gate electrode of the NMOS transistor N1, the source of the NMOS transistor N1 is connected to the ground terminal 7, and the drain is connected to the source of the NMOS transistor N12. The drain of the NMOS transistor N12 is connected to the output terminal 8, and the gate electrode is connected to the power supply terminal 6 (3V). The substrate of the PMOS transistor P1 is connected to the power supply terminal 6.

Next, the operation of this circuit will be described.

First, when an "L" level (0 V) signal is input to the enable signal input terminal 2 as an input signal,
The output of the input NAND circuit 4 becomes "H" level (3 V), and the PMOS transistor P1 is turned off. In addition, the signal of “H” level is input to the 2-input NOR through the inverter circuit 3.
The output of the two-input NOR circuit 5 is "
When the input signal to the enable signal input terminal 2 is at the "L" level, the PMOS transistor P1 is turned off.
1. Both the NMOS transistor N1 is turned off and the output terminal 8 is in a floating state regardless of the input signal to the signal input terminal 1.

In this state, when 5 V is applied to the output terminal 8 from an external power supply terminal or the like (for example, when the bus to which the output terminal 8 is connected becomes 5 V), the PMOS is used.
A forward voltage is applied to the diodes between the drains and the substrates of the transistors P13 and P14, a current flows from the P-active of the drain to the N-well B1 of the substrate, and the potential of the N-well B1 in a floating state rises to around 5V. . As a result of N-well B1 rising to around 5V, PMO
Since the gate potential of the S transistor P14 is 3 V, the substrate potential becomes relatively higher, and the PMOS transistor P14
Is turned on. Since the PMOS transistor P14 is turned on, the source of the PMOS transistor P14 has the voltage (5V) applied to the output terminal 8, and the gate potentials of the PMOS transistors P12 and P13 connected to the source of the PMOS transistor P14 are also 5V. Become. As a result, the PMOS transistors P12 and P13 are turned off, so that 5 V applied to the output terminal 8 is transmitted to the PMOS transistor P1 and no leak current flows through the substrate of P1. The N well B1, which is the substrate of the PMOS transistors P12 and P13, is in a floating state.
Since it is not connected to the V power supply terminal 6, there is no fear that a leak current flows to the power supply terminal 6 through the N well B1 of the substrate due to the drain-substrate diodes of the PMOS transistors P12 and P13.

The upper diagram in FIG. 3 shows a change in the potential of the N-well B1 in the floating state when the voltage applied to the output terminal 8 is OUT and OUT is changed from 0 to 5.5 V, and the gate electrodes of the PMOS transistors P12 and P13. The change in the applied potential (S13). The figure below shows IM1 with the current as seen from the power supply terminal 6 (3V) side of this circuit as IM1.
N-well B in a floating state as described above
1 rises to around 5 V when 5 V is applied to the output terminal 8. S13 applied to the gate electrodes of the PMOS transistors P12 and P13 is 5V. It can be seen that the current IM1 flowing in the circuit is about 8 nA, which is much smaller than the conventional leakage current of several mA.

Next, when an "H" level signal is input to the enable signal input terminal 2 as an input signal and a "L" level signal is input to the signal input terminal 1 as a two-input NAND circuit. The output of 4 becomes "H" level, and the PMOS transistor P1 is turned off. Since the two-input NOR circuit 5 receives an "L" level signal at both input terminals, the output becomes "H" level and the NMO
The S transistor N1 is turned on. Since the NMOS transistor N11 is always on, a two-input NAND is connected to the gate electrodes of the PMOS transistors P12 and P13.
The “H” level signal which is the output of the circuit 4
The OS transistors P12 and P13 are both turned off. As a result, the output terminal 8 outputs an "L" level signal. When an "H" level signal is input to the signal input terminal 1 as an input signal, the output of the two-input NAND circuit 4 becomes "L" level and the PMOS transistor P1 is turned on. 2 inputs N
The output of the OR circuit 5 becomes "L" level, and the NMOS transistor N1 is turned off. An “L” level signal which is an output of the two-input NAND circuit 4 is supplied to the gate electrodes of the PMOS transistors P12 and P13. PMO
Since the S-transistors P12 and P13 have a diode between the source and the substrate, when the potential of the N-well B1 of the substrate is lower than 3 V, a forward voltage is applied to the diode, and the diode between the source and the substrate is added to the diode. Electric current flows. This current causes the PMOS transistors P12, P1
Since the N well B1, which is the substrate of P14 and P14, has risen to around 3V, the substrate potential is relatively higher than the gate potential of the PMOS transistors P12 and P13, and the PMOS transistors P12 and P13 are turned on. . By turning on the PMOS transistor P12, the potential of the N-well B1 in the floating state is reliably increased to 3V, and the PMOS transistor P12 is turned on.
This has the effect of further stabilizing the operation of MOS transistor P13. As a result of the above operation, the output terminal 8 becomes “H” level (3
V) is output.

FIG. 4 shows a case where the potential applied to the signal input terminal 1 when the "H" level signal is input to the enable signal input terminal 2 is set to IN and IN is changed from 0 to 3 V (L to H). Of the output terminal 8, the gate potential S11 of the PMOS transistor P1, the gate potential S12 of the NMOS transistor N1, the gate potential S13 of the PMOS transistors P12 and P13, and the potential of the N well B1 in the floating state. As shown in the figure, the signal IN applied to the signal input terminal 1 is at "L" level, and the output terminal 8 is at "L" level as OUT.
Level, the signal IN is at “H” level and the output terminal 8 is OUT
Output a signal of “H” level.

In this circuit, when a voltage of 5 V is applied to the output terminal 8 of the NMOS transistors N11 and N12, the voltage of 5 V is directly applied to the two-input NAND circuits 4 and N12.
2-input NAND circuit 4 over MOS transistor N1
And the function of preventing the possibility that the NMOS transistor N1 or the like is destroyed.

As described above, according to the output circuit of the first embodiment of the present invention, an output signal similar to that of the conventional output circuit is output from the output terminal 8 for an input signal supplied to each input terminal. On the other hand, when a potential (5 V) higher than the potential (3 V) of the power supply terminal 6 is input to the output terminal 8 from an external circuit or the like, the floating N well B1, which is the substrate of the PMOS transistors P12, P13, and P14, is near 5V. As a result, the PMOS transistors P12 and P13 are turned off. Thus, the PMOS transistors P12, P12
When 13 is turned off, a potential of 5 V is applied to the PMOS transistor P1, so that no leak current flows from the drain of the PMOS transistor P1 to the power supply terminal 6 through the substrate. Also, PMOS transistors P12, P13,
Since the floating N well B1 itself, which is the substrate of P14, is not connected to the 3V power supply terminal 6, the output terminal
It is possible to prevent leakage current from flowing from 8 to the power supply terminal 6.

FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention. Note that parts common to those in FIG. 1 are denoted by the same reference numerals. Hereinafter, an output circuit according to the second embodiment of the present invention will be described with reference to FIG.

The signal input terminal 1 is connected to one input terminal of each of a two-input NAND circuit 4 and a two-input NOR circuit 5,
The enable signal input terminal 2 is connected to the other input terminal of the two-input NAND circuit 4 and the input terminal of the inverter circuit 3. The output terminal of the inverter circuit 3 is a 2-input NOR circuit 5
Is connected to the other input terminal. The output terminal of the two-input NAND circuit 4 is connected to the gate electrode of the PMOS transistor P1 and the source of the NMOS transistor N11. The source of the PMOS transistor P1 is connected to the power supply terminal 6 (3
V), the drain is connected to the source of the PMOS transistor P12 and the source of the PMOS transistor P13. The gate electrode of the NMOS transistor N11 is a power supply terminal
At 6 (3V), the drain is connected to the gate electrodes of PMOS transistors P12 and P13 and the source of PMOS transistor P14. The drain of the PMOS transistor P12 is connected to the PMOS transistors P12, P13, P14 and P
The N-well is connected to an N-well B1, which is a substrate of 25, and is in a floating state as in the first embodiment. That is, in the second embodiment, the PMOS transistors P12, P13, P14 and P25 are formed in the floating N-well B1. PMOS transistor P2
The source of No. 5 is connected to this floating N well B1. PMOS transistors P13, P14 and P
The drain 25 is connected to the output terminal 8. PMOS
The gate electrodes of the transistors P14 and P25 are connected to the power supply terminal 6 (3
V). The output terminal of the two-input NOR circuit 5 is connected to the gate electrode of the NMOS transistor N1.
The source of the MOS transistor N1 is connected to the ground terminal 7 and the drain is connected to the source of the NMOS transistor N12. The output terminal of the drain of the NMOS transistor N12
8. The gate electrode is connected to the power supply terminal 6 (3V).
The substrate of the PMOS transistor P1 is connected to the power supply terminal 6.

Next, the operation of this circuit will be described.

First, when an “L” level (0 V) signal is input to the enable signal input terminal 2 as an input signal,
The output of the input NAND circuit 4 becomes "H" level (3 V), and the PMOS transistor P1 is turned off. In addition, the signal of “H” level is input to the 2-input NOR through the inverter circuit 3.
The output of the two-input NOR circuit 5 is "
When the input signal to the enable signal input terminal 2 is at the "L" level, the PMOS transistor P1 is turned off.
1. Both the NMOS transistor N1 is turned off and the output terminal 8 is in a floating state regardless of the input signal to the signal input terminal 1.

In this state, when 5 V is applied to the output terminal 8 from an external power supply terminal or the like (for example, when the bus to which the output terminal 8 is connected becomes 5 V), the PMOS
A forward voltage is applied to the diodes between the drains and the substrates of the transistors P13, P14 and P25, and a current flows through these diodes. As a result, the voltage of the N well B1 as the substrate rises to around 5V. As a result of the N-well B1 rising to around 5V, the PMOS transistors P14 and P25 have a gate potential of 3V, so that the substrate potential becomes relatively higher and the transistor is turned on. Since the PMOS transistor P14 is turned on, 5V applied to the output terminal is
The gate electrodes of the PMOS transistors P12 and P13 appearing at the source of the transistor P14 and connected to the source of the PMOS transistor P14 have a voltage of 5V. Also PM
Since the OS transistor P25 is also turned on, the N well B
The potential of 1 is 5 V instead of around 5 V (5-α) as in the first embodiment, and the gate potentials of the N well B1 of the substrate and the PMOS transistors P12 and P13 are exactly the same. Therefore, the PMOS transistors P12 and P13 are turned off with a more stable operation than in the first embodiment. PM
When the OS transistors P12 and P13 are turned off, 5V applied to the output terminal 8 is transmitted to the PMOS transistor P1, and no leak current flows through the substrate of the PMOS transistor P1. In the second embodiment, since the N-well B1, which is the substrate of the PMOS transistors P12, P13, and P25, is in a floating state as in the first embodiment, the PMOS transistors P12, P13, and P25 are in a floating state.
There is no fear that a leak current flows to the power supply terminal 6 through the N well B1 of the substrate due to the 25 drain-substrate diodes.

The upper diagram in FIG. 5 shows that the voltage applied to the output terminal 8 is OU
When OUT is changed from 0 to 5.5 V as T, the potential change of the N well B1 in the floating state and the potential (S2) applied to the gate electrodes of the PMOS transistors P12 and P13
The change in 3) below shows IM2 with the current seen from the power supply terminal (3V) side of this circuit as IM2. As described above, when 5 V is applied to the output terminal 8, the N well B1 in the floating state rises to 5V and the same is applied to the gate electrodes of the PMOS transistors P12 and P13.
A voltage of 5V is applied. As a result, the operation of the circuit is further stabilized as a result of the potentials applied to the substrate and the gate being completely matched, and the current IM2 flowing through the circuit is about 3 nA,
It can be seen that it is even smaller than in the first embodiment.

Next, when an "H" level signal is input to the enable signal input terminal 2 as an input signal, and a "L" level signal is input to the signal input terminal 1 as an input signal, the two-input NAND circuit 4 Becomes "H" level, and the PMOS transistor P1 is turned off. 2 input NO
Since an R-level signal is input to both input terminals of the R circuit 5, the output becomes an H-level and the NMOS transistor N1 is turned on. Further, since the NMOS transistor N11 is always on, the signal of "H" level which is the output of the two-input NAND circuit 4 is given to the gate electrodes of the PMOS transistors P12 and P13, and both the PMOS transistors P12 and P13 are turned off. As a result, the output terminal 8 outputs an "L" level (0 V) signal. When an "H" level signal is input to the signal input terminal 1 as an input signal, the output of the two-input NAND circuit 4 becomes "L" level and the PMOS transistor P1 is turned on. 2 input NO
The output of the R circuit 5 becomes "L" level, and the NMOS transistor N1 is turned off. Since the NMOS transistor N11 is on, the PMOS transistor P12,
An “L” level signal which is an output of the two-input NAND circuit 4 is applied to the gate electrode of P13. Since the N-well B1, which is the substrate of the PMOS transistors P12, P13, and P14, rises to about 3 V due to the diode between the source and the substrate of the PMOS transistors P12 and P13,
The transistors P12 and P13 have a relatively higher potential on the substrate and are both turned on. As a result, the output terminal 8 becomes “
A signal of H level (3 V) is output.

FIG. 6 shows a case where the potential applied to the signal input terminal 1 when the signal of the "H" level is input to the enable signal input terminal 2 is IN and the IN is changed from 0 to 3 V (L to H). Of the output terminal 8, the gate potential S21 of the PMOS transistor P1, the gate potential S22 of the NMOS transistor N1, the gate potential S23 of the PMOS transistors P12 and P13, and the potential of the N well B1 in the floating state. As shown in the figure, the signal IN applied to the signal input terminal 1 is at "L" level, and the output terminal 8 is at "L" level as OUT.
Level, the signal IN is at “H” level and the output terminal 8 is OUT
Output a signal of “H” level.

According to the output circuit according to the second embodiment of the present invention, an output signal similar to that of a conventional output circuit is output to the output terminal 8 for an input signal applied to each signal input terminal. Even if a potential (5 V) higher than the potential (3 V) of the power supply terminal 6 is input to the output terminal 8 from an external circuit or the like, the N-well B1 which is a substrate of the PMOS transistors P12 and P13 is operated by the PMOS transistor P25. PM
The potential rises to 5 V, which is the same potential as the gate potentials of the OS transistors P12 and P13. As a result, the PMOS transistors P12 and P13 operate more stably than in the first embodiment, and it is possible to more reliably prevent a leak current from flowing from the output terminal 8 to the power supply terminal 6.

FIG. 7 is a circuit diagram showing an output circuit according to a third embodiment of the present invention. 1 and 2 are denoted by the same reference numerals. Hereinafter, the output circuit of the present invention will be described with reference to FIG.

A signal input terminal 1 is connected to one input terminal of each of a two-input NAND circuit 4 and a two-input NOR circuit 5 and an NMOS.
The enable signal input terminal 2 is connected to the gate electrode of the transistor N75, and is connected to the other input terminal of the two-input NAND circuit 4, the input terminal of the inverter circuit 3, and the gate electrode of the NMOS transistor N76. The output terminal of the inverter circuit 3 is connected to the other input terminal of the two-input NOR circuit 5. The output terminal of the 2-input NAND circuit 4 is PM
The gate electrode of the OS transistor 6 is connected to the source of the NMOS transistor N11. The source of the PMOS transistor P1 is at the power supply terminal 6 (3V), and the drain is PM
It is connected to the source of the OS transistor P12 and the source of the PMOS transistor P13. The drain of the NMOS transistor N11 is connected to the PMOS transistors P12 and P13.
, The source of the PMOS transistor P14, and the drain of the NMOS transistor N74. The source of the NMOS transistor N74 is connected to the drain of the NMOS transistor N75. NMOS
The source of the transistor N75 is an NMOS transistor N76.
And the source of the NMOS transistor N76 are connected to the ground terminal 7. PMOS transistor P12
Are PMOS transistors P12, P13 and P14.
Of the PMOS transistor P13 and the PMOS transistor P13.
The drain of the S transistor P14 is connected to the output terminal 8. The gate electrode of the PMOS transistor P14 is connected to the power supply terminal 6 (3V). The output terminal of the two-input NOR circuit 5 is connected to the gate electrode of the NMOS transistor N1, the source of the NMOS transistor N1 is connected to the ground terminal 7, and the drain is connected to the source of the NMOS transistor N12. The drain of the NMOS transistor N12 is connected to the output terminal 8, and the gate electrode is connected to the power supply terminal 6 (3V). The substrate of the PMOS transistor P1 is connected to the power supply terminal 6.

Next, the operation of this circuit will be described.

First, when an "L" level signal is input to the enable signal input terminal 2 as an input signal, two inputs N
The output of the AND circuit 4 becomes "H" level, and the PMOS transistor P1 is turned off. Further, since a signal of "H" level is input to the two-input NOR circuit 5 via the inverter circuit 3, the output of the two-input NOR circuit 5 becomes "L" level, and the NMOS transistor N1 is turned off. Thus, when the input signal to the enable signal input terminal 2 is at "L" level, both the PMOS transistor P1 and the NMOS transistor N1 are turned off, and the output terminal 8 is in a floating state regardless of the input signal to the signal input terminal 1. Becomes

In this state, when 5 V is applied to the output terminal 8 from an external power supply terminal or the like (for example, when the bus to which the output terminal 8 is connected becomes 5 V), the PMOS
A forward voltage is applied to the diode between the drains and the substrates of the transistors P13 and P14, and a current flows through the diodes, so that the PMOS transistors P13 and P14
The N-well B1, which is the substrate of P14, rises to around 5V.
As a result of the N-well B1 rising to around 5 V, the substrate potential is relatively higher because the gate potential of the PMOS transistor P14 is 3 V, and the PMOS transistor P14 is turned on. Since the PMOS transistor P14 is turned on, the source of the PMOS transistor P14 is also the output terminal 8.
, And the gate potentials of the PMOS transistors P12 and P13 connected to the source of the PMOS transistor P14 also become 5V. When the gate potential of the PMOS transistors P12 and P13 becomes 5V, PM
The OS transistors P12 and P13 are turned off. Therefore, 5V applied to the output terminal 8 is the PMOS transistor P
The leak current does not flow through the P1 substrate through the P1 substrate. The PMOS transistors P12 and P13
Since the N-well B1 as a substrate is in a floating state, there is no fear that a leak current flows to the power supply terminal 6 due to a diode between the drains and the substrates of the PMOS transistors P12 and P13.

In this circuit configuration, when 5 V is applied to the source, that is, the output terminal of the PMOS transistor P14, the NMOS transistors N74, N75,
N76 is connected. In this case, a leak current from the output terminal 8 to the ground terminal 7 is considered. However, when the signal applied to the enable signal input terminal 2 is at “L” level,
The NMOS transistor N76 is always off. Therefore, the signal applied to the signal input terminal 1 is "H".
Even if the level changes to the level and the NMOS transistor N75 is turned on, as long as the signal applied to the enable signal input terminal 2 is at the "L" level, the ground terminal 7 from the output terminal 8 through the transistor P14 → N74 → N75 → N76. It is unlikely that a leak current will flow through the device.

Next, when an "H" level signal is input to the enable signal input terminal 2 as an input signal, and a "L" level signal is input to the signal input terminal 1 as an input signal, the 2-input NAND circuit 4 Becomes "H" level, and the PMOS transistor P1 is turned off. 2 input NO
Since an R-level signal is input to both input terminals of the R circuit 5, the output becomes an H-level and the NMOS transistor N1 is turned on. Further, since the NMOS transistor N11 is always on, the signal of "H" level which is the output of the two-input NAND circuit 4 is given to the gate electrodes of the PMOS transistors P12 and P13, and both the PMOS transistors P12 and P13 are turned off. As a result, the output terminal 8 outputs an "L" level signal. Signal input terminal 1
When an "H" level signal is input to the
The output of the input NAND circuit 4 becomes "L" level and the
The S transistor P1 is turned on. 2-input NOR circuit
The output of 5 becomes "L" level and the NMOS transistor N1
Is turned off. Since the NMOS transistor N11 is in the ON state, an "L" level signal which is the output of the two-input NAND circuit 4 is supplied to the gate electrodes of the PMOS transistors P12 and P13. PMOS transistor P
12, PMOS by the diode between the source and the substrate of P13
The N-well which is the substrate of the transistors P12, P13 and P14 is
Since the voltage has risen to around 3 V, both the PMOS transistors P12 and P13 are turned on. As a result, output terminal 8
Outputs an "H" level (3 V) signal.

Here, a signal of "H" level is supplied to the enable signal input terminal 2 as an input signal, and the input signal supplied to the signal input terminal 1 changes from "L" to "H" level. Considering this, the NMOS transistor N74 is always on, and the gate potential of the NMOS transistor N75 changes from "L" to "H" level in accordance with the change of the input signal IN. In the NMOS transistor N76, the signal given to the enable signal input terminal 2 is "H".
It is on for level. NMOS transistor N
When the gate potential of 75 changes to "H" level, NMOS
Since the transistor N75 is turned on and both the NMOS transistors N74 and N75 are turned on, the potential applied to the gate of the PMOS transistor P13 changes from “H” to “H” without passing through the two-input NAND circuit 4 and the NMOS transistor N11.
L ”level. That is, the enable signal input terminal
When an "H" level signal is given as an input signal to 2 and the input signal given to the signal input terminal 1 changes from "L" to "H" level, the PMOS transistor P13 is turned off to on. Is faster than in the first and second embodiments.

As described above, according to the output circuit of the third embodiment of the present invention, an output signal similar to that of the conventional output circuit is output to the output terminal 8 for an input signal supplied to each input terminal. Further, even if a potential (5 V) higher than the potential (3 V) of the power supply terminal 6 is input to the output terminal 8 from an external circuit or the like, the PM
The rise of the N-well (B1), which is the substrate of the OS transistors P12, P13, and P14, to around 5 V turns off the PMOS transistors P12 and P13, thereby preventing leakage current from flowing from the output terminal 8 to the power supply terminal 6. be able to. The signal applied to the enable input signal terminal 2 is at "H" level, and the input signal applied to the signal input terminal 1 is changed from "L" to "H" level (that is, the output level is from "L" to "H"). Change to level), PM
Since the potential applied to the gate of the OS transistor P13 changes from “H” to “L” level without passing through the two-input NAND circuit 4 and the NMOS transistor N11, the change of the PMOS transistor P13 from OFF to ON is faster. The change of the output signal also becomes faster.

In this circuit configuration, the enable signal terminal
When the signal given to 2 is at the "L" level, the NMOS transistor N76 is always off. Therefore, even if the signal supplied to the input signal terminal 1 changes to "H" level, the signal supplied to the enable signal terminal 2 becomes "L".
As long as the level is at the level, a leak current cannot flow from the output terminal 8 to the ground terminal 7.

The embodiment of the present invention is not limited to the tri-state output circuit as described in the text, and the same effect can be obtained even when used in a normal push-pull output circuit. The NMOS in FIGS. 1 and 2
The transistors N11, N12 and the NMOS transistors N11, N12, N74 in FIG. 7 are for preventing the possibility that other elements are destroyed by applying a voltage of 5V to the output terminal 8, and the other elements are destroyed at 5V. If there is no fear, even if it is deleted, there is no hindrance to the effect of suppressing the leak current.

[0039]

As described above, according to the output circuit of the present invention, the potential of the power supply terminal (for example, 3 V) is applied to the output terminal.
Even if a higher potential (for example, 5 V) is input from an external circuit or the like, the well in the floating state rises to near the high potential input from the external circuit or the like, so that the second transistor formed in this well becomes The transistor is turned off and a high potential input from an external circuit or the like is not applied to the first transistor. Further, since the well in the floating state, which is the substrate of the second transistor, is not connected to the power supply terminal, it is possible to prevent a leak current from flowing from the output terminal to the power supply terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a relationship between a voltage applied to an output terminal 8 and a leakage current according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between a voltage applied to a signal input terminal and a voltage of each unit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between a voltage applied to an output terminal 8 and a leakage current according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between a voltage applied to a signal input terminal and a voltage of each unit according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing an output circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional output circuit.

[Explanation of symbols]

1… Signal input terminal, 2… Enable signal input terminal, 3
... Inverter, 4 ... 2-input NAND circuit, 5 ... 2-input NOR
Circuit, 6 ... power supply terminal to which a power supply potential of 3 V is applied, 7 ... ground terminal to which a ground potential is applied, 8 ... output terminal, B1 ... N well in a floating state, P1, P12, P13, P14,
P25: PMOS transistor, N1, N11, N12, N7
4, N75, N76 ... NMOS transistor

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-8-65135 (JP, A) JP-A-7-202678 (JP, A) JP-A-7-297701 (JP, A) JP-A 8- 8715 (JP, A) JP-A-6-216752 (JP, A) JP-A-8-237102 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/00

Claims (16)

(57) [Claims] A gate connected to a first node; a gate connected to the first node;
One terminal connected to a power supply terminal of the first, the other terminal connected to the second node, a first MOS transistor having a substrate terminal connected to the first power supply terminal, the first MOS transistor A second terminal having a gate connected to the node, one terminal connected to the second node, the other terminal connected to the output terminal, and a substrate terminal connected to the third node in a floating state; Two MOS transistors; a gate connected to the first power supply terminal; one terminal connected to the first node; another terminal connected to the output terminal; And a third MOS transistor having a substrate terminal connected to the output terminal. 2. A gate connected to the first node, one terminal connected to the second node, another terminal connected to the third node, and a third node connected to the third node. 2. The output circuit according to claim 1, further comprising a fourth MOS transistor having a substrate terminal connected to the output terminal. 3. A gate connected to the first power supply terminal, one terminal connected to the third node, another terminal connected to the output terminal, and a third terminal connected to the third node. 2. The output circuit according to claim 1, further comprising a fourth MOS transistor having a connected substrate terminal. 4. A gate connected to the first node, one terminal connected to the second node, another terminal connected to the third node, and a third node connected to the third node. A fourth MOS transistor having a substrate terminal connected to the first power supply terminal, a gate connected to the first power supply terminal, one terminal connected to the third node, and the other connected to the output terminal. 2. The output circuit according to claim 1, further comprising: a first terminal; and a fifth MOS transistor having a substrate terminal connected to the third node. A first input signal terminal supplied with a first input signal; a second input signal terminal supplied with a second input signal; a gate connected to the first node; With the potential of
A first MOS transistor having one terminal connected to the first power supply terminal, the other terminal connected to the second node, and a substrate terminal connected to the first power supply terminal having the first potential; A transistor, a gate connected to the first node, one terminal connected to the second node, another terminal connected to the output terminal, and a third node connected to a floating state. A second MOS transistor having a substrate terminal, a gate connected to a first power supply terminal having the first potential, one terminal connected to the first node, and a connection to the output terminal. The other terminal, a third MOS transistor having a substrate terminal connected to the third node, a gate connected to the first input terminal, and one connected to the first node. Terminal and the other connected to the fourth node A fourth MOS transistor having a terminal, a substrate terminal connected to a second power supply terminal having a second potential, a gate connected to the second input terminal, and a connection to the fourth node. One terminal, a second terminal connected to a second power terminal having the second potential, and a substrate terminal connected to a second power terminal having the second potential. An output circuit having five MOS transistors. 6. A gate connected to the first node, one terminal connected to a second node, another terminal connected to the third node, and a gate connected to the third node. 6. The output circuit according to claim 5, further comprising a sixth MOS transistor having a connected substrate terminal. 7. A gate connected to a first power supply terminal having the first potential, one terminal connected to the third node, and another terminal connected to the output terminal. A sixth MO having a substrate terminal connected to the third node
6. The output circuit according to claim 5, comprising an S transistor. 8. A gate connected to the first node, one terminal connected to the second node, another terminal connected to the third node, and a third node connected to the third node. A sixth MOS transistor having a substrate terminal connected to: a gate connected to a first power supply terminal having the first potential; one terminal connected to the third node; 6. The output circuit according to claim 5, further comprising: a seventh MOS transistor having another terminal connected to the terminal and a substrate terminal connected to the third node. 9. A gate connected to the first node, the gate connected to the first node.
A first MOS transistor having one terminal connected to a power supply terminal of the first MOS transistor and the other terminal connected to a second node; a gate connected to the first node; and a second node connected to the second node. A second MOS transistor formed in a floating well having one terminal connected thereto and the other terminal connected to the output terminal; a gate connected to the first power supply terminal; An output circuit comprising: one terminal connected to a first node; and a third MOS transistor formed in the floating well having the other terminal connected to the output terminal. . 10. The floating state having a gate connected to the first node, one terminal connected to the second node, and the other terminal connected to the well in the floating state. 10. The output circuit according to claim 9, further comprising a fourth MOS transistor formed in the well. 11. The floating well having a gate connected to the first power supply terminal, one terminal connected to the well in the floating state, and another terminal connected to the output terminal. 10. The output circuit according to claim 9, further comprising a fourth MOS transistor formed therein. 12. The floating state having a gate connected to the first node, one terminal connected to the second node, and another terminal connected to the floating well. A fourth MOS transistor formed in the well, a gate connected to the first power supply terminal, one terminal connected to the well in the floating state, and another terminal connected to the output terminal 10. The output circuit according to claim 9, further comprising: a fifth MOS transistor formed in the floating well having: 13. A first input signal terminal to which a first input signal is applied, a second input signal terminal to which a second input signal is applied, a gate connected to a first node, With the potential of
A first MOS transistor having one terminal connected to the first power supply terminal and the other terminal connected to the second node; a gate connected to the first node; A second MOS transistor formed in the floating well having one terminal connected to the node and the other terminal connected to the output terminal; a first power supply having the first potential A third MOS transistor formed in the floating well having a gate connected to a terminal, one terminal connected to the first node, and the other terminal connected to the output terminal; A fourth MOS transistor having a gate connected to the first input terminal, one terminal connected to the first node, and the other terminal connected to a fourth node; The second input A fifth MOS transistor having a gate connected to a terminal, one terminal connected to the fourth node, and another terminal connected to a second power supply terminal having the second potential. An output circuit, comprising: 14. The floating state having a gate connected to the first node, one terminal connected to a second node, and the other terminal connected in the floating well. 14. The output circuit according to claim 13, further comprising a sixth MOS transistor formed in the well. 15. A gate connected to a first power supply terminal having the first potential, one terminal connected to the well in the floating state, and another terminal connected to the output terminal. 14. The output circuit according to claim 13, further comprising a sixth MOS transistor formed in the floating well having the sixth MOS transistor. 16. The floating state having a gate connected to the first node, one terminal connected to the second node, and the other terminal connected to the well in the floating state. A sixth MOS transistor formed in the well, and a sixth MOS transistor having the first potential.
A seventh terminal formed in the floating well having a gate connected to the first power supply terminal, one terminal connected to the floating well, and the other terminal connected to the output terminal; 14. The output circuit according to claim 13, comprising: