JP3338735B2 - Drive circuit for liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display, and more particularly, to a poly-silicon TFT (Thi).
The present invention relates to a drive circuit of an active matrix type liquid crystal display device having a thin film transistor matrix array (hereinafter, referred to as a TFT array) using an n film transistor.

[0002]

2. Description of the Related Art FIG. 5 shows a previously proposed Japanese Patent Application No. 4-330.
No. 222, a driving circuit of a polysilicon type active matrix type liquid crystal display device, in which 31 is a timing generation circuit, 32 is an M-stage N-bit shift register, 33 is an M-stage N-bit data latch circuit, 34 is an M-stage N-bit digital comparator, 35 is an N-bit counter, 36 level shifter, 37 is an analog switch,
Reference numeral 8 denotes a conversion analog signal generation circuit, 39 denotes a TFT liquid crystal matrix circuit, 40 denotes a TFT, 41 denotes a pixel, 42 denotes a horizontal line, and 43 denotes a scanning driver.

The driving circuit of this conventional liquid crystal display device has a series of N-bit pixel data in a driving circuit of an active matrix type liquid crystal display device for driving the liquid crystal display device by a matrix array composed of thin film transistors made of polysilicon. Digital video signal consisting of
A shift register 32 for sequentially storing each line, a latch circuit 33 for holding one line of digital video signals sequentially stored in the shift register 32 for one horizontal period,
Each pixel data constituting one line of digital video signal output from the latch circuit 33 is converted into an N-ary counter 35.
A digital comparator 34 which compares the data value with the output data value and generates a coincidence pulse at the time of coincidence; a conversion analog signal generation circuit 38 which generates an analog ramp waveform between a white level and a black level for each horizontal period; An analog switch 37 that samples the analog ramp waveform from the conversion analog signal generation circuit 38 using the coincidence pulse and generates an analog voltage having a level corresponding to the coincidence pulse generation timing; The sampling output is supplied to a thin film transistor corresponding to a predetermined pixel on a selected horizontal line of the matrix array, and a predetermined analog video signal is supplied to a predetermined pixel of the liquid crystal display device.

In the above-described driving circuit of the liquid crystal display device, the conversion analog signal generating circuit 38 for generating the analog ramp waveform for each horizontal cycle is provided with the voltage and transmittance of the liquid crystal with respect to the analog ramp waveform. A gamma correction circuit for performing gamma correction of a video signal according to characteristics is provided.

[0005]

As described above, in a conventional driving circuit of a liquid crystal display device, a shift register circuit, a latch circuit, and a digital comparator are constituted by digital circuits. Therefore, when a driver-integrated liquid crystal display device is realized by polysilicon TFTs, it has been difficult in terms of manufacturing yield. This is because the larger the circuit becomes, the higher the probability that one defect causes the entire circuit to be defective. As means for solving these problems, various functions for providing redundancy to the circuit have been conventionally proposed. However, a circuit for that purpose is required, and there is a problem that the entire circuit scale is increased.

The present invention has been made in view of such circumstances, and is provided with a circuit for converting a digital video signal from a time series order to a data order, and supplying an address corresponding to data to a driver on the TFT side. It is an object of the present invention to propose a driving circuit for a liquid crystal display device in which a TFT driver is simplified.

[0007]

According to the present invention, there is provided a driving circuit for an active matrix type liquid crystal display device for driving a liquid crystal display device by using a matrix array composed of thin film transistors made of polysilicon. A reordering circuit for converting a digital video signal consisting of a series of bits of pixel data from its chronological order to data order, that is, to an order according to the size of data;
An address decoder circuit for driving a sampling switch circuit for selecting a source line of a matrix array based on the address data output from the rearranging circuit;
A circuit for performing A-conversion and supplying the signal to the signal line of the sampling analog switch, and supplying a predetermined analog video signal to a predetermined pixel in a selected horizontal line of the matrix array.

A dummy address is added to the address data output from the rearrangement circuit in accordance with the amount of change in the video data, and during this dummy address period, the video data of the next address is output. , A sampling time for the sampling analog switch is secured.

[0009]

In the driving circuit of the liquid crystal display device of the present invention having the above-mentioned configuration, the digital video signal in the time series composed of a series of bits of pixel data supplied from the outside is rearranged in the data order by the rearranging circuit. . The order of rearrangement is from the smaller data (corresponding to the black level of the video) or the larger data (corresponding to the white level of the video). Since this data includes image-related data (video data) and time-series elements, that is, address information, when outputting in the data order, the address information is also output at the same time. The address information (data) is supplied to an address decoder circuit, and the video data is supplied to a D / A conversion circuit. The address decoder circuit has a function of turning on a gate of an analog switch for selecting a source line of a matrix array based on address data. On the other hand, D /
The A-converted video signal is connected to the source side of the analog switch. When the analog switch is turned on by the address decoder, the video signal is connected to the source side of the matrix array, thereby outputting the video signal to the source side of the matrix array. Is done. Here, if a gate line of the matrix array is selected in advance, a video signal is provided to the TFT pixel. The configuration of the signal driver is a shift register circuit, a latch circuit,
In addition, since the digital comparator circuit is eliminated, and this part is replaced with the address decoder circuit, the circuit scale can be reduced, which is very simple. Therefore, the active matrix TF integrated with a polysilicon type driver
This is convenient when producing a T liquid crystal display device because the circuit scale is small.

Also, a dummy address is added to the address data output from the rearranging circuit in accordance with the amount of change in the video data, so that the video data of the next address is output during the dummy address data period. Therefore, the sampling time in the sampling analog switch can be secured.

[0011]

Embodiments will be described below with reference to the drawings. Here, FIG. 1 is a block diagram for explaining one embodiment of a driving circuit of a liquid crystal display device according to the present invention.
1 is a reordering circuit, 2 is a D / A converter, 3 is a buffer,
4 is a driver-integrated polysilicon TFT active matrix circuit, 5 is a TFT liquid crystal matrix circuit, 6 is a gate driver, 7 is a source driver, 8 is a decoder circuit,
9 is a sampling gate control circuit, 10a is a level shifter circuit, and 10b is a sampling gate circuit.

A digital video signal SVd composed of a series of bits of pixel data supplied from the outside in chronological order is
It is input to the rearrangement circuit 1 in synchronization with CLK. The rearranging circuit 1 is constituted by a digital circuit. SVd
.. M correspond to data of the number M of pixels in the horizontal direction of the TFT liquid crystal matrix circuit 5, and 1, 2, 3,.
, And are input to the rearranging circuit 1 in the order of position in the horizontal direction, that is, in the order of addresses. The horizontal synchronizing signal HD is a horizontal synchronizing signal input every M data. The rearrangement circuit 1 performs a conversion as shown in FIGS. 2 (a) and 2 (b). In the figure, for simplicity,
The video data inputs arranged in the order of 15 addresses are rearranged and arranged in ascending order of data, and address information is output in that order (1, 9, 10, 11,... 3). When the same video data is present in a plurality of addresses, the same video data is output by the number of addresses of the same video data.

FIG. 3 is a block diagram for explaining an embodiment of the rearrangement circuit. In the figure, 11 is an M-stage N-bit shift register, 12 is an M-stage N-bit data latch, and 13 is an M-stage N-bit latch. A digital comparator, 14 is an M-stage 1-bit latch shift register, 15 is an M-stage (L + N) bit shift register, 16 is an M-stage (L + N) bit latch shift register, 17 is a 2 n power counter, and 18 is an M counter. .

A digital video signal synchronized with a clock (CLK) is input to an M-stage N-bit shift register 11. At the point in time when one horizontal synchronization data is input, all data is stored in the M-stage N-bit data latch 12 by the horizontal synchronization signal HD. Here, one digital data is N-bit data. The data latched by the M-stage N-bit data latch circuit 12 is input to the M-stage N-bit digital comparator 13 and is supplied to the 2 n-th power counter 1.
7 are sequentially compared.

The 2 to the n-th power counter 17 is an M counter 18
The M counter 18 is counted up by CLKA. CLKA is used as a shift clock of the M-stage 1-bit latch shift register 14. The output of the M-stage N-bit digital comparator 13 indicates the result of comparison with the output of the 2 to the n-th power counter 17, and if they match, one bit is output for each data. This is latched by the M-stage 1-bit latch shift register 14.

That is, every time the 2 n counter 17 counts up, the matched result is stored in the M-stage 1-bit latch shift register 14. By repeating a series of operations to the power of 2 n, the comparison of M pieces of video data ends. On the other hand, the matched data stored in the M-stage 1-bit latch shift register 14 is output by CLKA by the shift register in the M-stage 1-bit latch shift register 14, and this signal is output by the M-stage (L + N) bits. This is a shift clock for the shift register 15.

The M-stage (L + N) bit shift register 1
In 5, the shift register is written only when they match. At this time, there are two data to be written to the M-stage (L + N) bit shift register 15, one is the address data which is the output data of the M counter 18, and the other is the content of the video data at that time. Is the output of the 2 to the n-th power counter 17. L is the number of bits to represent M, and has a relationship of M = 2 to the L-th power. For example, if the number M of SVd data is 256 pieces, this is true. In the above operation, the M-stage (L + N) bit shift register 15 stores the video data in the order of addresses input to the M-stage N-bit shift register 11 in the data order. Once in the M-stage (L + N) bit latch shift register 16, the M-stage 1-bit latch shift register 14
Is latched and output while shifting by CLK, the data is output at the data transfer rate of SVd.

Referring to FIG . 1, a driving circuit according to the present invention will be described.
The operation will be described. In FIG. 1, the sorting circuit 1
The output video data is input to the D / A conversion circuit 2,
Driver-integrated polysilicon TF via buffer 3
Input to the T active matrix circuit 4
Connected to the gate circuit 11. As described above,
Data is organized in the order of the data size.
It is a shape. On the other hand, SADR address data is
Integrated polysilicon TFT active matrix circuit 4
Is input to the decoder circuit 8 in the
Pulse on the output line indicated by the data content.
Occurs.

This pulse is supplied to the sampling gate control circuit.
Is latched in the path 9 and its output is
10a, the gate of the sampling gate circuit 10b
Supply to In the sampling gate control circuit 9
Is reset every one horizontal cycle by the input of the horizontal synchronization signal HD.
Since it is set, the sampling gate time
In the path 10b, all the gates are turned on, and SA is the TFT liquid crystal matrix.
Connected to the source line of the ricks circuit 5 and thereafter
Means that the value of SA is supplied to the source line.

That is, the sampling gate control circuit 9
At the time when the output from the decoder circuit 8 occurs,
Operation of turning off the gate of the sampling gate circuit 10b
In the source line, the SA
Is supplied by the gate driver 6.
T of the TFT liquid crystal matrix circuit 5 of the selected line
A video signal is supplied to the FT, and an image can be formed.

The above operation is shown in FIGS.
FIG. 4A shows an SADR signal, FIG. 4B shows video data,
FIG. 4C shows the order of data size by the rearrangement circuit.
Video signal SA after rearranged and D / A converted, FIG.
4 (d) shows the source line address data Mc.
FIG. 4E shows a source line address.
FIG. 4F shows a sampling pulse in the data Mz.
Video signal SA passed through sampling analog switch
The subsequent charging voltage waveforms are shown. In FIG. 4, T
In the FT liquid crystal matrix circuit 5, there is a feature having a source line.
Indicates the sampling pulse at a fixed location, and the SA at this time
Is written to the liquid crystal pixels.

[0022]

As is apparent from the above description, the present invention
According to the above, the configuration of the signal driver is more
It's always easy. Therefore, the TFT matrix array
A, scan driver, sampling analog switch,
Monolithic bell shifter and address decoder
This is convenient for In addition, the video signal should be stepped
Because the sharp part of the video signal is suppressed,
Ring analog switch speed (sampling time)
It may be less. In addition, the speed of the address decoder is insufficient.
If so, multiplexing may be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of a driving circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a diagram illustrating a state of conversion by a rearrangement circuit in FIG. 1;

FIG. 3 is a block diagram illustrating an embodiment of a rearrangement circuit according to the present invention.

FIG. 4 is video data in a source driver according to the present invention .
It is a figure showing the example of conversion.

FIG. 5 is a block diagram of a driving circuit of a conventional liquid crystal display device.
is there.

[Explanation of symbols]

Reference Signs List 1 rearranging circuit 2 D / A converter 3 buffer 4 driver-integrated polysilicon TFT active matrix circuit 5 TFT liquid crystal 6 gate driver 7 source driver 8 decoder circuit 9 sampling gate control circuit 10a level shifter circuit 10b sampling gate circuit 11 M stage N Bit shift register 12 M-stage N-bit data latch circuit 13 M-stage N-bit digital comparator 14 M-stage N-bit latch shift register 15 M-stage (L + N) bit shift register 16 M-stage (L + N) bit latch shift register 172 n Counter 18 M counter 19 M counter 202 2 n power counter 21 Decoder circuit 22 to 24 M-stage 1-bit latch shift register 25 to 27 M-stage (M + N) bit latch shift register 28 CHIPLEXER 29 Dummy address circuit

Claims (1)

(57) [Claims] 1. A driving circuit of an active matrix type liquid crystal display device for driving a liquid crystal display device by means of a matrix array composed of thin film transistors made of polysilicon converts a digital video signal consisting of a series of bits of pixel data from a time series order. A rearrangement circuit for converting the digital video signal into an order according to the data size, and an address decoder for driving a sampling switch circuit for selecting a source line of a matrix array based on the address data output from the rearrangement circuit Circuit and video data output from the rearrangement circuit
/ A conversion, and supplies a predetermined analog video signal to a predetermined pixel on a selected horizontal line of the matrix array, wherein the address data is A drive circuit for a liquid crystal display device, which is an address assigned in a time series of a digital video signal and is data indicating a position of a source line of a matrix array.