JP3336623B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for burst-transferring data through a shared bus.

[0002]

2. Description of the Related Art When data is mutually transferred between a plurality of master devices and a plurality of slave devices, those devices are connected to a shared bus, and the shared bus is used by time division multiplexing. A so-called shared bus method is employed. FIG. 11 shows a configuration of such a shared bus system. In FIG. 11, 1 is a master device, 2 is a slave device, and 3 is a shared bus.

In recent years, as in image processing, there has been an increasing number of applications that require a large amount of data to be transferred at high speed and processed in real time. One measure is to increase the bus width of the shared bus 3. If the bus width of the shared bus 3 is increased, it goes without saying that the amount of data that can be carried per unit time is increased.

However, since only the shared bus 3 cannot occupy a very large area on the printed circuit board, the area is restricted first in terms of area. The shared bus 3 has an ASIC
(Application Specific IC), but the number of pins that can be provided there is still limited by the type and size of the ASIC package. Due to such circumstances, there is a limit in increasing the bus width of the shared bus 3.

Therefore, as another measure, it has been considered that data transfer is performed by burst transfer instead of single transfer. FIG. 12 illustrates single transfer and burst transfer. In FIG. 12, T is a time axis, 5 is an address designation time, 6 is a data transfer time, and 7 is an arbitration time.

FIG. 12A is a diagram for explaining the single transfer. In the single transfer, prior to once transferring data of the number of bits corresponding to the bus width, an address which is a destination of the data is designated. . And after sending,
After the bus is arbitrated and the bus is secured again, the next data transfer is performed. Therefore, the time required to transfer data of the number of bits corresponding to the bus width once is the sum of the address designation time 5, the data transfer time 6, and the arbitration time 7.

FIG. 12B is a diagram for explaining the burst transfer. In the burst transfer, after an address is specified, data of the number of bits corresponding to the bus width is continuously transferred several times with the address as a head position. The number of times (burst cycle number) is predetermined to one (eg, only in four cycles), or one is selected from several predetermined ones (eg, 4 cycles, 8 cycles, 16 cycles and 3
One of them, and select 8 cycles from them). FIG. 12B shows an example of a case where data is transferred four times consecutively (four cycles). Arbitration for the next transfer is performed after that. In the burst transfer, the number of times of addressing and arbitration is reduced, so that the time spent for the addressing and arbitration is reduced, and data is transmitted at high speed.

FIG. 13 is a diagram showing a conventional data transfer method performed via a shared bus. Reference numerals correspond to those in FIG. 11, 1-1 is a master device, 1-2 is a transfer control circuit, 2-1 is a slave device, 2-2 is a transfer control circuit, 4 is an arrow, and H _{1 to} H ₄ are transfer. It is a block. The master device 1-1 is, for example, a CPU or a DMA (Direct Memory Access) controller, and the slave device 2-1 is, for example, a memory. "0", "1",... "F" described in the master device 1-1 and the slave device 2-1 each represent a 1-byte data address.

In the conventional burst transfer, the data width is fixed to the data width of the shared bus 3 (that is, the number of physical signal lines of the shared bus 3), and both the port width of the master device 1 and the port width of the slave device 2 are set. Must be equal to the data width of the shared bus 3. In the case of FIG. 13, since the shared bus 3 has a data width of 4 bytes (32 bits), the master device 1 and the slave device 2 have a port width of 4 bytes.

Assuming that the number of burst cycles is 4, at the time of burst transfer, a designated transfer start address (FIG. 12)
From the address specified by the address specification time 5 in (b)), four consecutive bytes are continuously transferred as one transfer block. In FIG. 13, the transfer start address is “0”, and the transfer blocks H _{1 to} H ₄ each having 4 bytes are transferred from the slave device 2 as indicated by an arrow 4.
(Write operation). “0” to “F” described in the slave device 2-1 indicate the transferred result. Note that the transfer control circuits 1-2 and 2-2
This is a circuit for exchanging various control signals (eg, a burst cycle signal, an acknowledge signal) required at the time of burst transfer.

Conventional documents relating to the above-described data transfer method include, for example, Japanese Patent Application Laid-Open Nos. 56-110125, 57-64834, 64-36147, and 2 -253362, JP-A-3-135647 and the like.

[0012]

[Problems to be solved by the invention]

(Problem) However, in the conventional data transfer method,
There is a problem that burst transfer can be performed only when the condition that the port width of the master device, the port width of the slave device, and the bus width of the shared bus are all equal is satisfied.

(Explanation of Problems) As the number of master devices and slave devices connected to the shared bus increases, it would be very convenient if a device whose port width is not equal to the bus width of the shared bus can be connected. Requests have been issued. However, the conventional data transfer method cannot meet such a demand.

An object of the present invention is to enable burst transfer even if the port widths of the master device and the slave device are different from each other, as long as the port width is smaller than the bus width of the shared bus. Is what you do.

[0015]

According to the present invention, there is provided a master unit connected via a shared bus.
Data between the device and the slave device by burst transfer
In the data transfer method for transferring
The data written to the register cell is arranged in a column format.
Data can be shifted in the row and column directions,
The end in the row direction exchanges data with the master device
Connected to the master port, and the column ends are shared
First transfer interface connected to a bus port
Master device with buffer and register cells in a matrix
And the data written in the register cell is
It is possible to shift freely in the direction
End exchanges data with the slave device
It is connected to the slave port, and the end in the column direction is the shared bus port.
Second transfer interface buffer connected to the
And a slave device having a first transfer interface.
Interface buffer between the master device
Data transfer or the second transfer interface
Buffer transfers data with the slave device.
When receiving, give and receive while shifting in the row direction,
Transfer data to / from the shared bus via the shared bus port
When performing a shift in the column direction every burst cycle.
I decided to give and receive.

[0016]

When the width of the shared bus port of the transfer interface buffer is smaller than the bus width of the shared bus, the shared bus port is packed into one of the lower address side and the upper address side of the shared bus. Connected.

[0018]

[Operation] In a data transfer method in which a master device or a slave device is connected to a shared bus and data is transferred by burst transfer, a transfer interface buffer in which register cells are arranged in a matrix is provided in the master device or the slave device. The data written in the register cell can be freely shifted in the row direction and the column direction. When exchanging data with the shared bus, a shift in the column direction is performed every burst cycle. When data is exchanged with a master device or a slave device, a shift in the row direction is performed. As a result, data at consecutive addresses can be arranged in the column direction of the transfer interface buffer with an arbitrary byte width equal to the transfer destination port width. Therefore, it is possible to perform burst transfer even with a partner having a different port width.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the data transfer system of the present invention. Reference numerals correspond to those in FIG.
3,2-3 transfer interface buffer, 8 master port, 9, 10 shared bus port, 11 slave ports, 12 and 13 arrows, H ₅ to H ₈ is a transfer block.

In the present invention, the transfer interface buffer 1-3 is provided inside the master device 1. And
Data exchange with the master device 1-1 is performed via the master port 8, and data exchange with the shared bus 3 is performed via the shared bus port 9. Similarly, a transfer interface buffer 2-3 is provided inside the slave device 2, and data exchange with the slave device 2-1 is performed via the slave port 11, and data exchange with the shared bus 3 is shared. This is performed via the bus port 10.

The port width of the master port 8 is made equal to the port width of the slave port 11, and in the example of FIG.
Bytes. However, the port width of the shared bus port 9 (this is the port width of the master device 1) and the port width of the shared bus port 10 (this is the port width of the slave device 2)
Is different. In the example of FIG. 1, the port width of the master device 1 is 4 bytes, and the port width of the slave device 2 is 2 bytes. The bus width of the shared bus 3 is 4 bytes or more, which is the larger port width. Each of the shared bus ports 9 and 10 is connected to one of the bus widths of the shared bus 3 (for example, an address). (Lower side).

FIG. 2 is a diagram showing the configuration of the transfer interface buffer 1-3. The reference numerals correspond to those in FIG. 1; 14-1 to 14-16 are register cells, 15 is a right data path, 16 is an upper data path, 17 is a left data path, and 18 is a lower data path. Each register cell can record one byte of data, and each data path can transfer one byte of data. In this example, the matrix is configured to be a 4 × 4 matrix, and an end in the row direction of the matrix configuration is connected to the master port 8, and an end in the column direction is connected to the shared bus port 9.

This transfer interface buffer 1-
3, the 4-byte data can be simultaneously shifted vertically or horizontally (transfer interface buffer 2-3).
Is configured as 2 × 4). The shift is performed in accordance with a command from the transfer control circuit 1-2 in FIG. 1 while taking timing with a clock signal.

For example, the master port 8
4 sent to register cells 14-1 to 14-4 from
The byte data is transferred to the register cell 14- at the next clock.
It is shifted to 5-14-8, and thereafter shifted right by one step at every clock. Conversely, when sending data from the transfer interface buffer 1-3 to the master port 8, the shift direction is changed from right to left, and sent from the register cells 14-1 to 14-4 to the master port 8. Also, the shift direction is changed from left to right, and the register cell 1
From 4-13 to 14-16, the data can be sent to the master port 8 through the respective right data paths 15. Up-down shifting in the transfer interface buffer 1-3 and transfer of data with the shared bus port 9 are performed in the same manner.

FIG. 3 is a diagram showing a configuration of a register cell which is a component of the transfer interface buffer.
Reference numerals correspond to those in FIG. 2, 14 is a register cell, 19
22 is an enable control signal, 24 is a flip-flop, 25 is a selector, 26, 28, 29, and 30 are control gates, and S is a select signal. The enable control signal and the select signal are transmitted to the transfer control circuit 1-2 (2-
Supplied from 2). Each control gate is turned on when the enable control signal is low (L), and passes data. The selector 25 selects only one of the data of the plurality of input terminals (0, 1, 2) and sends it to the flip-flop 24. The flip-flop 24 is a flip-flop capable of recording 1-byte data.

FIG. 4 is a diagram showing a relationship between a data flow in the register cell 14 and a control signal. The items (a) to (d) show the types of data flow that can be performed by the register cell 14. For example, in the case of “A”, it is a case where data is to flow from upper to lower (that is, upper data path 16 → lower data path 18). At this time, the selector 25 selects the input terminal of “1” connected to the upper data path 16, and data from the upper data path 16 is first sent to the flip-flop 24. In the case of “A”, only the enable control signal 21 is low (L) among the enable control signals, so that only the control gate 29 is turned on among the control gates. As a result, the data of the flip-flop 24 is sent out to the lower data path 18 through the control gate 29, and the transmission of the data from the upper side to the lower side is successfully achieved.

Next, the case of “d” (right → left) in FIG. 4 will be described. Since the input terminal of “2” is selected by the selector 25, the right data path 15 connected thereto is selected.
Is sent to the flip-flop 24. On the other hand, since the enable control signals 19 and 21 are made low, the data of the flip-flop 24 is
→ Control gate 28 → Sent to left data path 17, and data transmission from right to left is achieved.

It is to be noted that the control gate 28 may be omitted in some cases and only the wiring may be used. When this is omitted, it is worried that, in the case of "c" in FIG. 4 where data is input from the left data path 17, the data is transferred to the lower register cell (not shown) via the lower data path 18. Is not transmitted. However, there is no such concern, as described below. When data is input from the left data path 17, the data is transmitted to the selector 25 (to the “0” input terminal) and the lower data path 1
8 is also told. Since the lower data path 18 is the upper data path 16 for the lower register cell,
The data is transmitted to the input terminal “1” of the selector 25 (not shown) of the lower register cell. However, "C"
In the case of, "0" is simultaneously selected in the selector 25, so that the data transmitted to the lower stage is not selected,
It disappears there. Therefore, there is no such concern.

(Specific operation example of transfer) Next, specific operation when data is transferred from the master device 1 having a 4-byte port width to the slave device 2 having a 2-byte port width as shown in FIG. An example will be described. It is assumed that each of the shared bus ports is connected to the lower portion of the address of the bus width of the shared bus 3. Assuming that burst transfer with a burst cycle number of 4 is adopted, the transfer interface buffer 1-3 sets the register cell to 4 (port width) ×
4 (the number of burst cycles). On the other hand, the transfer interface buffer 2
Reference numeral -3 denotes a configuration in which register cells are arranged in a matrix of register cells of 2 (port width) × 4 (burst cycle number). Now, from 0 to F of the master device 1-1,
The data at the consecutive addresses up to this point is to be transferred to the slave device 2.

When data is transferred from a device having a large port width to a device having a small port width, all data in the transfer interface buffer of the transfer source is transferred in one burst transfer. It has to do some burst transfers because it can't fit. In the example of FIG. 1, since the port width of the transfer source is twice the port width of the transfer destination, in order to transfer all the data in the transfer interface buffer 1-3, two burst transfers must be performed. No. The transfer process is shown in FIG.
It will be explained by.

FIG. 5 is a diagram showing a transfer process from a device having a large port width (4 bytes) to a device having a small port width (2 bytes). FIG. 5A shows the first half of the process, and FIG.
Indicates the latter half of the process. FIG. 5B shows a preparation process for executing the latter half of the process. It should be noted that the situation of the data shown in FIG. 1 is the situation in the first half of the transfer process, and the first half of the transfer process will be described with reference to this.

[First Half Transfer Process] From the master device 1-1 to the transfer interface buffer 1-3 First, four bytes of continuous data of addresses 0 to 3 are transferred from the master device 1-1 to the transfer interface buffer 1-3. Sent to Each time the transfer interface buffer 1-3 receives the next data, it shifts the previously received 4-byte data to the right (operation "c" in FIG. 4). Eventually, the data from address 0 to address F is stored as shown in the transfer interface buffer 1-3 in FIG. 1 (or FIG. 5A). Master device 1-1 and transfer interface buffer 1
3 can be performed independently of the shared bus 3, the operation clock in this case is:
It does not have to be synchronized with the operation clock of the shared bus 3 (the frequency may be different). In the case described later, the situation is the same, so the situation is the same.

Transfer interface buffer 1-3
→ To the shared bus 3 Next, the data is transmitted to the shared bus 3 by burst transfer. The data is transmitted in a direction (vertical direction) perpendicular to the shift direction (lateral direction) when data is received from the master device 1-1. ), And 4 bytes are transmitted from the shared bus port 9 as one transfer block. As a result, the transfer block H ₅ of the data initially transmitted, the 0
It is data of addresses 4, 4, 8, and C, and is not data of continuous addresses. The reason is that what is received after shifting in the left-right direction is sent out after shifting in the vertical direction. Since the number of burst cycles is four, the data transfer blocks H _{6 to} H ₈ having the contents shown in FIG. 1 are transmitted three times thereafter, and are transferred in the direction of arrow 12. Data exchange between the transfer interface buffer 1-3 and the shared bus 3 is performed in synchronization with the operation clock of the shared bus 3. In the following case, the situation is the same, so that it is the same.

From the shared bus 3 to the transfer interface buffer 2-3 Of the transfer blocks H _{5 to} H ₈ transferred from the shared bus 3 as shown by the arrow 13 in FIG.
₅ is taken into the transfer interface buffer 2-3 via the shared bus port 10. However, since the shared bus port 10 has a port width of only 2 bytes and is connected to the lower portion of the bus width of the shared bus 3 and is connected, only the data of addresses 0 and 4 are fetched. When the next transfer block H ₆ is fetched,
The data of addresses 0 and 4 that have been fetched earlier are shifted upward. The same applies to the following. As a result, at the stage where the first burst transfer consisting of four cycles is completed, the transfer interface buffer 2 shown in FIG. 1 (or FIG.
Data of each address as shown in FIG.

Transfer interface buffer 2-3
→ To the slave device 2-1 In the transfer interface buffer 2-3, each time data is received from the shared bus 3,
The data is shifted in the direction perpendicular to the slave port 11
Send more. 4 because the number of burst cycles was 4
A byte is sent out, which is the master device 1-
It becomes the initial continuous 4 bytes (eg, addresses 0 to 3) that were at 1. These are stored in designated addresses in the slave device 2-1. Next, the data at addresses 4 to 7 in the transfer interface buffer 2-3 is shifted rightward (to the slave port 11 side) and stored in the slave device 2-1 in the same manner. Thus, the transfer of data at addresses 0 to 7, which is half of all data to be transferred, is completed.

[Preparation process for transfer in the latter half] When the transfer in the above section is completed, the slave device 2 as the transfer destination
The transfer control circuit 2-2 sends an acknowledge signal indicating its own port width (2 bytes) to the transfer control circuit 1-2 of the master device 1 which is the transfer source. The transfer source receiving this transfers the data at addresses 8 to F, which could not be transmitted this time, and therefore, as shown in FIG. Is shifted by two clocks toward the lower side of the address.

[Second half transfer process] In this way, as shown in FIG. 5C, the second burst transfer is performed through the same processes as in the first half transfer. In this way, all data of the master device 1 to be transferred is transferred to the slave device 2-1.

As described above, according to the present invention, the device corresponding to a small port width (2 bytes in the above example) of the bus width is substantially used, and a device having a larger port width is used. Data can be burst transferred. FIG. 7 shows a general expression of a state transmitted to a transfer destination device (eg, a slave device) in the first burst transfer to a device having a small port width.

In FIG. 7, a is a transfer start address, N
Is the number of burst cycles, M is the transfer source port width, M ₁ is the transfer destination port width, n is an arbitrary number of burst cycles (1 ≦ n ≦ N), and m ₁ is the lower address of the port width M _1. Is an arbitrary number byte (1 ≦ m ₁ ≦ M ₁ ) counted from ( ₁ ). Data M ₁ byte sent in each burst cycle of the burst transfer is as follows. First time → a, a + N,..., A + (m ₁ -1) N,.
+ (M ₁ −1) N 2nd time → a + 1, a + N + 1,..., A + (m ₁ −1) N
+1,..., A + (M ₁ −1) N + 1 nth → a + (n−1), a + N + (n−1),.
_{+ (M 1 -1) N +} (n-1), ..., a + (M 1 -1)
N + (n−1) Nth time → a + (N−1), a + N + (N−1),.
_{+ (M 1 -1) N +} (N-1), ..., a + (M 1 -1)
The N + (N-1) first step burst transfer is completed, stored since the destination port width has only M ₁ byte, the hatched portion of the data (FIG. 7 of the difference between the port width M and the port width M ₁ Is not sent in the first burst transfer.

FIG. 6 is a diagram showing a transfer process from a device having a small port width (2 bytes) to a device having a large port width (4 bytes). However, it is assumed that the shared bus 3 has a bus width larger than a large port width (4 bytes). Each port is connected to one side (eg, lower address side) of the bus width of the shared bus 3. The burst cycle of the burst transfer is assumed to be 4. The example of FIG. 6 corresponds to the example of FIG. 1 in which data of the slave device 2-1 is burst-transferred to the master device 1-1. FIG. 6A shows the first half of the process, and FIG. 6C shows the second half of the process. FIG. 6B shows a preparation process for executing the latter half of the process.

In FIG. 6A, the slave device 2-1
After that, data of consecutive addresses are first sent to the transfer interface buffer 2-3 by 4 bytes (data of addresses 0 to 3) corresponding to the burst cycle number 4.
Next, the data sent to the transfer interface buffer 2-3 is shifted to the left, and at the same time, data of the next four consecutive addresses (addresses 4 to 7) are sent to the trace. As a result, the transfer interface buffer 2-3 having a port width of 2 bytes becomes full, and burst transfer is performed to the transfer interface buffer 1-3. In this case, the data is transmitted while being shifted in a direction perpendicular to the shift direction in which the data was received from the slave device 2-1. H ₁₀ is an example of a transport block sent in that way. The transfer interface buffer 1-3, which is the transfer destination, receives the data at the lower 2 bytes of the address of the port width. Each time a transfer block is received, it shifts upward.

FIG. 6B shows the process of shifting the data received in the first burst transfer by two bytes in a direction perpendicular to the direction of the shift performed when receiving the data. As a result, preparations for receiving a burst transfer from a transfer source having a port width of 2 bytes are completed. In such a state, the remaining data (data of addresses 8 to F)
In the second half of burst transfer by the same procedure. FIG. 6C shows this. Thus, all data of the slave device 2-1 has been transferred to the transfer interface buffer 1-3.
The transfer interface buffer 1-3 shifts in the direction perpendicular to the direction of the shift performed when data is received (in the direction of the thick arrow), and moves to the designated position of the master device 1-1 (see FIG. 1). Store.

The above description relates to the case where burst transfer is performed between devices having different port widths by using a part of the bus width. However, when performing the burst transfer between devices having the same port width and using the entire bus width, it is most difficult. Burst transfer is performed with high efficiency. FIG.
FIG. 3 is a diagram showing an example of burst transfer to a device having the same port width, and shows a state in which burst transfer of four cycles is performed between transfer interface buffers having a port width of 4 bytes.

FIG. 9 is a diagram showing a general expression of a state where data is sent to a transfer destination device in a burst transfer to a device having the same port width. The reference numerals correspond to those in FIG. Among the N burst cycles, the first burst → a, a + N,..., A + (m−1) N,.
(M−1) N 2nd → a + 1, a + N + 1,..., A + (m−1) N +
1,..., A + (M−1) × N + 1 nth → a + (n−1), a + N + (n−1),.
+ (M-1) N + (n-1), ..., a + (M-1) N +
(N-1) N-th → a + (N-1), a + N + (N-1),..., A
+ (M-1) N + (N-1), ..., a + (M-1) N +
Data of each address such as (N-1) is transferred. However,
1 ≦ n ≦ N and 1 ≦ m ≦ M.

FIG. 10 is a diagram showing a transfer process when the port width does not match the number of burst cycles. Numerals correspond to those of FIG. 1, H ₁₂ ~H ₁₅ is a transfer block.
Although the port width of the master device 1-1 is 2 bytes,
Even if the port width does not match the burst cycle number, as in the case where the burst transfer is performed with a burst cycle number of 4, the present invention can perform the burst transfer as described below. Here, as the transfer interface buffer 1-3, one configured in a 4 × 4 matrix is used.

In FIG. 10A, first, the master device 1
From -1, two-byte data is transmitted to the transfer interface buffer 1-3 four times. The portion with a dot indicates it. Next, as shown in FIG. 10 (b), the data transferred to the transfer interface buffer 1-3 is reduced by 2 bytes (in a direction perpendicular to the shift direction performed when the data was received). Shift only. Data is sent again from the master device 1-1 to the area vacated by this shift (FIG. 10).
(C)). This, because the data of the four cycles the number of burst cycles are aligned, as shown in FIG. 10 (d), they are divided into transport blocks H ₁₂ to H ₁₅ to the burst transfer. The transfer block is obtained by shifting in a direction perpendicular to the shift direction performed when the transfer interface buffer 1-3 receives data from the master device 1-1.

[0047]

As described above, according to the data transfer method of the present invention, the following effects can be obtained. When performing burst transfer between a master device and a slave device connected via a shared bus, if the bus width is equal to or less than the bus width of the shared bus, the devices have arbitrary port widths or have different port widths from each other. Burst transfer can be performed even between devices. Burst transfer can be performed even if the port width is different from the bus width of the shared bus. Therefore, an ASIC (Application Spec)
In the case of designing with ICs, the number of pins corresponding to the bus width is not restricted, and the number of pins can be reduced. In the transfer interface buffer, the data width transmitted in burst transfer is set to an arbitrary byte width by shifting in the direction (row direction) perpendicular to the shift direction (column direction) for transmitting data. When performing burst transfer between devices with different port widths,
The data width to be transferred can be easily adjusted to the smaller port width. That is, the bus sizing function is performed. Therefore, it is not necessary to provide a so-called bus sizing mechanism.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a data transfer method according to the present invention.

FIG. 2 is a diagram showing a configuration of a transfer interface buffer 1-3.

FIG. 3 is a diagram showing a configuration of a register cell which is a component of a transfer interface buffer;

FIG. 4 is a diagram showing a relationship between a data flow in a register cell and a control signal.

FIG. 5 is a diagram showing a transfer process from a device having a large port width (4 bytes) to a device having a small port width (2 bytes).

FIG. 6 is a diagram showing a transfer process from a device having a small port width (2 bytes) to a device having a large port width (4 bytes).

FIG. 7 is a diagram of a general expression of a state transmitted to a destination device in an initial burst transfer to a device having a small port width.

FIG. 8 shows one example of burst transfer to a device having the same port width.
Figure showing an example

FIG. 9 shows a burst transfer to a device having the same port width;
Diagram of the general representation of the state sent to the destination device

FIG. 10 is a diagram showing a transfer process when the port width does not match the number of burst cycles.

FIG. 11 is a configuration diagram of a shared bus system.

FIG. 12 illustrates single transfer and burst transfer.

FIG. 13 is a diagram showing a conventional data transfer method performed via a shared bus.

[Explanation of symbols]

1: Master device 1-1: Master device 1-2
... Transfer control circuit, 1-3 ... Transfer interface buffer, 2 ... Slave device, 2-1 ... Slave device,
2-2 transfer control circuit 2-3 transfer interface buffer 3 shared bus 4 arrow 5 address designation time 6 data transfer time 7 arbitration time 8 master port 9, 10: Shared bus port, 11: Slave port, 12, 13: Arrow, 14 ...
Register cell, 15: right data path, 16: upper data path, 17: left data path, 18: lower data path, 19-22: enable control signal, 24: flip-flop, 25: selector, 26-30 ... Control gate,
H ₁ ~H ₁₅ ... transfer block

Claims (1)

(57) [Claims] A master device connected via a shared bus.
Data between the device and the slave device by burst transfer.
In the data transfer method for transfer, the register cells are
Data written in the register cell
Can be freely shifted in the row and column directions, and
The end of the direction transmits and receives data to and from the master device.
Connected to the master port for
The first transfer interface bar connected to the
Master device with buffer and register cells in a matrix
And the data written to the register cell
In the row and column directions,
The end is a switch that exchanges data with slave devices.
Connected to the slave port, and the end in the row direction is shared bus port.
Transfer interface buffer connected to the
And a first transfer interface.
The face buffer transfers data to and from the master device.
Data transfer or second transfer interface
Buffer exchanges data with the slave device
When performing the transfer, the transfer is performed while shifting in the row direction.
Transfers data to / from the shared bus via the existing bus port
When performing a shift in the column direction every burst cycle.
A data transfer method characterized by exchanging data while transmitting.