JP3331081B2 - Subranging type A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unified subranging A / D converter. In particular, the present invention relates to a circuit for reducing an error between tap voltages of a ladder resistor.

[0002]

2. Description of the Related Art Unified type subranging type A
FIG. 6 shows a conventional configuration example of the / D converter (upper M bits, lower N bits). However, this figure is based on JSSC 1990 vol.
SC-25, No.1 "An 8-bit 20 MS / s CMOS A / D Converter wit
h 50-mW Power Consumption ". For simplicity, the figure shows upper 2 bits (M = 2) and lower 2 bits (N = 2). 4 shows a case where in the a / D converter bits is. symbol 1 in the figure ladder resistor for generating a reference voltage by resistance-dividing the reference voltage V _R consisting, 2 analog input terminal,
Reference numeral 3 denotes a switch group for switching between the analog input voltage and the upper and lower comparison tap voltages, 4 denotes a comparator array, and 5 denotes a digital adder. The comparator array 4 has three voltage comparators, each of which comprises an input capacitor Cc, a switch element 7 and an inverter 6.

The operation of the circuit shown in FIG. 6 will be described below.

A subranging type A / D converter has an A / D converter having three stages: a sample period, an upper comparison period, and a lower comparison period.
Perform the conversion. Moreover, in the unified system, as shown in FIG. 6, the same voltage comparator array 4 is used in the upper comparison period and the lower comparison period. FIG. 7 shows how the switch group 3 is connected in each period.

First, in the sampling period, the analog input voltage applied to the analog input terminal 2 is charged to each input capacitance Cc of the comparator array 4 (considering parasitic capacitance such as wiring capacitance). Next, in the upper comparison period, the switch group 3
Switches to the upper comparison tap voltage (Vrc1 to Vrc3),
The analog input voltage is compared with the upper comparison tap voltage. Thus, the upper code is determined, and the upper 1LSB in which the analog input voltage is located is selected. Further, in the lower comparison period, the switch group 3 sets the lower comparison tap voltage (Vrf1) in the region selected in the upper comparison period.
... Vrf3), and a more detailed comparison is performed. As a result, a lower code is determined. The resulting upper code and lower code are added by the digital adder 5 to obtain a digital output of all bits. After these actions,
A / D conversion of one sample is completed.

In practice, these operations are repeated at the sampling frequency, and all A / D conversions are performed.

[0007]

At present, there are the following problems.

That is, when the connection of the input capacitance of the comparator array is switched, the electric charge moves between the input capacitance and the ladder resistance due to the voltage difference. Since the switching of the connection is repeated at the sampling frequency, this charge transfer becomes a current flowing into and out of the ladder resistor. This current causes the tap voltage of the ladder resistor to bend. Each tap voltage is A / D
Since this is used as a reference voltage at the time of conversion, this deflection is one cause of deterioration of A / D conversion accuracy. The deflection of the tap voltage occurs at the time of the upper comparison and the lower comparison, respectively, and the sum of these becomes the deflection of the tap voltage.

FIG. 8 shows a plot of the error of the tap voltage (subtraction of the ideal value from the deflection) with respect to the position of the ladder resistance. The position of the ladder resistor is 0 ≦ x ≦ 1
It has been standardized.

In the upper comparison period, the connection is switched between the analog input voltage and the upper comparison tap voltage. As an example, the case of FIG. 9 is considered, and it is assumed that the analog input voltage Va corresponding to the position a of the ladder tap (ladder resistance) shown in FIG. 9 is applied. First, during the sampling period, the input capacitors (c1 to c3) are charged with the analog input voltage Va. Next, in the upper comparison period, the input capacitance (C1 to C
The connection of 3) corresponds to each upper comparison tap voltage (Vrc1 to Vrc3)
Switch to Since Vrc1> Va, current flows out of the ladder tap to the input capacitance c1, and Vrc2 <Va, Vrc
Since 3 <Va, a current flows into the ladder tap from the input capacitors c2 and c3. The state of the deflection of the tap voltage is determined from the sum of these outflow / inflow currents. In the case of the position a, since the inflow amount is larger than the outflow amount, the tap voltage becomes larger than the ideal value. Similar considerations can be made for all analog inputs. The error of the tap voltage is larger than the ideal value at the upper position (x ≧ 0.5) and smaller than the ideal value at the lower position (x ≦ 0.5) from the middle value (x = 0.5) of the ladder resistance (see FIG. Curve A in 8).

On the other hand, in the lower comparison period, the connection is switched between the upper comparison tap voltage charged to each input capacitor during the upper comparison and the lower comparison tap voltage near the analog input. In this case as well, as in the upper comparison, the charge / discharge current of the input capacitance flows into and out of the ladder resistor according to the magnitude of the voltage difference before and after the switch is switched. In this case, the error and the reverse polarity due to the upper-order comparison are shown, contrary to the upper-order comparison. Further, since the lower comparison is performed in the upper 1 LSB region based on the upper comparison result, the current density flowing into and out of the ladder resistor is 2 ^N times that of the upper comparison. Therefore, the error generated in the lower comparison period has a larger absolute value than the error generated in the upper comparison period (curve B in FIG. 8).

The sum of the errors in each comparison period is
This is the error of the actual tap voltage (curve C in FIG. 8).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object the purpose of the present invention.
It is to improve the linearity of the A / D conversion result of the D converter.

[0014]

The invention according to claim 1 is
A ladder resistor that divides a reference voltage by a resistor, connected to each tap of the ladder resistor and an analog input terminal, and a sample period, an upper comparison period, and a lower comparison period are controlled by first, second, and third clocks, respectively. In a subranging A / D converter including a switch group, a comparator array having a plurality of voltage comparators, and a digital adder , each of the plurality of voltage comparators is a switch.
A node connected to the switch group, and a node connected to the node and
The input volume whose output is sent to the digital adder
One end is connected to the ground side and the other end is
Capacitance connected to the node except for the lower comparison period
And the input capacitance value of each of the plurality of voltage comparators is set to a different value between the upper comparison period and the lower comparison period.

[0015]

According to a second aspect of the present invention, there is provided a subranging type A / D converter, wherein the capacitance according to the first aspect is set to a value twice as large as the input capacitance.

The subranging A / D converter according to claim 3, the capacitance according to claim 1, wherein the first and second
It is connected to the node via first and second switch elements, each controlled by a clock and connected in parallel.

The subranging A / D converter according to claim 4, in which the capacity of claim 1, wherein, connected to said node via a switch means controlled by the inverted clock of the third clock is there.

The subranging A / D converter according to claim 5, a ladder resistance of the reference voltage to resistance division, and analog input terminal to which the analog input voltage is inputted, the ladder
A higher-order comparison tap voltage input terminal to which a higher-order comparison tap voltage is input among the respective tap voltages of the resistor;
A lower comparison tap voltage input terminal to which a lower comparison tap voltage is input among the respective tap voltages, a switch connected to the analog input terminal and turned on only during a sample period,
Another switch connected to the upper comparison tap voltage input terminal and turned on only during the upper comparison period, and another switch connected to the lower comparison tap voltage input terminal and turned on only during the lower comparison period; and A node connected to another switch and a further switch, an input capacitor connected to the node, a switch connected to the node, and turned on only in the sample period and the upper comparison period; and the switch And a capacitor inserted between the ground and the ground.

[0020]

The sub-ranging type A / D converter according to claim 1 is provided.
In the sample period, the capacitance and the input capacitance
, And both capacities are charged. Next, the upper comparison period
However, since the capacitance and the input capacitance are connected,
Current flowing between the comparator and the ladder resistor increases
You. On the other hand, during the lower comparison period, only the input capacitance is
The connection does not increase the current flow.
No. As a result, during the upper comparison period,
Resulting tap voltage error, which is lower ratio
Has the opposite characteristic to the tap voltage error in the comparison period
Therefore, the tap voltage error generated during the lower comparison period increases.
The tap voltage error during the upper comparison period
It is. Thus, the sub-ranging type A /
In the D converter, the tap voltage error generated in the upper comparison period is changed according to the setting of a different input capacitance value so as to cancel the tap voltage error generated in the lower comparison period.

[0021]

In the subranging A / D converter according to the second aspect , the tap voltage error generated in the lower comparison period is canceled by the increased tap voltage error in the upper comparison period.

In the subranging type A / D converter according to the third aspect , the connection between the capacitor and the node during the sampling period is realized by the first switch element turned on by the first clock. The connection between the capacitor and the node during the upper comparison period is realized by the second switch element turned on by the second clock.

In the sub-ranging type A / D converter according to the fourth aspect , the connection between the capacitor and the node is controlled by an inverted clock of the third clock. Therefore, the switch is turned on and the capacitance is connected to the node during the sample period and the upper comparison period, but the switch is turned off and the capacitance is not connected to the node during the lower comparison period.

In the subranging type A / D converter according to the fifth aspect , the switch and the switch means are turned on during the sampling period, and the analog input voltage charges the input capacitance and the capacitance. In the upper comparison period, another switch and switch means are turned on, and current flows in and out according to the voltage difference between the upper comparison tap voltage and the node potential. On the other hand, in the lower comparison period, only another switch is turned on, and current flows in and out according to the voltage difference between the lower comparison tap voltage and the node potential given by the charging voltage of the input capacitor.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention intends to cancel tap voltage errors by utilizing the fact that tap voltage deflections generated during an upper comparison period and a lower comparison period have opposite characteristics. Therefore, in each of the following embodiments, a configuration is adopted in which the input capacitance value of the comparator array is changed between the upper comparison period and the lower comparison period.

[0027] (Example 1) subranging A / D converter according to a first embodiment of the present invention, like the conventional A / D converter shown in FIG. 6, the resistor dividing the reference voltage V _R Ladder resistor (ladder tap) 1 for generating a reference voltage, a switch group 3, a comparator array 4, and a digital adder 5
They are roughly divided into However, in the first embodiment, the configuration of each voltage comparator constituting the comparator array 4 is different. Other parts are the same as those in FIG.

FIG. 1 is a block diagram showing one of a plurality of voltage comparators constituting the comparator array 4 of the first embodiment, and showing an equivalent circuit thereof together with a schematic switch group 3. As shown in the figure, the voltage comparator is an inverter 6
And the switching element 7 controlled by the first clock φ1
And an input capacitor C connected between the node Na and the node Nb.
It has a _c, and a switch means SW which is connected to the node Na, a capacitor C _e connected between the switching means SW and the ground. Then, the switch means SW outputs the first clock φ
1 and a second switch element SW2 controlled by a second clock φ2.

[0029] On the other hand, in the analog input terminal 2 to the switch group 3 is connected to the node Na through a switch controlled by the first clock .phi.1, inputs the analog input voltage V _a to the voltage comparator. The upper comparison tap voltage input terminal 8 is connected to the node Na via a switch controlled by the second clock φ2, and inputs the upper comparison tap voltage V _rc to the voltage comparator. Further, the lower comparison tap voltage input terminal 9 is connected to the node Na via a switch controlled by the third clock φ3, and inputs the lower comparison tap voltage _Vrf to the voltage comparator.

FIG. 2 shows the timings of the first to third clocks φ1 to φ3. In the figure, when each of the first to third clocks φ1 to φ3 is at “H” level,
Each corresponds to a sample period, an upper comparison period, and a lower comparison period.

[0031] In sample period, the first switching element SW1 and switching element 7 is turned on, the analog input voltage V _a is charged to the input capacitance C _c and the capacitance C _e.

In the upper comparison period, the second switch element SW
2 is turned on, the capacitance C _e is connected in parallel with the input capacitance C _c. That is, the input capacitance value of each voltage comparator of the comparator array, and thus given by the input capacitance C _c and the capacitance C _e. As a result, it is possible to increase the inflow and outflow of the current to and from the ladder resistor 1 that occurs at the time of the upper comparison. On the other hand, the lower comparison period, the first and second switching elements SW1, SW2 is not turned on any, will not be capacitance C _e is connected in parallel with the input capacitance C _c. That is, the input capacitance value of each voltage comparator of the comparator array is given only by the input capacitance C _c. Therefore, it is possible to cancel the error in the lower comparison having a large absolute value by the increase in the upper comparison.

FIG. 3 shows a preferred embodiment of FIG. In order to realize the equivalent circuit of FIG. 1, as shown in FIG. 3, two capacitors C _e1 (first capacitance) and C _e2 (second capacitance) having the same capacitance value as the input capacitance C _c are connected in parallel. and forming the capacitor C _e, further, it is provided with an inverter means inv.1 to equalize the circuit state after the node Na. The inverter means inv.1 comprises a third switch element SW3 controlled by the first clock φ1 and an inverter element 10. Note that the capacitance values of the first capacitance C _e1 , the second capacitance C _e2, and the input capacitance C _c are set within a range of process variation.

FIG. 4 shows the configuration in FIG. 3, that is, the capacitance C
The deflection of the ladder resistor 1 of the tap voltage when the _e = 2C _c, and plotted versus the position of the ladder resistor 1, in the figure, curves A and B at the upper comparison and at lower comparison respectively A tap voltage error is shown, and both curves A and B are substantially line-symmetrical. As a result, an actually obtained tap voltage error is as shown in a curve C. Therefore, when the capacitance C _e = 2C _c , the linearity of the A / D conversion result is the best.

(Embodiment 2) A subranging type A / D converter according to a second embodiment of the present invention relates to a modification of the above-described first embodiment, and its configuration is shown in an equivalent circuit of FIG. That is, in the second embodiment, the switch means S of the first embodiment is used.
W is constituted by one switch means SWA,
The switch means SWA is controlled by an inverted clock φ3 bar of the third clock φ3. Other points are the same as the first embodiment. Therefore, the third clock φ3 is H
The lower comparison period in the level, capacitance C _e is the node Na
Will not be connected to. In this case, improvement of the linearity of the reduction · A / D conversion result of the error of the ladder resistor is realized similarly, the best linearity of the A / D conversion result particularly when the capacitance C _e = 2C _c This is the same as in the first embodiment.

[0036]

The sub-ranging type A / D according to claim 1
According to the converter, it is possible to increase the inflow and outflow of current to the ladder resistor generated at the time of the upper-order comparison, thereby increasing the error at the time of the upper-order comparison and offsetting the error at the time of the lower-order comparison having a large absolute value. , A / D conversion results can be improved. Moreover, this subranging type A / D converter
The ladder resistance by setting the capacity value appropriately.
A / D with deflection of tap voltage of resistance being cancelable
The linearity can be improved.

[0037]

[0038] According to subranging A / D converter according to claim 2, it is possible to cancel the deflection of the tap voltage of the ladder resistor, thereby improving the optimum linearity of the A / D conversion result can do.

According to the subranging type A / D converter according to the third aspect , it is possible to reduce the deflection of the tap voltage of the ladder resistor and to improve the A / D linearity accordingly.

According to the subranging type A / D converter according to the fourth aspect , it is possible to reduce the deflection of the tap voltage of the ladder resistor and to improve the A / D linearity accordingly.

According to the subranging type A / D converter according to the fifth aspect , it is possible to increase the current flowing into and out of the ladder resistor at the time of the upper-order comparison, and reduce the error at the time of the lower-order comparison having a large absolute value. As a result, the A / D conversion result can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a subranging type A / D converter as one embodiment of the present invention.

FIG. 2 is a timing chart showing the timing of each switch.

FIG. 3 is a diagram showing a specific implementation method of the A / D converter of FIG. 1;

FIG. 4 is a diagram showing the effect of the embodiment of the present invention.

FIG. 5 is a diagram showing an equivalent circuit of a subranging type A / D converter as another embodiment of the present invention.

FIG. 6 is a block diagram showing a circuit of a conventional unified subranging A / D converter.

7 is a view to view the connection state of the switches in each period.

FIG. 8 is a diagram illustrating a calculation result of a deflection of a tap voltage generated in each comparison.

FIG. 9 is a diagram for explaining a charge / discharge current generated by switching of a switch at the time of upper-order comparison.

[Explanation of symbols]

1 ladder resistance, 2 analog input terminals, 3 switches, 4 comparator array, 5 digital adder, tap voltage input terminal 8 upper comparison, the tap voltage input terminal 9 lower comparison, 10 inverter, V _a analog input voltage, V _rc upper comparison tap voltage, V _rf lower comparison tap voltage, C _c input capacitance, C _e capacitance, C _e1 first capacitor, C _e2 second capacitor, SW1 first switch element, SW
2 Second switch element, SW3 Third switch element, S
W, SWA switch means.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-212120 (JP, A) JP-A-4-242321 (JP, A) JP-A-1-190120 (JP, A) JP-A 57-212 141124 (JP, A) Hira 4-38138 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (5)

(57) [Claims] A ladder resistor for dividing a reference voltage by resistance;
A switch group connected to each tap of the ladder resistor and an analog input terminal and controlled by first, second and third clocks during a sample period, an upper comparison period and a lower comparison period, respectively, and a plurality of voltage comparators; Type A with comparator array and digital adder
/ D converter, each of the plurality of voltage comparators includes a node connected to the switch group, and an output connected to the node and having the output of the digital adder.
The input capacitance to be sent to the calculator, one end of which is connected to the ground side and the other end is
A capacitance connected to the node except for the potential comparison period , whereby the input capacitance values of the plurality of voltage comparators are set to different values in the upper comparison period and the lower comparison period. A sub-ranging type A / D converter characterized by the above -mentioned. 2. The method according to claim 1, wherein the capacitance is set to a value twice as large as the input capacitance.
The sub-ranging type A / D converter according to claim 1, wherein 3. The system according to claim 2, wherein the capacity is the first and second clocks.
And the first and the
Being connected to the node via a two-switch element
The sub-ranging type A / D according to claim 1, characterized in that :
converter. 4. The capacitor according to claim 3, wherein said capacitor is an inverted clock of said third clock.
The switch is controlled by a lock.
The sub-ranging type A / D converter according to claim 1, wherein the A / D converter is connected to a node . 5. A ladder resistor for dividing a reference voltage by resistance, an analog input terminal to which an analog input voltage is inputted , and a higher-order comparison tap among tap voltages of the ladder resistor.
An upper comparison tap voltage input terminal to which a voltage is input; and a lower comparison tap among the tap voltages of the ladder resistor.
And lower ratio 較用tap voltage input terminal to which a voltage inputs connected to said analog input terminal, the sample period only O
And the main routine switches, connected to the tap voltage input terminal for upper comparison, the upper ratio
Connected to another switch that is turned on only during the comparison period, and the lower comparison tap voltage input terminal.
Another switch that is turned on only during the comparison period, and a switch connected to the switch, another switch, and another switch.
Connected node and input capacitance connected to said node
And connected to the node, the sample period and higher order comparison
A switch device that is turned on only during a period, and a capacitor inserted between the switch device and ground.
And the amount, characterized by comprising, subranging type A / D converter.