JP3329642B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device that performs an operation similar to a semiconductor device having a MOS gate structure such as a GBT and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices having a MOS gate structure have been frequently used as power devices and high frequency devices. FIG. 37 shows a power M as an example of a conventional power device.
1 shows a cross-sectional view of an OSFET.

In the figure, reference numeral 92 denotes an n-type drift layer, a p-type well layer 93 is selectively formed on the surface of the n-type drift layer 92, and a low-resistance n-type source layer 94 is formed on the p-type well layer. It is selectively formed on the surface of the layer 93.

A gate electrode 97 is provided on a p-type well layer 93 between an n-type drift layer 92 and an n-type source layer 94 via a gate insulating film 96. Also, the p-type well layer 9
Source electrode 95 is provided so as to contact both 3 and n-type source layers 94. Then, a drain electrode 98 is provided on the n-type drift layer 92 via a low-resistance n-type semiconductor layer 91.

In this type of power MOSFET, semiconductor layers such as a p-type well layer 93 and an n-type source layer 94 are formed by diffusion of impurities. For example, the p-type well layer 93 is formed by diffusion of a p-type impurity such as boron, and the n-type source layer 9 is formed.
4 is formed by diffusion of an n-type impurity such as arsenic.

Therefore, the power MOSFET has the following problems. That is, since formation by diffusion of impurities takes time, the p-type well layer 93 and the n-type source layer 9 are formed.
It takes time to form a semiconductor layer such as No. 4, and as a result, there is a problem that the manufacturing time of the device becomes long. Especially Si
When a semiconductor, such as C, CdS, or diamond, which makes diffusion of impurities difficult, is used as a bulk material, manufacture of the device becomes impossible.

Further, in a semiconductor device having a MOS gate structure such as a power MOSFET, a current flows through a channel whose generation is controlled by the gate electrode 97, so that a channel resistance exists. Such channel resistance causes an increase in on-voltage, making it difficult to improve on-characteristics. Particularly, it is known that channel resistance is large in SiC or the like, and it is difficult to realize this type of semiconductor device.

[0008]

As described above, since the conventional power MOSFET is formed by diffusion of impurities, there is a problem that the manufacturing time of the device becomes long. In addition, there is a problem that the ON voltage is increased due to the presence of the channel resistance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can shorten the manufacturing time and improve the ON characteristics as compared with the related art. It is in.

[0010]

SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
In a semiconductor device, a first semiconductor layer of a first conductivity type, a first main electrode for Schottky junction with the first semiconductor layer,
A second main electrode connected to the first semiconductor layer; and control means for controlling a height of the Schottky barrier of the Schottky junction, wherein a voltage is applied between the first and second main electrodes. When the height of the Schottky barrier is reduced in a state where the voltage is applied, the Schottky barrier is turned on, and in the on state, a current flows between the first and second main electrodes through the first semiconductor layer.

According to a second aspect of the present invention, in a semiconductor device, a first semiconductor layer of a first conductivity type, a first main electrode having a Schottky junction with the first semiconductor layer, and A second semiconductor layer of a low resistance and a first conductivity type disposed;
A second main electrode in ohmic contact with the second semiconductor layer,
Control means for controlling the height of the Schottky barrier of the Schottky junction;
When the height of the Schottky barrier is reduced while a voltage is applied between the main electrodes, the Schottky barrier is turned on, and in the on state, a current flows between the first and second main electrodes through the first and second semiconductor layers. And

According to a third aspect of the present invention, in a semiconductor device, a first semiconductor layer of a first conductivity type, a first main electrode having a Schottky junction with the first semiconductor layer, and a first semiconductor layer formed on the first semiconductor layer. A second semiconductor layer of low resistance and second conductivity type disposed;
A second main electrode in ohmic contact with the second semiconductor layer,
Control means for controlling the height of the Schottky barrier of the Schottky junction;
When the height of the Schottky barrier is reduced while a voltage is applied between the main electrodes, the Schottky barrier is turned on, and in the on state, a current flows between the first and second main electrodes through the first and second semiconductor layers. And

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the control means includes an insulating film interposed between the first semiconductor layer adjacent to the Schottky junction. And a control electrode opposed thereto.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, a trench is formed in the first semiconductor layer adjacent to the Schottky junction, and the control electrode is formed in the trench. It is characterized by being arranged.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the plurality of trenches are separated from each other by the trench, and the plurality of control electrodes are respectively disposed in the trenches. It is characterized by comprising a control electrode portion.

According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects, the first main electrode extends between the control electrode and the first semiconductor layer. Wherein the Schottky junction is formed by the extension.

According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, a tunnel insulating film is provided between the first main electrode and the first semiconductor layer. It is characterized by the following.

According to a ninth aspect of the present invention, in the semiconductor device according to any one of the first to eighth aspects, a semiconductor layer of a second conductivity type is provided between the first main electrode and the first semiconductor layer. It is characterized by being arranged.

According to a tenth aspect of the present invention, in the semiconductor device according to any one of the first to ninth aspects, the first semiconductor layer is made of a material selected from the group consisting of Si, SiC, Cd and diamond. It is characterized by the following.

According to an eleventh aspect of the present invention, in the semiconductor device according to any one of the first to tenth aspects, the first conductivity type is an n-type.

According to a twelfth aspect of the present invention, in the semiconductor device according to the seventh aspect, the extension is formed of a silicide layer.

According to a thirteenth aspect of the present invention, in the semiconductor device according to the seventh aspect, the extension is made of a metal thin film having a thickness of 0.2 μm or less.

According to a fourteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the twelfth aspect, a step of forming the control electrode on the first semiconductor layer via a gate insulating film; And forming the silicide layer in a self-aligned manner using the method.

According to a fifteenth aspect of the present invention, in a semiconductor device, a first semiconductor layer of a first conductivity type, a first main electrode having a small area disposed on the first semiconductor layer, A second main electrode connected to a semiconductor layer; and a large-area control electrode disposed on the first semiconductor layer and the first main electrode with an insulating film interposed therebetween. A current flows between the first and second main electrodes through one semiconductor layer, and a second conductivity type inversion layer induced in the first semiconductor layer by applying a potential to the control electrode allows the first main electrode to be formed. The lower current path is pinched off.

In the semiconductor device according to the present invention, the height of the Schottky barrier at the interface between the first main electrode and the semiconductor layer is reduced by applying a voltage to the control electrode, for example, by the control means. Thus, the semiconductor device is in an operation state, and a current flows between the first and second main electrodes through the first semiconductor layer. When the first semiconductor layer is n-type, electrons are injected from the first main electrode into the first semiconductor layer in an operation state.

Since the channel does not exist despite the control of the main current by the control electrode, an increase in the on-state voltage due to the channel resistance can be prevented, and the on-state characteristics can be improved. Also,
Since a diffusion layer is basically unnecessary, there is no problem that the manufacturing time is long.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a low-resistance n-type semiconductor substrate made of silicon, and an n-type semiconductor layer 2 made of silicon is formed on the n-type substrate 1 by epitaxial growth. On the surface of the n-type semiconductor layer 2, a stripe-shaped, island-shaped or annular source electrode 4 (first main electrode) is formed by Schottky junction. As a material of the source electrode 4, for example, Al, A
u, Pt, Ti, and Pd.

The source electrode 4 is formed on the surface of the n-type semiconductor layer 2.
, A stripe-shaped, island-shaped or annular gate electrode 6 is provided via a gate insulating film 5. Gate electrode 6
Are insulated from the source electrode 4. Then, the drain electrode 3 (second main electrode) makes ohmic contact with the n-type substrate 1.

FIG. 2 is a diagram showing a potential distribution (eV value) of the device in a cross section taken along line II-II of FIG.

[0032] in the case of applying a zero or negative gate voltage V _G to the gate electrode 6 with respect to the source electrode 4, the interface to a sufficiently high Schottky barrier with the n-type semiconductor layer 2 and the source electrode 4 (that level _VB ) in the figure is formed.
For this reason, even when a predetermined voltage is applied between the drain electrode 3 and the source electrode 4, the injection of electrons from the source electrode 4 to the n-type semiconductor layer 2 is performed similarly to the reverse bias state of the Schottky diode. Does not happen.

On the other hand, in the case of applying a positive gate voltage V _G to the gate electrode 6, the Schottky barrier is low at a portion close to the gate electrode 6. As Figure 2 illustrates, as the gate voltage V _G is higher Schottky barrier is low. Then, the gate voltage V _G is a predetermined value (threshold voltage)
Is exceeded, the height of the Schottky barrier becomes sufficiently small. Therefore, when a predetermined ON voltage is applied so that the drain electrode 3 is positive and the source electrode 4 is negative, a large number of electrons are injected from the source electrode 4 into the n-type semiconductor layer 2, The device is in a conductive state (ON state).

As described above, in the semiconductor device shown in FIG. 1, a positive gate voltage is applied to the gate electrode 6 to lower the height of the Schottky barrier so that the main current flows in the device. Become. That is, the main current is switched by controlling the height of the Schottky barrier by the voltage applied to the gate electrode 6.

Therefore, in the semiconductor device shown in FIG. 1, although a gate electrode 6 is present, unlike a MOSFET, a diffusion layer is formed in the n-type semiconductor layer 2 or a channel is formed for switching main current. There is no need to control the generation. Therefore, there is no problem that the manufacturing time is long due to the formation of the diffusion layer and the ON voltage is increased due to the channel resistance.

In the semiconductor device shown in FIG.
As described above, since the height of the Schottky barrier is controlled by the gate voltage, the amount of the main current can be continuously changed, similarly to the MOSFET. Moreover, since there is no channel resistance, the on-resistance is lower than that of the MOSFET, and high-speed operation is possible. Therefore, the present semiconductor device is also effective as a high-frequency device.

In the semiconductor device shown in FIG.
Although silicon was used as the material of the substrate 1 and the semiconductor layer 2, since the device structure according to the present invention does not require a diffusion layer,
It is possible to use a material such as iC, Cd, or diamond which has a lower impurity diffusion coefficient than silicon and has difficulty in forming an impurity diffusion layer.

When a reverse bias is applied between the source and the drain, the Schottky junction becomes conductive, and a commutating diode when an inverter circuit is assembled becomes unnecessary. Further, since this diode is a Schottky barrier diode, the speed is higher than that of a pn junction type semiconductor device, and the performance of the inverter circuit is significantly improved.

In this embodiment and in many embodiments described below, an n-type semiconductor substrate 1 is provided below the n-type semiconductor layer 2. In this case, the operation of the device formed is similar to that of a MOSFET. However, as shown in FIG. 30, a p-type semiconductor substrate 11 may be used instead of the n-type semiconductor substrate 1. In this case, the operation of the semiconductor device formed is similar to that of an IGBT (a bipolar transistor with an insulated gate).

FIG. 3 is a sectional view of a semiconductor device according to another embodiment of the present invention. In the drawings of the following embodiments, portions corresponding to the above-described drawings are denoted by the same reference numerals as those in the above-described drawings.

The semiconductor device shown in FIG. 3 differs from the semiconductor device shown in FIG. 1 in that the source electrode 4 and the gate electrode 6 partially overlap with the gate insulating film 5 interposed therebetween. For this reason, even if the same level of gate voltage is applied to the gate electrode 6, the height of the Schottky barrier at the interface between the source electrode 4 and the n-type semiconductor layer 2 becomes lower, so that the on-voltage can be further reduced. it can.

Further, since the source electrode 4 in a portion overlapping with the gate electrode 6 is formed thin, the thin portion functions as a negative feedback resistor (that is, a ballast resistor) connected in series to the source. Therefore, when a plurality of semiconductor devices are formed, the current distribution of each semiconductor device is made uniform.

In the case of the present embodiment, the electric field may be concentrated at the corners (ends) of the source electrode 4 in the off state, and the leakage current may increase. This is because the gate voltage is adjusted to a negative value. This can be prevented by relaxing the electric field concentrated on the corner of the source electrode 4.

FIG. 4 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 4 differs from the semiconductor device shown in FIG. 3 in that the corner shape of the source electrode 4 is tapered. For this reason, a high electric field is formed at the narrow portion at the tip of the tapered portion during the on-state, so that electron injection can be effectively performed from the tip and the on-voltage can be further reduced.

FIG. 5 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 5 is different from the semiconductor device shown in FIG. 4 in that the gate electrode 6 is also formed in a tapered shape so that the height of the Schottky barrier can be more effectively controlled by the gate voltage. I did it.

FIG. 6 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 6 differs from the semiconductor device shown in FIG. 5 in that the entire corners of the source electrode 4 and the gate electrode 6 are formed in a tapered shape. The same effect as the semiconductor device shown in FIG. 5 can be obtained in the semiconductor device shown in FIG. Further, the source electrode 4 is larger than the semiconductor device shown in FIG.
Further, since the shape of the gate electrode 6 is simplified, the manufacture is easy.

FIG. 7 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 7 is different from the semiconductor device shown in FIG. 3 in that a gate electrode 6 is buried in a trench on the surface of an n-type semiconductor layer 2 via a gate insulating film 5. .

In the semiconductor device shown in FIG. 7, the gate electrode 6 and the source electrode 4 partially overlap each other via the gate insulating film 5 in the depth direction of the trench. Therefore, FIG.
The same effects as those of the semiconductor device shown in FIG.

FIG. 8 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 8 differs from the semiconductor device shown in FIG. 5 in that a part of the gate electrode 6 is Schottky-bonded to the surface of the n-type semiconductor layer 2. Further, the gate electrode 6 is provided with a resistor R to prevent a large current from flowing to the device when the gate electrode 6 is turned off. In addition, the gate electrode 6
The formation of an underlying oxide film becomes unnecessary.

It is preferable to select the material of the source electrode 4 and the material of the gate electrode 6 so that the height of the Schottky barrier formed by the gate electrode 6 is higher than that of the source electrode 4.

FIG. 9 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 9 is different from the semiconductor device shown in FIG. 1 in that a silicide layer 7 of PtSi or the like is inserted at the interface between the source electrode 4 and the n-type semiconductor layer 2 so that the semiconductor device is more stable. It is to form a Schottky junction. It is preferable that the silicide layer 7 partially overlaps the gate electrode 6.

FIG. 10 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 10 is different from the semiconductor device shown in FIG. 1 in that a portion of the surface of the n-type semiconductor layer 2 where the Schottky junction is formed by the source electrode 4 and the n-type semiconductor layer 2 is formed. That is, the p-type diffusion layer 8 is formed in the portion. The p-type diffusion layer 8 can be formed corresponding to the entire lower surface of the source electrode 4.

According to the semiconductor device shown in FIG. 10, the barrier against electrons is increased by the p-type diffusion layer 8, and the leakage current due to carriers flowing into the device over the Schottky barrier in the off state can be reduced.

In the case of the semiconductor device shown in FIG. 10, the p-type diffusion layer can be optimally formed and the threshold voltage can be set high in order to prevent a malfunction in the off state.
In order to prevent malfunction due to noise, it is desirable to set the threshold voltage high for a high power device.

FIG. 11 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 11 corresponds to FIGS.
0 is a combination of the features of the semiconductor device shown in FIG. That is, in the semiconductor device shown in FIG.
A p-type diffusion layer 8 is formed underneath, and a silicide layer 7 forming a Schottky junction is selectively formed on the surface of the p-type diffusion layer 8.

FIG. 12 is a plan view of a semiconductor device according to still another embodiment of the present invention. FIG. 13 is a view similar to FIG.
FIG. 14 is a sectional view taken along line XIII-XIII, and FIG.
FIG. 4 is a sectional view taken along the line XIV.

The semiconductor device shown in FIGS. 12 to 14 has a configuration in which the silicide layer 7 which is a feature of the semiconductor device shown in FIG. According to the semiconductor device shown in FIGS. 12 to 14, even in a region where the source electrode 4 is not provided, electrons are partially injected from the silicide layer 7. Accordingly, the number of portions into which electrons are injected increases, and the on-voltage can be further reduced.

FIG. 15 is a plan view of a semiconductor device according to still another embodiment of the present invention. FIG. 16 is a view similar to FIG.
FIG. 17 is a sectional view taken along line XVI-XVI, and FIG.
FIG. 7 is a sectional view taken along line XVII.

In the semiconductor device shown in FIGS. 15 to 17, the gate electrode 6 which is a feature of the semiconductor device shown in FIG.
Of the source electrode 4a underneath. According to the semiconductor device shown in FIGS. 15 to 17, electrons are injected from the source electrode 4 a also in the region of the gate electrode 6. Therefore, as in the eleventh embodiment, the number of portions into which electrons are injected increases, so that the on-voltage can be further reduced.

FIG. 18 is a sectional view of a semiconductor device according to still another embodiment of the present invention. Note that the n-type semiconductor substrate 1 and the drain electrode 3 are omitted.

The feature of the semiconductor device shown in FIG. 18 is that a gate electrode is buried in a trench groove on the surface of n-type semiconductor layer 2 via a gate insulating film 5.

According to the semiconductor device shown in FIG. 18, since the length of the gate portion contributing to the control of the height of the Schottky barrier is increased as compared with the semiconductor device shown in FIG. 1, the ON voltage can be further reduced. .

Since the bottom of the trench is closer to the drain side than the lower portion (Schottky junction surface) of the source electrode 4, the voltage is applied to the drain electrode 3 when the trench is off, so that the trench is formed on the Schottky junction surface. The generated electric field E1 is weaker than the electric field E2 formed at the bottom of the trench. That is, the strong electric field due to the drain voltage at the time of off is supported by the bottom of the trench groove, and the Schottky junction is protected from the strong electric field. Therefore, the leak current due to the carriers exceeding the Schottky barrier can be reduced. Further, as much as the leakage current can be reduced, it can be used up to a higher temperature than before, and high-temperature operation is possible.

FIG. 19 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 19 differs from the semiconductor device shown in FIG. 18 in that a thin insulating film (tunnel insulating film) 9 is provided below the source electrode 4. Insulating film 9
Is set to such an extent that a tunnel current flows between the n-type semiconductor layer 2 and the source electrode 4.

According to the semiconductor device shown in FIG. 18, electrons flowing as a leak current at the time of off-state must cross not only the Schottky barrier but also the barrier of the insulating film 9.
Leakage current is reduced.

FIG. 20 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 20 differs from the semiconductor device shown in FIG. 18 in that the depth of the trench is deeper. According to the semiconductor device shown in FIG.
Is further reduced, so that the leak current can be further reduced, and the device can be operated up to a higher temperature.

FIG. 21 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 21 is a modification of the semiconductor device shown in FIG. 18 and has a structure in which the source electrode 4 extends into the trench. With such a structure, the area of the Schottky junction increases, and the on-state voltage when working as a reverse conducting diode can be reduced.

In the semiconductor device shown in FIG. 21, since the area of the Schottky junction is increased, there is a possibility that the leakage current may increase when the semiconductor device is turned off. This can be prevented by forming the trench deep.

FIG. 22 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The feature of the semiconductor device shown in FIG. 22 is that the source electrode 4 is formed on the entire surface, and the lower part of the source electrode 4 and the upper part of the gate electrode 6 are interposed via the gate insulating film 5 in the depth direction of the trench. The reason is that they overlap.

According to the semiconductor device shown in FIG.
As in the case of the semiconductor device shown in the figure, the on-voltage is reduced by adopting the trench groove. Further, similarly to the semiconductor device shown in FIG.
Even when the source electrode 4 and the gate electrode 6 partially overlap, the on-voltage is reduced. Therefore, according to the semiconductor device shown in FIG. 22, the on-voltage can be sufficiently reduced. Also, the switching speed is improved. Further, when used as an amplification device, a high amplification factor can be realized.

FIG. 23 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 23 is different from the semiconductor device shown in FIG. 1 in that a source electrode 4 and a gate electrode 5 are provided on an n-type semiconductor layer 2 via a thin insulating film (tunnel insulating film) 10. It is in. The thickness of insulating film 9 is set to such an extent that a tunnel current flows between n-type semiconductor layer 2 and source electrode 4.

In order to turn on the semiconductor device thus configured, a DC positive gate voltage is always applied to the gate electrode 5 with respect to the source. In addition, as described later,
An AC gate voltage may be applied.

When such a gate voltage is applied to the gate electrode 5, electron-hole pairs are generated in the n-type semiconductor layer 2 in the high electric field portion near the source electrode 4 and the gate electrode 5.

Electrons flow into the gate electrode 5 via the tunnel insulating film 10 due to the tunnel effect, but holes are trapped at the interface between the tunnel insulating film 10 and the n-type semiconductor layer 2. Is accumulated.

The accumulated positive charges form an electric field in the tunnel insulating film 10 having such an intensity that a tunnel phenomenon occurs, and electrons are injected from the source electrode 4 into the n-type semiconductor layer 2 through the tunnel insulating film 10. And the device is turned on.

On the other hand, to turn off the gate electrode, a zero or negative gate voltage is applied to the gate electrode 5 with respect to the source.
As a result, the holes trapped at the interface between the tunnel insulating film 10 and the n-type semiconductor layer 2 recombine with the electrons of the n-type semiconductor layer 2 and disappear, so that the injection of electrons from the source electrode 4 is stopped. , The device is turned off.

In order to facilitate generation of electron-hole pairs, only the lower portion of the gate electrode 5 or the tunnel insulating film 1 is formed.
A high-resistance p-type layer may be provided on the entire surface of the n-type semiconductor layer 2 below 0.

In order to prevent the device from being turned on by a leak current when the device is turned off, some of the source electrodes 4 are turned off.
May be connected to the n substrate 1.

The insulating film under the source electrode 4 is
A semiconductor film having a wider band gap may be used. In this case, electrons are injected across the barrier. Although a semiconductor film having such a wide band gap can be used, an insulating film is preferable.

FIG. 24 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 24 has a configuration in which the low-resistance n-type semiconductor substrate 1 of the semiconductor device shown in FIG. 23 is replaced with a low-resistance p-type semiconductor substrate 11 made of silicon. Therefore, the operation of the semiconductor device is similar to that of the IGBT.

To turn on the device thus constructed, a positive DC voltage with respect to the source is applied to the gate electrode 5. Once turned on, like the thyristor, holes are supplied from the p-type substrate 11, and the on-state of the device is maintained without applying a gate voltage to the gate electrode 5.

According to the semiconductor device shown in FIG. 24, both the electron current and the hole current flow in the device in a plasma state (high injection state), so that only the electron current flows as in the semiconductor device shown in FIG. The on-state voltage is lower than in the case of.

In the semiconductor device shown in FIGS. 23 and 24, a positive DC gate voltage is applied to the gate electrode 5 in order to turn on the device, but instead, an AC gate voltage is applied. It may be applied.

In this case, holes are accumulated at the interface between the tunnel insulating film 10 and the n-type substrate 2 while the gate voltage is negative,
Then, the holes accumulated during the period when the gate voltage is positive flow into the interface between the tunnel insulating film 10 and the source electrode 4.

As a result, an electric field having a strength enough to cause a tunnel phenomenon is formed in the tunnel insulating film 10, electrons are injected from the source electrode 4 into the n-type semiconductor layer 2 through the tunnel insulating film 10, and the device is turned on. State.

Note that the semiconductor device shown in FIG.
As in the case of ET, it is necessary to constantly apply an AC gate voltage in order to maintain the ON state.

Although the semiconductor device shown in FIG. 24 is controlled by the MOS gate electrode 6, a diode structure without the gate electrode 6 may be used. Even in that case, a semiconductor device with low on-voltage can be realized.

FIG. 25 is a sectional view of a semiconductor device according to still another embodiment of the present invention. The lower portion of the n-type semiconductor layer 2 may be an n-type substrate or a p-type substrate.

The feature of the semiconductor device shown in FIG. 25 is that the switching of the device is controlled by light. Therefore,
There is no gate electrode.

In the semiconductor device shown in FIG. 25, to turn on the device, light hν having a predetermined energy or more is applied to the n-type semiconductor layer 2 via the tunnel insulating film 10. As a result, electron-hole pairs are generated in the n-type semiconductor layer 2, holes are trapped at the interface between the tunnel insulating film 10 and the n-type semiconductor layer 2, and an electric field having a strength enough to cause a tunnel phenomenon is generated. It is formed on the insulating film 10. Therefore, electrons are injected from the source electrode 4 into the n-type semiconductor layer 2 through the tunnel insulating film 10 and the device is turned on.

Here, when the lower portion of the n-type semiconductor layer 2 is an n-type substrate (in the case of MOSFET operation), a current flows during irradiation of the light hν, and the device is turned off when the irradiation of the light hν is stopped. become.

On the other hand, when the lower part of the n-type semiconductor layer 2 is a p-type substrate (in the case of IGBT operation), once the device is turned on, the device remains on even if the irradiation of the light hν is stopped.

In the semiconductor devices shown in FIGS. 23, 24 and 25, it is desirable that the source electrode 4 is made of n-type polysilicon, since the injection of electrons is good.

FIG. 26 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 26 is different from the semiconductor device shown in FIG.
It is in Schottky joining.

In the semiconductor device shown in FIG. 26, in order to turn on the device, the n-type semiconductor layer 2 is irradiated with light hν having a predetermined energy or more. As a result, electron-hole pairs are generated in the n-type semiconductor layer 2, and holes are trapped at the interface between the source electrode 4 and the n-type semiconductor layer 2. Therefore, the height of the Schottky barrier is reduced, electrons are injected from the source electrode 4 into the n-type semiconductor layer 2, and the device is turned on.

Here, when the lower portion of the n-type semiconductor layer 2 is an n-type substrate (in the case of MOSFET operation), a current flows during irradiation of light hν, and the device is turned off when irradiation of light hν is stopped. become.

FIG. 27 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 27 is an example in which the present invention is applied to a horizontal device. In the figure, reference numeral 11 denotes a semiconductor substrate made of silicon, on which an n-type semiconductor layer 2 made of silicon is provided.

A low-resistance n-type semiconductor layer 12 made of silicon is formed on the n-type semiconductor layer 2, and the surface of the n-type semiconductor layer 12 is in ohmic contact with the drain electrode 3. Since the n-type semiconductor layer 12 is formed by epitaxial growth, it is higher than other portions.

Note that the drain electrode 3 may be a Schottky junction as well as the source electrode 4 to facilitate manufacture.

FIG. 28 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 28 differs from the semiconductor device shown in FIG. 27 in that an insulating substrate 13 is used instead of the semiconductor substrate 11. That is, the semiconductor device is formed on the SOI. Alternatively, a semi-insulating substrate such as a GaAs substrate may be used instead of the insulating substrate 13, and the n-type semiconductor layers 2 and 12 may be formed by doping impurities into a semi-insulating substrate such as a GaAs substrate.

FIG. 29 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 29 differs from the semiconductor device shown in FIG. 28 in that the low-resistance n-type semiconductor layer 12 does not exist and the drain electrode 3 forms a Schottky junction with the n-type semiconductor layer 2. is there.

FIG. 30 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 30 has a configuration in which the low-resistance n-type semiconductor substrate 1 of the semiconductor device shown in FIG. 22 is replaced with a low-resistance p-type semiconductor substrate 11. Therefore,
The operation of the semiconductor device is similar to that of the IGBT.

In order to turn on the device thus constructed, a DC positive gate voltage with respect to the source is applied to the gate electrode 5.

FIG. 31 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 31 is a modification of the semiconductor device shown in FIGS. 12 to 14 and FIGS. A feature of the semiconductor device shown in FIG. 31 is that the source electrode 4 is formed thin. When a negative bias voltage is applied to the gate electrode 6 in the blocking state, FIG.
As shown, a hole inversion layer ch is formed very close to the source electrode 4. Inversion layer ch is SIT
33, and pinches off under the source electrode 4 as shown by equipotential lines in FIG. FIG. 34 shows a band diagram at this time. The injection of electrons from the source electrode 4 is completely prevented by this pinch-off.

The effect of the semiconductor device shown in FIG. 31 is that even if the Schottky barrier height of the source electrode 4 is low, the source electrode 4 is formed by the inversion layer ch formed by the gate bias.
Pinch off underneath, so the effective barrier height Veff
Is increased (FIG. 34), and a complete blocking state is created. In an extreme case, the source electrode 4 may not be a Schottky junction.

The semiconductor device shown in FIG. 31 is turned on by increasing the voltage applied to the gate electrode or making it positive to inject electrons from the source electrode as in the other embodiments. Can be.

FIG. 35 is a plan view of a structure embodying the semiconductor device shown in FIGS. 31 to 34, and FIGS. 36 (a) and 36 (b) show FIG. 35 along lines S1-S1 and S2-S2, respectively. It is sectional drawing. As shown in FIG. 35, the source electrode 4 is basically narrow only in the portion between the gate electrodes 5.

FIG. 38 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

In this semiconductor device, an n-type semiconductor substrate 1 is made of SiC, and an n-type semiconductor layer 2 made of SiC is formed thereon by epitaxial growth. The drain electrode 3 makes ohmic contact with the surface of the n-type substrate 1.

The source electrode 4 is formed on the surface of the n-type semiconductor layer 2 by Schottky junction. A gate electrode 6 is provided on the n-type semiconductor layer 2 via an insulating film 5 (for example, a thermal oxide film) adjacent to the source electrode 4. Here, the thickness of the gate oxide film 5 in the MOS structure portion is desirably 1000 Å or less. Interlayer insulating film 17 is formed so as to cover gate electrode 6.
Is further provided thereon, and an Al layer 18 functioning as a part of the source electrode and a wiring layer is further provided thereon.

A method of forming the upper portion of the semiconductor device shown in FIG. 38 will be described with reference to FIGS.

First, a gate insulating film 21 is formed by thermal oxidation, and a gate electrode 22 made of p-type or n-type doped polysilicon is selectively deposited thereon by CVD. Next, the thermal oxide film other than the gate portion is removed (FIG. 39A). Next, a mixed film 23 of Ti or Pt and Si is formed by co-sputtering (FIG. 39B).

Next, heat treatment, that is, sintering (sintering)
ing), a silicide layer 24 is formed. Next, the mixed film 23 is oxidized and removed. Next, an insulating film 25 made of a silicon oxide film is formed by CVD.
(C)). Next, the insulating film 25 is patterned so that a portion covering the gate electrode 22 remains, and an Al layer 26 for wiring is formed (FIG. 39D).

According to this method, the device is formed in a self-aligned manner, and the Schottky electrode 4 (silicide layer 24) is formed under the gate insulating film 5, so that the Schottky barrier height due to the gate voltage is increased. Is effectively controlled, and the controllability of the main current by the gate voltage is improved. The height of the step at the silicide boundary is desirably 0.2 μm or less, and if it is 50 nm or less, it is possible to prevent a decrease in yield due to the step of the insulating film.

Next, another method of forming the upper part of the semiconductor device shown in FIG. 38 will be described with reference to FIGS.

First, a silicide layer 31 is selectively formed in the surface of the SiC semiconductor layer 2 (FIG. 40A). Next, a polysilicon film 32 is deposited on the surfaces of the silicide layer 31 and the semiconductor layer 2 (FIG. 40B). Next, the polysilicon film 32 is thermally oxidized to form an insulating film 33.
0 (c)).

At this time, the semiconductor (SiC) layer 2 may be oxidized. Before depositing the polysilicon film 32, the semiconductor layer 2
Is oxidized first, there is no step between the silicide layer 31 and it is possible to prevent disconnection or the like when the polysilicon film 32 is oxidized.

Next, a gate electrode 34 made of highly doped polysilicon is selectively formed on the insulating film 33 (FIG. 40D). Next, an interlayer insulating film 35 made of a silicon oxide film is formed by CVD. Next, the silicide layer 3
Then, the insulating films 33 and 35 on 1 are removed, and an Al layer 36 for wiring is formed so as to be in contact with the silicide layer 31 (FIG. 40E).

According to this method, the overlap between the Schottky junction (silicide layer 31) of the source electrode 4 and the gate electrode 6 is increased, and the controllability of the Schottky barrier by the gate is improved.

Next, another method of forming the upper portion of the semiconductor device shown in FIG. 38 will be described with reference to FIGS.

First, a Schottky metal thin film 41 is selectively formed on the surface of the SiC semiconductor layer 2 (FIG. 41).
(A)). Next, a polysilicon film 42 is deposited on the surfaces of the metal thin film 41 and the semiconductor layer 2 (FIG. 41B). Next, the polysilicon film 42 is thermally oxidized to form an insulating film 43 (FIG. 41C).

At this time, the semiconductor (SiC) layer 2 may be oxidized. Before depositing the polysilicon film 42, the semiconductor layer 2
Is oxidized first, there is no step with the Schottky metal thin film 41, and it is possible to prevent disconnection or the like when the polysilicon film 42 is oxidized.

Next, a gate electrode 44 made of highly doped polysilicon is selectively formed on the insulating film 43 (FIG. 41D). Next, an interlayer insulating film 45 made of a silicon oxide film is formed by CVD. Next, the insulating films 43 and 45 on the Schottky metal thin film 41 are removed, and the metal thin film 4 is removed.
An Al layer 46 for wiring is formed so as to be in contact with No. 1 (FIG. 41E).

According to this method, the overlap between the Schottky junction (Schottky metal film 41) of the source electrode 4 and the gate electrode 6 is increased, and the controllability of the Schottky barrier by the gate is improved.

The thickness of the metal thin film 41 is desirably 0.2 μm or less, and if it is 50 nm or less, it is possible to prevent a decrease in yield due to a step portion of the insulating film. In order to lower the on-voltage,
As a material of the metal thin film 41, a method of using Ti and making contact with an Al electrode is considered. On the other hand, it is desirable to use Ni and Au as the material of the metal thin film 41 from the viewpoint of the leak current and the cutoff ability. Further, as a material of the metal thin film 41, a mixed film of any one of Ti, Ni, and Au and Al may be used. In particular, when the ratio of Al: Ti is 1: 1 or less, the height of the Schottky barrier is sufficient and the reduction of the barrier height is small, so that a device having a large blocking ability can be manufactured. In addition, by setting the thickness of the metal thin film 41 to 20 atomic layers or less, a resistance is inserted in series in the electron injection portion, and current variation between cells is reduced.

FIG. 42 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 42 differs from the semiconductor device shown in FIG. 38 in that a p-type layer 8 (see FIG. 11) for improving withstand voltage is formed in the surface of n-type semiconductor layer 2. . The carrier concentration of the p-type layer 8 is set to 1 × 10 ¹⁷ / cm ³ or less.

Referring to FIGS. 43A to 43E, a method of forming the upper portion of the semiconductor device shown in FIG. 42 will be described. This method is a partial modification of the method shown in FIGS.

First, a gate insulating film 21 is formed by thermal oxidation, and a gate electrode 22 made of p-type or n-type doped polysilicon is selectively deposited thereon by CVD. Next, the thermal oxide film other than the gate portion is removed (FIG. 43A). Next, using the gate electrode 22 as a mask, boron is ion-implanted on the surface of the semiconductor layer 2 to form a boron implant layer 27 (FIG. 43).
(B)). Next, a mixed film 23 of Ti or Pt and Si is formed by co-sputtering (FIG. 43C).

Next, heat treatment, that is, sintering,
The silicide layer 24 is formed, and the boron of the boron implantation layer 27 is diffused to form the p-type layer 8. next,
The mixed film 23 is oxidized and removed. Next, an insulating film 25 made of a silicon oxide film is formed by CVD.
(D)). Next, the insulating film 25 other than the gate portion is removed, and an Al layer 26 for wiring is formed (FIG. 43E).

According to this method, the device is formed in a self-aligned manner, and the Schottky electrode 4 (silicide layer 24) is formed under the gate insulating film 5. Is effectively controlled, and the controllability of the main current by the gate voltage is improved. Further, by forming the p-type layer 8, the leakage current in the forward blocking state can be reduced.

Next, another method of forming the upper portion of the device structure of the semiconductor device shown in FIG. 38 will be described with reference to FIGS. The illustrated method can be performed subsequent to the step illustrated in FIG.

First, the insulating film 25 is patterned so as to leave a portion covering the gate electrode 22 from the structure shown in FIG. Next, boron is ion-implanted on the surface of the semiconductor layer 2 through the silicide layer 24 using the gate electrode 22 covered with the insulating film 25 as a mask to form a boron implant layer 28 (FIG. 44A). . Next, the p-type layer 8 is formed by diffusing boron of the boron implantation layer 28 by heat treatment (FIG. 44B). Next, A for wiring
An l-layer 26 is formed (FIG. 44C).

According to this method, it is possible to prevent deterioration during the formation of the silicide layer 24 due to implanted impurities, for example, boron.

FIG. 45 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

In the semiconductor device shown in FIG.
A low-resistance p-type layer 11 (see FIG. 30) is disposed on the anode side of n-type semiconductor layer 2 made of C. Therefore, the operation of the semiconductor device is similar to that of the IGBT. When a positive potential is applied to the gate electrode 6 with respect to the electrode 4, the Schottky barrier of the electrode 4 is lowered below the gate electrode 6, and electrons are injected into the n-type semiconductor layer 2. The injected electrons reach the p-type layer (emitter layer) 11 on the anode side, and the p-type layer 1
The barrier between 1 and n-type layer 2 is lowered, and the injection of holes from p-type layer 11 is promoted. In this way, the device performs a bipolar operation.

Referring to FIGS. 46A to 46C, the p-type layer (emitter layer) 1 on the anode side of the semiconductor device shown in FIG.
1 will be described.

First, silicon and / or germanium are ion-implanted in the back surface of the n-type semiconductor layer 2 (for example, a SiC substrate) (FIG. 46A) and boron is implanted (FIG. 46B). ). Next, the Al electrode 3 is disposed on the back side of the implant layer (FIG. 46).
(C)).

By implanting silicon or germanium, boron is easily activated in the crystal and activated, and the ohmic junction of the electrode 3 is easily formed. As a result, the implanted layer containing boron becomes a p-type layer (emitter layer), so that a device that performs bipolar operation can be realized.

FIG. 47 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

An n-type semiconductor layer 2 made of SiC is epitaxially grown on an n ⁺ -type substrate 1 (or p-type substrate 11) made of SiC. The drain electrode 3 makes ohmic contact with the surface of the substrate 1. A trench is selectively formed on the surface of the semiconductor layer 2, and a gate electrode 6 is formed in the trench via an insulating film 5 (for example, a thermal oxide film). The thickness of the insulating film 5 is desirably 100 nm or less in the case of a thermal oxide film. The upper surface of the semiconductor layer 2 other than the trench is in contact with the source electrode 4. It is desirable that the interface in contact with the source electrode 4 be Schottky junction.

FIG. 48 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device shown in FIG. 48 is different from the semiconductor device shown in FIG. 47 in that n ⁺
The layer 16 is formed, and the source electrode 4 makes ohmic contact with the n ⁺ layer 16.

FIG. 49 shows the semiconductor device shown in FIG. 48 in which the bulk width W between trenches (see FIG. 48) is based on the assumption that the ratio of off-resistance / on-resistance is at least four digits (10 ⁴ ). 4 is a graph showing the relationship between the density of the SiC layer and the impurity concentration of the SiC layer. In the graph, the limit lines L1, L2
Is the range that satisfies the condition. In other words, under conditions outside this range, the switching characteristics are poor and the leakage current is large.
FIG. 50 is a graph showing the relationship between the bulk width W and the breakdown voltage of the device, obtained based on the conditions of FIG.

The graphs shown in FIGS. 49 and 50 show the case where the trench has a stripe shape. When the trench is formed so as to surround the bulk portion, the effect of the gate potential on the bulk portion is doubled, so that the same effect can be obtained even when the width W is twice the value shown in both graphs.

As shown in FIG. 47, when the source electrode 4 is in Schottky junction with the n-type semiconductor layer 2, switching is possible even if the width W is large. However, in view of the effect of reducing the leak current, it is desirable that the width W does not exceed about 3 to 4 times the value shown in both graphs. When the barrier height is low due to the incompleteness of the Schottky junction, or when the barrier lowering due to the drain voltage is large (ideal facto).
If r is much larger than 1, it is desirable to make the values shown in both graphs.

Next, with reference to FIGS. 51A to 51F, a method of forming an upper portion of the semiconductor device in which the gate electrode 6 is arranged in the trench will be described.

First, a mixed film 51 of Ti and Si is formed on the n-type semiconductor layer 2 made of SiC by co-sputtering (FIG. 51A). Next, an oxide film 52 serving as a mask for the trench RIE is selectively formed thereon by CVD (FIG. 51B). Next, a trench 53 is formed in the n-type semiconductor layer 2 made of SiC by RIE, and an oxide film 52 is formed.
Is removed (FIG. 51 (c)).

Next, by heat treatment (sintering), Ti
The mixed film 51 of Si and Si is silicided to form a silicide layer 54, and the side wall of the trench 53 is oxidized to form a gate insulating film 55 (FIG. 51D). next,
Polysilicon doped with impurities in the trench 53 is used as a buried gate electrode 56 (FIG. 51E).

Next, an interlayer insulating film 57 made of a silicon oxide film is formed by CVD. Next, the silicide layer 54
The upper insulating films 55 and 57 are removed, and an Al layer 58 for wiring is formed so as to contact the silicide layer 54 (FIG. 51F).

The method shown in FIGS. 51A to 51F can be changed to the following mode.

First, a mixed film 51 of Ti and Si is formed on the semiconductor layer 2 by co-sputtering (FIG. 51).
(A)). Next, the mixed film 51 of Ti and Si is silicided by heat treatment (sintering) to form a silicide layer 5.
4 is formed. An oxide film 52 serving as a mask for the trench RIE is selectively formed thereon by CVD (FIG. 51).
(B)). Next, a trench 5 is formed in the semiconductor layer 2 by RIE.
3 is formed, and the oxide film 52 is removed (FIG. 51C).

Next, the trench 53 and the silicide layer 54
A polysilicon film is formed on the surface of the substrate and is oxidized to form a gate oxide film 55. In this case, the oxidation proceeds to the inside of the surface of the semiconductor layer 2. That is, the gate oxide film 5
5 is formed of an oxide film of polysilicon and an oxide film of SiC.

The polysilicon film is oxidized to form a gate oxide film 55.
In this case, the method of making the oxidation proceed to the surface of the SiC layer 2, that is, the method of forming the gate oxide film 55 by the polysilicon oxide film and the SiC oxide film is only a trench type device. Instead, the present invention can be applied to the above-mentioned planar type device. Further, the method of forming the trench 53 after the formation of the Schottky electrode 4 (silicide layer 54) can be applied as it is even when a metal thin film is used as the Schottky electrode 4.

Next, a method of forming the upper portion of the semiconductor device in which the p-type layer 8 is arranged below the trench will be described with reference to FIGS. This method is shown in FIGS.
(F) The method shown is partially modified.

After forming the trench 53, the trench 53
Implant boron into the SiC layer 2 under the trench 53 to form an implant layer 61 (FIG. 52).
(C)). Boron in the implant layer 61 is diffused by a heat treatment performed thereafter, whereby the p-type layer 8 is formed below the trench 53. Other steps are shown in FIG.
(A) to (f) are the same as the illustrated methods.

The semiconductor device according to the embodiment of the present invention described above is particularly effective for power and high frequency, but is also effective as a memory cell switching device.

Note that the present invention is not limited to the above embodiment. For example, when a p-substrate is used instead of an n-type substrate, the semiconductor device performs an IGBT operation.
The features of the vertical device according to each embodiment can also be applied to a horizontal device. In addition, various modifications can be made without departing from the scope of the present invention.

[0179]

According to the present invention, by applying a voltage to the control electrode (gate electrode) to lower the height of the Schottky barrier, a main current flows in the device, so that the channel becomes Since it does not exist, it is possible to prevent an increase in on-voltage due to channel resistance. Furthermore, since the diffusion layer is basically unnecessary, there is no problem that the manufacturing time of the device is long.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a potential distribution of the semiconductor device in a cross section taken along line II-II of FIG.

FIG. 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 12 is a plan view of a semiconductor device according to still another embodiment of the present invention.

FIG. 13 is a sectional view taken along the line XIII-XIII in FIG. 12;

14 is a sectional view taken along the line XIV-XIV in FIG.

FIG. 15 is a plan view of a semiconductor device according to still another embodiment of the present invention.

FIG. 16 is a sectional view taken along the line XVI-XVI in FIG. 15;

FIG. 17 is a sectional view taken along the line XVII-XVII in FIG. 15;

FIG. 18 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 19 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 20 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 21 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

FIG. 22 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 23 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 24 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 25 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 26 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 27 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 28 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 29 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 30 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

FIG. 31 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

FIG. 32 is a diagram showing an inversion layer formed when a negative bias voltage is applied to the gate electrode in the blocking state of the semiconductor device shown in FIG. 31;

FIG. 33 is a view showing an electric field distribution of the semiconductor device shown in FIG. 32;

FIG. 34 is a band diagram of the semiconductor device shown in FIG. 32;

FIG. 35 is a plan view of a structure embodying the semiconductor device shown in FIG. 31;

FIG. 36 is a sectional view taken along lines S1-S1 and S2-S2 of FIG. 35;

FIG. 37 is a cross-sectional view of a conventional power MOSFET.

FIG. 38 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

39 is a sectional view sequentially illustrating a method of forming the upper portion of the semiconductor device shown in FIG. 38;

40 is a cross-sectional view showing another method of forming the upper portion of the semiconductor device shown in FIG. 38 in order;

FIG. 41 is a sectional view showing still another method of forming the upper portion of the semiconductor device shown in FIG. 38 in order;

FIG. 42 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

FIG. 43 is a cross-sectional view showing a method of forming the upper portion of the semiconductor device shown in FIG. 42 in order;

44 is a cross-sectional view showing another method of forming the upper portion of the semiconductor device shown in FIG. 42 in order;

FIG. 45 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

46 is a sectional view sequentially illustrating a method of forming the lower portion of the semiconductor device shown in FIG. 45;

FIG. 47 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

FIG. 48 is a sectional view of a semiconductor device according to still another embodiment of the present invention;

FIG. 49 is a graph showing a relationship between a bulk width between trenches and its impurity concentration in the semiconductor device shown in FIG. 48;

50 is a graph showing the relationship between the bulk width between trenches and the breakdown voltage of the element in the semiconductor device shown in FIG. 48.

FIGS. 51A and 51B are cross-sectional views sequentially illustrating a method of forming an upper portion of a semiconductor device in which a gate electrode is arranged in a trench.

FIGS. 52A to 52C are cross-sectional views sequentially illustrating a method of forming an upper portion of a semiconductor device in which a p-type layer is arranged below a trench.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Low resistance n-type semiconductor layer (substrate) 2 ... N-type semiconductor layer 3 ... Drain electrode (2nd main electrode) 4 ... Source electrode (1st main electrode) 5 ... Gate insulating film 6 ... Gate electrode (control electrode) 11 low-resistance p-type semiconductor layer (substrate) 12 low-resistance n-type semiconductor layer 13 insulating substrate

Continuation of the front page (56) References JP-A-7-30112 (JP, A) JP-A-2-7571 (JP, A) JP-A-62-274775 (JP, A) JP-A-4-179268 (JP) , A) JP-A-4-29368 (JP, A) JP-A-59-119045 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/334- 21/336

Claims (9)

(57) [Claims] 1. A first conductive type first having a flat common surface.
A semiconductor layer; a first main electrode provided on the common surface and Schottky-joined to the first semiconductor layer; a second main electrode connected to the first semiconductor layer; A Schottky barrier at a portion of the Schottky junction corresponding to an edge of the first main electrode, which is disposed so as to face the first semiconductor layer via the provided insulating film and to be adjacent to the Schottky junction And a control electrode for controlling the height of the Schottky barrier at the edge by a turn-on voltage to the control electrode in a state where a voltage is applied between the first and second main electrodes. When the height is lowered, the device is turned on, and a current flows between the first and second main electrodes through the first semiconductor layer; and between the first main electrode and the first semiconductor layer. With A first interface forming a Ttoki junction, wherein a second interface between the insulating film and the first semiconductor layer, and that are arranged on substantially the same plane on said common surface, said first One main electrode includes the control electrode, the first semiconductor layer,
An extension portion sandwiched between the
The semiconductor device is formed by the extension . 2. The semiconductor device according to claim 1, further comprising a second semiconductor layer of a first conductivity type and a low resistance disposed on said first semiconductor layer, wherein said second main electrode is in ohmic contact with said second semiconductor layer. The semiconductor device according to claim 1 , wherein: 3. The semiconductor device according to claim 1, further comprising a second semiconductor layer of a second conductivity type and a low resistance disposed on said first semiconductor layer, wherein said second main electrode makes ohmic contact with said second semiconductor layer. The semiconductor device according to claim 1 , wherein: 4. When the height of the Schottky barrier is lowered, the semiconductor device according to any one of claims 1 to 3, characterized in that electrons in the first semiconductor layer from the edge is injected . 5. The semiconductor device according to claim 1 , wherein said extension portion is made of a thin metal film having a thickness of 0.2 μm or less. 6. An apparatus according to claim 1, wherein said extension portion is tapered toward its tip .
The semiconductor device according to. 7. The extended portion has a width smaller than that of the control electrode, and when a height of the Schottky barrier is increased by a turn-off voltage, a current path below the extended portion is connected to the control electrode. claims 1 to 6 by the application of the turn-off voltage, characterized in that it is pinched off by the inversion layer of the second conductivity type induced in the first semiconductor layer
The semiconductor device according to any one of the above. 8. The semiconductor device according to any one of claims 1 to 7, characterized in that said first conductivity type is n-type. Wherein said first semiconductor layer, SiC, CdS, and a semiconductor device according to any one of claims 1 to 8, characterized in that it consists of a material selected from the group consisting of diamond.