JP3317794B2 - PLL circuit and frequency pull-in method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase
Locked Loop (Phase Synchronization) Circuit and PLL
More specifically, the present invention relates to a method for acquiring a frequency of a circuit, and more specifically, a network synchronous oscillator, a clock extractor in digital transmission, an FM (PM) detector, and the like, which can be used for delineating a stable frequency signal synchronized with an input signal and detecting a phase of the input signal. The present invention relates to a PLL circuit and a frequency pull-in method applicable to a PLL circuit.

[0002]

2. Description of the Related Art One of conventional applications of a PLL circuit is clock multiplication. Current controlled oscillator (I
In the case where a multivibrator is used for a voltage controlled oscillator (CO) or a voltage controlled oscillator (VCO), the oscillation frequency is determined by the built-in capacitance C and the current I for charging it. In order to oscillate at a high frequency, C is reduced or I
It is necessary to take a measure of increasing the value of C. However, if C is reduced, a problem occurs in terms of variations in oscillation and the like. On the other hand, when I is increased, a problem occurs in terms of current consumption. Therefore, when it is necessary to oscillate at a high frequency, a ring oscillator (ring oscillator) may be used instead of the multivibrator. Since the oscillation frequency of a ring oscillator is determined by the total delay time of the inverters constituting the ring oscillator, a system using the ring oscillator is generally called a Delayed Lock L.
An OOP (DLL) circuit (delay synchronization circuit) is called.

As shown in FIG. 13, a conventional DLL circuit has a phase comparator 1 and a loop filter 2 like a PLL circuit, and is composed of a ring oscillator 3 and a frequency divider 4 with a fixed number of stages. The ring oscillator 3 has the feature that the free-running frequency increases as the number of stages decreases, and the determination of the number of stages is an important point in designing. In the prior art, since the number of stages is a fixed ring oscillator, the oscillation frequency is controlled only by the control voltage (or current) of the ring oscillator.

[0004]

However, the prior art as described above has a drawback that the frequency range of the input signal is limited to a narrow range because the number of stages of the ring oscillator is fixed. Therefore, the delay of the inverter constituting the ring oscillator changes due to the fluctuation of the process or the temperature, so that the control range of the frequency to be locked may be exceeded, which makes the design difficult.

[0005] Further, if an attempt is made to provide a wide lock range, the gain of the ring oscillator becomes large, so that the input sensitivity of the system becomes high and jitter may be a problem.

On the other hand, Japanese Patent Laid-Open Publication No. Hei 3-259609 discloses a PLL circuit having a phase comparator, a loop filter, and a ring oscillator having a variable number of stages. The feature is that a stage number selector for selecting the number of stages of the ring oscillator based on its input voltage is provided, and the number of stages is reduced when outputting a high frequency. This aims to stabilize the oscillation of the ring oscillator and to suppress phase jitter, rounding of the oscillation waveform at low frequencies, and the like. However, since the proposed frequency pull-in method of the PLL circuit is an ordinary method, the pull-in speed is not so high. In addition, there is a problem to be solved that the number of stages may be changed due to noise or the like after the frequency is pulled.

[0007] The present invention has been made in view of the above points, and an object of the present invention is to expand a lock range, which was limited to a narrow range in the prior art, regardless of the process and temperature. An object of the present invention is to provide a PLL circuit which suppresses a sharp change in gain caused by a change in the number of stages of a ring oscillator, suppresses an increase in input sensitivity, and solves a characteristic deterioration due to jitter.

Another object of the present invention is to determine the optimum number of stages in a PLL system by incorporating a frequency adjustment circuit in the system, and to determine the frequency in a period according to the architecture of the frequency adjustment circuit regardless of the loop filter capacity. It is an object of the present invention to provide a frequency lock-in method for a PLL circuit, which can speed up the frequency lock-in by pulling in the clock.

Another object of the present invention is to provide a PLL circuit which can be used in a digital / analog mixed LSI (large-scale integrated circuit) by reducing the noise of the ring oscillator.

Another object of the present invention is to provide a PLL circuit characterized in that the current consumption does not increase even if the locking frequency increases.

[0011]

In order to achieve the above object, a PLL circuit according to the present invention is a PLL circuit having a phase comparator, a loop filter, and a ring oscillator having a variable number of stages. Input setting means for setting, initial reset means for setting the ring oscillator to the maximum number of stages and switching to a setting signal from the input setting means at its input, and counting down pulses of the phase comparator every predetermined period, When the count value does not reach a preset value, the number of stages of the ring oscillator is reduced by one each time, and when the count value reaches a preset value, the number of stages of the ring oscillator is locked and an input thereof is made. Frequency pulling means for switching to a signal from the loop filter. To.

[0012] In one aspect of the present invention, preferably, input limiting means for limiting an input supplied to the ring oscillator in proportion to the number of stages of use of the ring oscillator is provided. Can be.

According to another preferred embodiment of the present invention, each stage of the ring oscillator is constituted by a differential inverter having a constant current.

According to another preferred embodiment of the present invention, a current consumption reducing means for reducing the current consumption of the unused stage of the ring oscillator is provided.

According to another aspect of the present invention, preferably, a voltage-current converter is provided between the loop filter and the ring oscillator.

The frequency pull-in method for a PLL circuit according to the present invention is the frequency pull-in method for a PLL circuit having a phase comparator, a loop filter, and a ring oscillator having a variable number of stages. Fix the input of the oscillator to a predetermined value and
After the L circuit is started, the number of stages of the ring oscillator is sequentially reduced at predetermined intervals to increase its output frequency, and when the value of the output frequency rises to a value exceeding the reference frequency, the number of stages is reduced. The reduction is stopped, and the input of the ring oscillator is switched to the output of the loop filter.

[0017]

According to the present invention, the frequency of the input clock is compared with the frequency of the clock output from the ring oscillator, and
A wide lock range is achieved by combining a frequency adjustment circuit, which is a frequency pull-in device with the function of determining the optimal number of ring oscillator stages, and a ring oscillator that has a switch at each output stage so that it can oscillate with any number of stages. And high-speed frequency acquisition. Furthermore, the use of a current-constant fully-differential inverter as the ring oscillator realizes low noise of the PLL circuit.

By utilizing the control signal from the frequency adjustment circuit as a signal for powering down the inverter in the ring oscillator that has become unnecessary, it is possible to suppress an increase in current consumption. An oscillation frequency is obtained.

By obtaining information on the number of stages from a ring oscillator stage number monitor circuit having a function of monitoring the number of ring oscillator stages in response to a control signal from the frequency adjustment circuit and controlling the amount of current supplied to the ring oscillator, Input sensitivity is suppressed.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration of a PLL circuit according to an embodiment of the present invention. In FIG. 1, 11 is a phase comparator, 12 is a loop filter, 13 is input setting means, 14 is a voltage-current converter, 15 is a ring oscillator, and 16 is a 1 / N divider. Reference numeral 17 denotes a frequency lock-in means, which comprises a frequency adjustment circuit 18 and a ring oscillator stage number monitor 19. The contents of the signals in FIG. 1 are as shown in the table below.

[0022]

[Table 1] REF CLK Reference clock (basic frequency, pull-in frequency) UP Frequency up signal (up pulse) DW Frequency down signal (down pulse) LOOK OUT Output signal from loop filter RLOCK Ring oscillator fixed signal (stage lock signal) FCLK Frame clock (stage number reduction signal) RCLK Clock output from ring oscillator (output frequency) GM OUT Signal obtained by converting the output of loop filter to VI MCLK Master clock GM CONT GM control signal of voltage-current converter Main The main feature of the PLL circuit of the present invention is that frequency pull-in can be performed at high speed. The overall operation of the embodiment including this point will be described with reference to the block diagram of FIG. 1 and the frequency pull-in operation chart of FIG.

(1) Basic Operation The ring oscillator 15 is set to the maximum number of stages by an automatic reset operation at the start, and the input of the ring oscillator 15 is switched to the input setting means 13.

The voltage value set in the input setting means 13 is, for example, 3/5 V _DD ,
Is a suitable intermediate number of stages, the pull-in frequency (reference frequency R
Output frequency (RCLK) slightly higher than (EFCLK)
It is a level that gives out. However, at the maximum number of stages, the output frequency based on that value is significantly lower than the reference frequency.

Frequency adjusting circuit 1 of frequency pull-in means 17
Numeral 8 counts down pulses DW every predetermined period, and when it does not reach a preset value, issues a pulse (FCLK) for lowering the number of stages of the ring oscillator 15 by one each time, resets it, and resets the down pulse again. Start counting. When the down pulse for each predetermined period reaches a preset value, a signal (RLOCK) for locking the number of stages of the ring oscillator 15 is output, and the input is switched to a signal from the loop filter 12.

At the start, since the output frequency of the ring oscillator 15 is lower than the corresponding reference frequency, only the up pulse UP is output from the phase comparator 11. Therefore,
The number-of-stages decreasing signal FC from the frequency pull-in means 17 every predetermined period
LK is output, and as shown in FIG.
The number of stages of 5 decreases, and the output frequency increases accordingly.

The output frequency RCLK is equal to the reference frequency REF.
From the vicinity of exceeding CLK, the down pulse DW starts to be output from the phase comparator 11. Then, when the down pulse DW reaches a preset value (for example, 8 down clocks) within a predetermined period (for example, 32 reference frequencies), an RLOCK signal is output from the frequency pull-in means 17 and the ring oscillator 15 is turned on. The number of stages is locked, the input is switched to the loop filter 12, and the frequency is pulled. However, at this time, since the output frequency of the ring oscillator 15 is slightly higher than the pull-in frequency,
It will be a rough pull-in. Thereafter, the output is locked to the output frequency corresponding to the reference frequency by the normal operation of the phase comparator 11.

(2) Others The frequency pull-in means 17 detects whether or not the down pulse DW for each predetermined period reaches a preset value when the output frequency of the ring oscillator 15 is close to the reference frequency. Even when the frequency is lower than the reference frequency, a down pulse may be generated, or an up-down alternate pulse may be generated, so that a single down pulse may cause a malfunction.
For example, a lock signal is issued only after counting eight down pulses.

The ring oscillator 15 is connected to the loop filter 12 via a voltage-current converter (VI) 14. However, if the ring oscillator 15 is of a type that performs a voltage input operation or has a voltage-to-current converter at its input portion, this voltage-to-current converter 1
Of course, 4 can be omitted.

In the embodiment of the present invention, the voltage-current converter 1
4 on the input side.
Has been switched. In this example, when the input setting means 13 is connected before the pull-in, the input value of the ring oscillator 15 is fixed to the set value regardless of the output of the loop filter 12. Then, the pull-in operation (R
Immediately after the LOCK signal is performed, since the set value level is accumulated in the capacitor of the loop filter 12, the level shifts to the normal PLL operation from the level.
There is an advantage that there is no discontinuity due to switching.

However, also in this example, the current set value from the current source can be directly input to the input portion of the ring oscillator 15, and even in this case, the ring oscillator 1
Depending on the capacity of the input unit of No. 5, it is possible to make a smooth transition.

Next, the inside of each circuit of FIG. 1 will be described in detail.

The phase comparator 11 and the frequency adjusting circuit 18 compare the frequencies of REFCLK and RCLK within the period determined by the phase comparator 11, and if the frequency of REFCLK is higher, the number of stages of the ring oscillator 15 is reduced. If the frequency of REFCLK is lower by one, the frequency adjustment circuit 1 operates with an architecture of fixing the number of stages of the ring oscillator 15 there.
By incorporating 8 into the system, it is possible to select the optimal number of ring oscillator stages. While the frequency adjustment circuit 18 is operating, the ring oscillator 1
Control voltage (or control current) that changes the operation speed of 5
GM OUT is fixed to a certain value.

FIG. 3 shows a configuration example of the phase comparator 11 of FIG. 1, and FIG. 4 shows a configuration example of the frequency adjustment circuit 18 of FIG.
FIG. 5 shows input / output signal timings of these circuits.

The phase comparator 11 shown in FIG.
A circuit in which the DW signal is active when the frequency of DCLK is faster or the phase is advanced compared to EFCLK, while the UP signal is active when the frequency of DCLK is slow or delayed. is there.

The DW8 count block 182 shown in FIG.
Is a block for counting the DW signals from the phase comparator 11, and when eight DW signals have been counted, the ring oscillator 1
The clock (FCLK) for changing the number of stages of 5 is disabled, and RLOCK is enabled (e
enabled). The DW8 count block 182 is composed of a plurality of flip-flops, and MCLK is REFC
This is a master clock having a higher frequency than LK. REFC
The LK32 count block 181 sets REFCLK to 32.
In this block, REFCLK
And a period for measuring the frequency of DCLK.

That is, the DW signal is set to 8 during 32 clocks.
If it is less than one, add the frame clock and reduce it by one step,
If the number of stages of the next ring oscillator 15 is set, and if DW ≧ 8 within the frame period, the RLOCK is output when eight DW signals have been counted, and the frequency adjustment circuit 18 sets the number of stages of the ring oscillator to be fixed. Function.

Loop Filter 12 As shown in FIG. 6, the loop filter 12 is a block for converting the UP / DW signal from the phase comparator 11 into a control voltage for the ring oscillator 15. Loop filter 12
When the UP signal is active, SW1 is turned on, and the current IUP charges the capacitor Cloop. D
When the W signal is active, SW2 is turned on and the current IDW discharges the capacitor Cloop. As described above, the current can be converted to the control voltage LOOP OUT of the ring oscillator 15 by the UP / DW signal.

Voltage-to-Current Converter 14 The voltage-to-current converter 14 is a circuit having a function of converting the control voltage LOOP OUT to the control current GM OUT. The circuit diagram is shown in FIG. FIG. 11 shows the output characteristics of the voltage-current converter 14.

Ring Oscillator 15 Next, the function of the ring oscillator 15 will be described.
In this embodiment, an eleven-stage ring oscillator 15 as shown in FIG. 7 is employed. Since the ring oscillator 15 includes the inverter 151 having a constant current, low noise can be expected. FIG. 8 shows a configuration example of the inverter 151.

At the time of resetting, the ring oscillator 15
Only W11 is ON, other SW (switch) is OF
F, which constitutes an 11-stage ring oscillator.

When the reset is released, the oscillation starts from the state of the 11-stage ring oscillator. Frame clock F
The data of the shift register 150 changes according to CLK, and the position of the SW to be turned on changes. As a result, the number of stages of the ring oscillator changes. In addition, if the number of stages is changed and the ring oscillator becomes unnecessary (in the case of an eight-stage ring oscillator, the ninth to eleventh inverters), if a power-down monitoring shift register is prepared, it is powered down by a signal from the shift register. be able to. Therefore, there is an advantage that current consumption does not increase even if the frequency increases.

1 / N frequency divider 16 The function of the block of the 1 / N frequency divider 16 will be described.
In this embodiment, N = 32. As shown in FIG. 9, the frequency divider 16 has a 1/8 frequency divider 161 and a 1/4 frequency divider 162, and the frequency divider 16 divides the clock RCLK output from the ring oscillator 15 by 1/8. The master clock (MCLK) is generated by dividing the frequency, and the clock is further divided by 1/4 to generate DCLK.

Ring Oscillator Stage Number Monitor 19 As shown in FIG.
Monitors the number of stages of the ring oscillator 15 and
It has a function of giving the required dI / dV to the voltage-current converter 14 in the number of stages. That is, only the two bits of the count output are used by using the 4-bit counter 191, and the gain of the voltage-current converter 14 is changed by the 2-bit signal.

The above function of the ring oscillator stage number monitor 19 makes it possible to suppress an abrupt increase in gain (dFreq./dI) caused by a change in the stage number of the ring oscillator 15. This is equivalent to lowering the input sensitivity of the ring oscillator 15. That is,
Even if noise enters the ring oscillator 15, the gain is the signal GMO from the ring oscillator stage number monitor 19.
Since it is suppressed by the UT, it is possible to make it difficult to cause jitter.

(System Operation) Next, the system operation of the PLL circuit of this embodiment will be described with reference to the flowchart of FIG. Before being locked to a certain clock, it must be reset (S0). At this time, the ring oscillator 1
Reference numeral 5 denotes the maximum number of stages (for example, 11 stages in the case of an 11-stage ring oscillator), and the potential of Loop out is the output from the reference voltage source V _REF (S1).

Until RLOCK = H, for example, if the reference potential is 3/5 V _DD , Loop out = 3
/ 5V _DD is fixed and V _REF = 1 / 2V _DD , Lo
Under the condition of opout = 3 / 5V _DD , R
The frequencies of EFCLK and DCLK will be compared. During the period of RLOCK = L, no matter how large the capacitance attached to the loop filter 12, the frequency can be roughly drawn regardless of the capacitance. In this embodiment, 32
The number of DWs is counted using REFCLK as one frame (S2).

If DW <8 in the current frame (S3), the number of stages of the ring oscillator 15 is reduced by one in the next frame (S4), the counter 182 for counting the DW is reset (S2), and the number of DWs is again determined. Count.

When DW = 8 (S3), RLOCK = H is immediately established, and the number of stages of the ring oscillator 15 is fixed. Then, Loop out is switched to the output from the loop filter 12, and a normal pull-in operation is performed. The capacity of the loop filter 12 is RLOCK
= H, the battery is charged to 3/5 V _DD , and the normal pull-in operation is Loop out = 3/5 V _DD (the reference potential is 3
/ 5V _DD ) (S
6).

When DW <8 even if the number of stages of the ring oscillator 15 is two, if the current condition (V
_REF = 1 / 2V _DD and Loop out = 3 / 5V _DD )
Cannot be locked (S5).

In the above description, the maximum time required for rough frequency pull-in is

[0052]

## EQU1 ## 32REFCLK × 9 = 288REFCLK. This does not depend on the capacity of the loop filter 12. When DW = 8, the reason for setting RLOCK = H is that DLOCK is set due to the phase relationship between REFCLK and DCLK.
Even if the frequency of CLK is low, DW may appear,
This is to eliminate this.

[0053]

As described above, according to the present invention,
Since the frequency adjusting circuit as the frequency pull-in means is combined with the ring oscillator having a variable number of stages, it is possible to obtain the frequency pull-in in a wide lock range and at a high speed operation. Further, the frequency can be quickly pulled in with a certain number of clocks regardless of the capacity of the loop filter.

Further, according to the present invention, noise reduction can be realized by using a current-constant fully-differential inverter as an inverter constituting the ring oscillator. Further, by powering down unnecessary inverters, oscillation can be performed with low current consumption even during high-speed operation. Further, the signal from the ring oscillator stage number monitor is dI / d
By controlling V (GM), the input sensitivity of the PLL circuit can be suppressed, and jitter caused by noise can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a PLL circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration example of a phase comparator of FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of a frequency adjustment circuit of FIG. 1;

FIG. 5 is a timing chart showing an operation of the frequency adjustment circuit of FIG. 4;

FIG. 6 is a circuit diagram illustrating a configuration example of a loop filter of FIG. 1;

FIG. 7 is a circuit diagram showing a configuration example of a ring oscillator of FIG. 1;

8 is a circuit diagram showing a configuration example of an inverter of the ring oscillator of FIG. 7;

FIG. 9 is a block diagram illustrating a configuration example of a 1 / N frequency divider of FIG. 1;

FIG. 10 is a circuit diagram illustrating a configuration example of a voltage-current converter and a ring oscillator stage number monitor of FIG. 1;

FIG. 11 is a graph showing output characteristics of the voltage-current converter of FIG.

FIG. 12 is a flowchart showing an operation procedure of the PLL circuit according to one embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 11 phase comparator 12 loop filter 13 input setting means 14 voltage-current converter 15 ring oscillator (ring oscillator) 16 1 / N divider 17 frequency pull-in means 18 frequency adjustment circuit 19 ring oscillator stage number monitor 20 reference voltage generation circuit 150 Shift register 151 Constant current inverter 161 1/8 frequency divider 162 1/4 frequency divider 181 REFCLK32 count block 182 DW8 count block 191 4-bit counter

Claims (6)

(57) [Claims] 1. A PLL circuit having a phase comparator, a loop filter, and a ring oscillator having a variable number of stages, an input setting means for setting an input of the ring oscillator to a predetermined value, and setting the ring oscillator to a maximum number of stages. Initial reset means for switching to a setting signal from the input setting means as an input; counting down pulses of the phase comparator at predetermined time intervals; and each time the count value does not reach a preset value, the ring oscillator is used. Frequency step-up means for reducing the number of stages by one stage, locking the number of stages of the ring oscillator when the count value reaches a preset value, and switching the input to a signal from a loop filter. PLL circuit. 2. An apparatus according to claim 1, further comprising input limiting means for limiting an input supplied to said ring oscillator in proportion to the number of stages of said ring oscillator.
3. The PLL circuit according to 1. 3. The PLL circuit according to claim 1, wherein each stage of said ring oscillator is constituted by a differential inverter having a constant current. 4. The PLL circuit according to claim 1, further comprising current consumption reduction means for reducing current consumption of a stage which is not used because of being reduced in said ring oscillator. 5. The PLL circuit according to claim 1, wherein a voltage-current converter is provided between said loop filter and said ring oscillator. 6. A frequency lock method for a PLL circuit having a phase comparator, a loop filter, and a variable number of ring oscillators, wherein the number of the ring oscillators is set to a maximum number and the input of the ring oscillator is fixed to a predetermined value. After starting the circuit, the number of stages of the ring oscillator is reduced one after another at predetermined intervals to increase its output frequency, and when the value of the output frequency rises to a value exceeding the reference frequency, the number of stages is reduced. And switching the input of the ring oscillator to the output of the loop filter.