JP3312551B2 - Level shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter (level shifter) for converting an input signal having a narrow logic amplitude of, for example, 3V into an output signal having a wide logic amplitude of, for example, 30V.
About.

[0002]

2. Description of the Related Art For example, a liquid crystal driving IC (liquid crystal driver)
In addition to the power transistor in the output stage, a level shift circuit for converting a low voltage level selection signal into a high voltage level liquid crystal drive voltage is built in. Conventionally, as this level shift circuit, a low power consumption type flip-flop circuit configuration in which two CMOS stages are connected and feedback is applied as shown in FIG. That is,
The level shift circuit 10 shown in FIG.
V (= Vss) to 3V (= Vdd)) A negative logic 3 (3V = Vdd−Vss) from a logic input signal V _{IN with a} negative logic amplitude
CMOS inverter I for generating V-system inverted signal V _IN ^*
NV1, a first N-channel MOSFET (first switch MOS) 1 for pull-down that opens and closes with a logical input signal V _IN , and the first N-channel MOSFET 1 exclusively with an inverted signal V _IN ^* Pull-down second N-channel MOSFET (second switch MO
S) 2 and, for example, 30 V (0 V (Vss) to 30 V (Vcc))
A first P-channel MOSFET 3 which is connected to the first N-channel MOSFET 1 by a totem pole connection (series connection) between the high voltage power supplies and is closed by closing the second N-channel MOSFET 2, and 30 V (0 V (0 V Vss) to 30V
(Vcc)) a second N-channel MOSFET 2 between power sources
Connected to the totem pole and the first N-channel type M
A second P-channel MOSFET 4 that is closed by closing the OSFET 1.

Here, the first P-channel type MOSFET
3 and the second P-channel MOSFET 4
A flip-flop (bistable circuit) FF in which nodes (storage nodes) N ₁ and N ₂ are cross-connected to their gates is formed. The wide logic amplitude output signal V _out of the level shift circuit 10 is now taken from the drain node N ₂ , and its inverted output signal V _out ^* appears at the drain node N ₁ .

In the level shift circuit 10 having such a basic configuration, when the logic input signal _VIN rises from a low level 0V (= Vss) having a narrow logic amplitude to a high level 3V (= Vdd), the first N channel The MOSFET N1 is closed and the inverted signal V _IN ^* of the opposite phase falls to 0V (= Vss), so that the second N-channel MOSFET 3 is opened in reverse. The drain node N ₁ of the flip-flop FF is closed by closing the first N-channel MOSFET _2.
(Vss) is supplied to the second N-channel MOSFET and the voltage is determined as a low level with a wide logic amplitude.
3 of the voltage at the drain node N ₂ by opening becomes once floated indefinite, the by placing the voltage 0V at the node N ₁ 2
The P-channel MOSFET 4 is closed, the drain node N ₂ is directly connected to the high-level voltage 30 V having a wide logic amplitude.
(= Vcc). As a result, the first P-channel MOSFET 3 is opened. Therefore, the P-channel type MO of the output stage whose gate is connected to the drain node N ₂
SFET5 opens.

Conversely, when the logic input signal V _IN is at a high level of 3V
When the voltage drops from (= Vdd) to the low level 0V (= Vss), the first N-channel MOSFET 1 opens and the second N-channel MOSFET 3 closes. Flip-flop 0V to the drain node N ₂ of the FF (= Vss) is is fed a voltage determined as a low level of a wide logic amplitude, the drain node voltage of N ₁ is a temporarily unstable floating, node N the _second determined voltage 0V since the first N-channel type MOSFET3 is closed, the drain node N ₁ is immediately wide logic amplitude high level voltage 30
V (= Vcc) is determined. As a result, the second P-channel MOSFET 4 is opened. Therefore, the P-channel MOSFET 5 in the output stage is closed.

Thus, in the level shift circuit 10,
Low level 0V (Vss) to high level 30V (Vcc) wide logic amplitude logical output signal with respect to the step waveform of the logic input signal _{VIN having} a low level 0V (Vss) to high level 3V (Vdd). A step waveform of V _OUT is obtained.

The above-described level shift circuit 10 includes a pre-stage circuit (not shown) for generating a logical input signal V _IN and an M-stage output stage.
Together with the OSFET 5, it is monolithic as a semiconductor integrated circuit (IC). Therefore, from the viewpoint of cost merit due to the reduction of the manufacturing process and the like, it is desirable that all the gate insulating films of the MOSFETs in one chip are formed to have the same thickness. However, the potentials of the drain nodes (storage nodes) N ₁ and N ₂ of the flip-flop FF in the level shift circuit 10 are changed to the switches MOS ₁ and MOS ₁ .
Because it is reset to 0V (Vss) alternately by opening and closing of 2,
First P-channel MOSFET 3 and second P-channel MOSFET 4 constituting flip-flop FF
In the MOSFET 5 at the output stage, the voltage between the source and the drain becomes a high voltage (about 30 V). Therefore, it is necessary to use a transistor having a high breakdown voltage structure in which an offset gate type low concentration drain region is formed. High voltage (approx.) Between source, gate-drain, gate-subslate
30V) is applied, so that the MO
The gate insulating films of the SFETs 3, 4, and 5 must be formed thicker than the gate insulating films of the MOSFETs of the other low-voltage control circuits.

The MOSFETs 3 and 4 and the output transistor 5
In order to keep the breakdown voltage between the gate-source, gate-drain, and gate-subslate within 3 V, a level shift circuit 20 shown in FIG. 8 is proposed. That is, the level shift circuit 20 is different from the level shift circuit 10 shown in FIG. 7 in that the first P-channel MOSFET 3 and the second P-channel MOSFET
The configuration is such that the gate of ET4 is connected to a 30 V (Vcc) high voltage power supply via constant voltage diodes D ₁ and D ₂ for diode clampers.

Assuming that the zener voltage V _Z of these constant voltage diodes D ₁ and D ₂ is about 3 V, the first N-channel type M
OSFET1 even if closed, the drain node N ₁ by a voltage clamping zener diode D ₂ is Vcc-V _Z =
The second P-channel type MOSF
ET4 gate-source, gate-drain, gate-
The voltage between the substrates falls within 3V. Similarly,
Be closed second N-channel type MOSFET2 is, the drain node N ₂ by a voltage clamping zener diode D ₁ also does not fall to less than about 27V, the gate of the first P-channel MOSFET 3 - source, gate -Drain,
The gate-substrate voltage falls within 3V. In addition, the voltage between the gate and source and the gate and substrate of the MOSFET 5 in the output stage also falls within 3V. Flip
The gate withstand voltage of the MOSFET 5 in the output stage as well as the MOSFETs 3 and 4 of the flop FF can be 3V. Further, the source-drain voltage of the MOSFETs 3 and 4 is also 3
Within V. Since the source-drain voltages of the switch MOSs 1 and 2 and the MOSFET 5 in the output stage are applied at 3 V or more, high voltage MOSFETs such as an offset gate structure having a lightly doped drain region (element symbols are circled). Are shown).

Incidentally, the level shift circuit 1 shown in FIG.
0, when the flip-flop FF is in a stable (steady state) state, the leakage current (P-channel M
Except for the saturation currents of the OSFETs 3 and 4, current consumption does not occur in principle, and only a small through current flows through the two-stage series circuit in the transition process of the flip-flop. Therefore, power consumption is low. On the other hand, in the process of closing the first switch MOS1 in the level shift circuit 20 shown in FIG.
The current to be passed through the first switch MOS 1 is the first P-channel MOSFET 3 closed in the immediately previous stable state.
Zener the voltage enough for breakdown current causing V _Z (write current to the memory node N ₁ to the low level), and in the course of the second switch MOS2 is closed to the diode D ₂ in the saturation current than that flowing in, The second switch MO
The current to be passed to S2 is the second
P-channel type MOSFET4 to flow enough for breakdown current causing Zener voltage V _Z to the diode D ₁ in saturation current than the (writing current to the memory node N ₂ to the low level), the source of P-channel type MOSFET5 of the output stage of - at least the sum of the charging current for charging the gate capacitance (gate capacitance) C _5. Then, the first switch MO
After shifting to a stable state where S1 is a closed state,
The current to flow in the switch MOS1 well in very small current (hold current) that the diode D ₂ is sufficient to hold the Zener voltage V _Z, also after the second switch MOS2 has moved to another stable state is a closed state , Its second switch M
Current to flow in the OS2 may be a small current diode D ₁ is sufficient to hold the Zener voltage V _Z (holding current).

However, in the circuit configuration of FIG.
After the switch MOS1 has reached the stable state of the flip-flop FF in the closed state, the first switch MOS1
1, the same current value as that at the time of the state transition still continues to flow, and even after the second switch MOS2 reaches another stable state of the flip-flop FF in which the second switch MOS2 is closed,
Since the same current value as that at the time of the state transition continues to flow through the switch MOS2, the power consumption is large.

Therefore, the present applicant proposes a level shift circuit 30 including the drain current variable circuits 32 and 34 shown in FIG. This level shift circuit 30 is configured as shown in FIG.
To the level shift circuit 20 shown, a series source resistor R ₁₁ and R ₁₂ together with the first N-channel type MOSFET1 constituting a source follower circuit (constant current circuit) which operates in a non-saturation region, while the source resistance R N-channel MOSFET 6 for switching source resistance that shorts ₁₂
When, the switching timed pulse P1 having a predetermined pulse width [Delta] T ₁ at time t ₁ the logic input signal V _IN rises MOSFET6
Source resistors R ₂₁ and R ₂₁ forming a source follower circuit (constant current circuit) together with a one-shot circuit (monostable multivibrator) 7 applied to the gate of the transistor and a second N-channel MOSFET 2 operating in an unsaturated region. ₂₂ and
Source resistance switching N-channel type MOSFET8 to short the source resistance R ₂₂ one of its logic input signal V
Predetermined pulse width [Delta] T ₂ at time t _{2 when IN} falls (= [Delta] T
_And a one-shot circuit 9 for applying the switching timed pulse P2 of ₁ ) to the gate of the MOSFET 8.

The first N-channel MOSFET 1, the source resistors R ₁₁ and R ₁₂ , the N-channel MOSFET 6 for switching the source resistance and the one-shot circuit 7 constitute a first drain current variable circuit 32, and the second , The source resistances R ₂₁ and R ₂₂ , the source resistance switching N-channel MOSFET 8 and the one-shot circuit 9 constitute a second drain current variable circuit 34.

The flip-flop in which the logical input signal V _IN rises
At the time point t ₁ in the state transition process of the flop FF, the MOSFET 6 is maintained in the closed state only for the period ΔT ₁ due to the generation of the switching time-limit pulse P ₁ , so that the source resistance of the first N-channel type MOSFET 1 is reduced to only the resistance R ₁₁ . since, although the drain current I _D1 flowing through the first N-channel type MOSFET1 increases rapidly, Beyond its [Delta] T ₁ period M
Since OSFET6 is then opened resistor R ₁₂ is connected in series with resistor R _11, the drain current I _D1 flowing through the first N-channel type MOSFET1 return to small current rapidly decreases. Further, the time t in another state transition process in which the logic input signal V _IN rises
₂ , the switching time pulse P2 is generated and the MOSF
Since the ET 8 is kept closed for the period ΔT ₂ , the source resistance of the second N-channel MOSFET 2 becomes the resistance R
₂₁ only, the second N-channel MOSFET 2
The drain current I _D2 flowing through the second N-channel MOSFET is rapidly increased after the ΔT ₂ period, and the MOSFET 8 is opened and the resistor R ₂₂ is connected in series with the resistor R _21.
The drain current _ID2 flowing through ET2 sharply decreases and returns to a small current. Thus, the first and second N-channel MOSFs
The drain currents I _D1 and I _D2 of the ET become a rapidly increasing drain current I _{MAX in} the transition process of the flip-flop FF, and a power saving drain current (quiescent mode current) I _{MIN in} a stable state.
This contributes to the realization of reliable state transition and reduction of power consumption.

[0015]

When the level shift circuit 30 shown in FIG. 9 is viewed as a dynamic circuit,
Drain nodes N ₁ and N _{2 of} flip-flop FF
Power P-channel type MOSFET at output stage
In 5 connected configuration, the one node source of a large capacity - so that the gate capacitance C ₅ can be seen to be in a connected state, the element of the level shift circuit 30 of large and small and the signal change Timing symmetry is necessarily broken.

That is, as shown in FIG. 9, when the gate of the P-channel MOSFET 5 in the output stage is connected to the drain node N ₂ , the first N-channel MOSFET 5 at time t ₁ .
OSFET1 is closed and the second N-channel MO
When the SFET 2 is opened, the second P-channel type MOSF
ET4 but is adapted to close, the second P-channel type MOSFET4 source - are built into the chip as a relatively large device for rapidly discharging the gate capacitance C _5. Therefore, since the second P-channel type MOSFET4 is a large element compared to the first P-channel type MOSFET 3, necessarily negligible source - gate capacitance C ₄ is parasitic.

[0017] As a result, the second N-channel type MOSFET2 at time t ₂ which falls logic input signal V _IN is closed, the first N-channel MOSFET1 is opened, the source in its initial - gate capacitance C voltage drain node N ₁ is less likely to rise because of _4, since the second P-channel type MOSFET4 are still some remains closed, rapidly drain current when the state transition flows through the second N-channel MOSFET 2 I _MAX substantially all ends up through a reactive current through the second P-channel type MOSFET 4, through a constant voltage diode D ₁ hardly flows, also element scale of a relatively large second N-channel type MOSF
Due to the low on-resistance of ET2, the first P-channel MO
Lowering of the gate voltage of SFET3 (voltage drain node N ₂₎ is delayed. For this reason, MO
SFET3 Although Vcc voltage is supplied to the node N ₂ and closed the source - because of the discharge time of the gate capacitance C _4, immediately when the second gate voltage of the P-channel type MOSFET4 not rise, Second P-channel MOSFET 4
Are opened after the second N-channel MOSFET 2 is closed.

Here, as shown in FIG. 10, the logic input signal V _IN falls and the second N-channel MOSFET 2
The second P-channel type MOSFE from time t ₂ to but is closed
Until the point in time t ₂₁ that T4 is opened is rapidly increasing drain current I _MAX
Flows as the reactive current Q1. Similarly, the logic input signal V _IN rises and the first N-channel MOSFET
From the time point t ₁ when the first P-channel type MOSF
ET3 but flows as the period is also rapidly increasing drain current I _MAX is the reactive current q1 to time t ₁₁ to open, because the gate capacitance of the first P-channel type MOSFET3 is negligible,
Period up to time t ₁ ~ time t ₁₁ is considerably shorter than the period until time point t ₂ ~ time t _21, also considerably smaller than the reactive current q1 also reactive current Q1.

The second P-channel type MOSF
Becomes the open time t ₂₁ of ET4, second N during state transition
Rapidly increasing drain current I flowing through channel type MOSFET 2
All _MAX since effectively flows through the constant voltage diode D _1, decreases the voltage V _OUT at the drain node N ₂ from the power supply voltage Vcc by the Zener voltage V _Z, the first time source - the charging to the gate capacitance C ₅ Be started.

[0020] The source - charge (charge amount Q2) of the gate capacitance C ₅ whereas short discharge by a second closing of the P-channel type MOSFET4 is momentarily a high capacity C ₅ second N-channel Since the battery is charged with a relatively large time constant corresponding to the product of the resistance of the source follower circuit including the MOSFET ₂ , the voltage of the drain node N ₂ , that is, the output signal V _OUT falls slowly with an exponential function waveform. As a result, the turn-on time T _ON of the P-channel MOSFET 5 in the output stage becomes longer, causing an imbalance with the turn-off time T _OFF, and the P-channel MOSFET 5 in the output stage becomes unbalanced.
Have poor switching characteristics.

In order to eliminate such imbalance between the turn-on time T _ON and the turn-off time T _OFF , a time t
Sources from ₂₁ - in order to rapidly charge the gate capacitance C _5, to further even larger spikes drain current I _MAX flowing through the second N-channel type MOSFET2 upon state transition, the second N-channel type MOSFET2 own device It is conceivable to increase the current capacity by making the area larger than that of the first N-channel MOSFET 1. This leads to an increase in chip size and causes an increase in the cost of the semiconductor integrated circuit. In addition to this, the following operational difficulties can be pointed out.

As described above, the second N-channel type M
Even if the current capacity of the OSFET 2 itself is increased for quick charging, the second P-channel MOSFET
Since only the first charging of the gate capacitance C ₅ is started after waiting for the fourth opening time t _21, inevitably minute charging period t ₂₁ ~t _23, will turn-on time is longer than the turn-off time, the switching speed Is bad.

Prior to that, the second P-channel type MO
Since the source-gate capacitance C ₄ parasitic on the SFET ₄ causes a time lag before the second P-channel MOSFET 4 is opened, the turn-on time is longer than the turn-off time, and the imbalance and Has become.

Output Stage P-Channel MOSFET 5
Source - for the gate capacitance C ₅ is rapid charging, as shown in FIG. 10, the second N-channel type when the state transition M
OSFET2 has a much larger surge current I _MAX ′
(> I _MAX ), the rapid increase in drain current I _MAX ′ is not changed from the time point t ₂ when the second N-channel MOSFET 2 is closed (the time point when the logical input signal V _IN rises) t ₂ . period opened up to the time t ₂₁ type MOSFET 4, since that must be previously pre-flow as a larger through-current of the two-stage series circuit (reactive current) Q1 ', rather ineffective current increases and power consumption increases I will.

Therefore, the improvement of the switching speed by shortening the turn-on time and the reduction of the reactive current at the time of the state transition are in a trade-off relationship.

In addition, since the current value variable circuit is a time switching type, the time period for switching from the rapidly increasing drain current I _MAX to the power saving drain current I _MIN (time t _11, time t ₂₃ )
Depends uniformly on the pulse widths ΔT ₁ and ΔT ₂ of the switching timed pulse P2 by the one-shot circuits 7 and 9. If the pulse width is too short, the drain current I _MIN decreases before the voltage of the nodes N _{1 and} N ₂ rises or falls sufficiently, so that the rise or fall is further delayed, and the transition time (turn-on time) , Turn-off time). If the pulse width is too long, even after the voltage of the node N _1, N ₂ dropped sufficiently rising or falling, surge drain current I _MAX because continues to flow unnecessarily, power consumption increases. However, in reality, the pulse width ΔT
₁ and ΔT ₂ must be set to be relatively long, so that the power consumption at the time of state transition becomes large.

In view of the above problems, the first aspect of the present invention
An object of the present invention is to provide a level shift circuit capable of improving the switching speed of a transistor in an output stage.

A second object of the present invention is to provide a level shift circuit capable of suppressing a rapidly increasing current value to be supplied at the time of state transition to a necessary minimum, thereby reducing power consumption.

A third object of the present invention is to provide a level shift circuit capable of suppressing a supply period of a rapidly increasing current to be supplied at the time of a state transition to a necessary minimum, thereby reducing power consumption.

[0030]

Means for Solving the Problems In order to solve the above first problem, the means taken by the present invention is to provide an output buffer circuit for rapidly charging and discharging a parasitic capacitance at a control terminal of an output stage transistor. It is. That is, the level shift circuit according to the present invention includes a first first conductivity type transistor that is controlled to open and close by a logic input having a narrow logic amplitude by a low voltage power supply, and a first transistor having an inverted input having a phase opposite to the logic input. First
A second first conductivity type transistor that is exclusively opened and closed with the conductivity type transistor;
A first second conductivity type transistor connected in series to the conductivity type transistor and controlled to be closed by closing a second first conductivity type transistor; and a second first conductivity type transistor between the high voltage power supply. A first first transistor connected in series with the transistor;
And a second second conductivity type transistor that is controlled to be closed by closing the conductivity type transistor.
In the signal voltage level conversion circuit in which the second conductivity type transistor constitutes a flip-flop via the first and second storage nodes, the discharge transistor being opened and closed based on the voltage of any one of the storage nodes Has,
A capacitance discharging circuit for discharging a parasitic capacitance at a control terminal of the second-conductivity-type transistor in the output stage; and a charging transistor that is opened / closed based on the logical input or the inverting input to charge the capacitor. Ru formed by adding the road.
Then, the first and second storage nodes are connected to the high-voltage power supply.
Diode clampers are connected between the
It is characterized by that.

[0031]

In order to solve the second problem, a sudden increase current is applied to the first and second first conductivity type transistors and the charging transistor during the transition of the level of the logic input to a low current. Each of them has a current variable circuit for reducing the current.

Such a current variable circuit may be a time-switchable current variable circuit that switches the sudden increase current to a low current after a predetermined period from the time when the level of the logic input changes.

In order to solve the third problem, the current variable circuit detects the end of the level change of the output voltage appearing at the control terminal of the output-stage second-conductivity-type transistor, and reduces the sudden increase current to a low current. A level detection switching type current variable circuit to be switched.

In a level shift circuit having a level detection switching type current variable circuit, an output stage first conductivity type transistor constituting a complementary drive system of an output terminal together with the output stage second conductivity type transistor, A closing timing circuit for inhibiting simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor using an output level detection signal of the switching type current variable circuit may be provided.

[Operation] In addition to the first and second second conductivity type transistors constituting the flip-flop, a discharge transistor which is opened and closed based on the voltage of one of the storage nodes is provided. Is also not connected to the control terminal of the output-stage second-conductivity-type transistor, so that the discharge transistor opens quickly without being affected by the parasitic capacitance of the control terminal. For this reason, the current from the charging transistor does not easily flow as a through current, and the parasitic capacitance of the control terminal can be rapidly charged. Therefore, the switching speed of the output stage second conductivity type transistor can be increased. Also, since the through current is reduced,
Power consumption can be reduced.

In a configuration in which a diode clamper is connected between each of the first and second storage nodes and the high-voltage power supply, the withstand voltage of an element such as a transistor constituting a flip-flop is reduced. be able to.

Further, in the configuration provided with the current variable circuit, the state transition of the flip-flop is accelerated by the sudden increase current, which contributes to the improvement of the switching speed. At the same time, the opening operation of the discharging transistor is accelerated,
The period of the through current through this is shortened, and the power consumption is further reduced.

In particular, according to the configuration using the level detection switching type current variable circuit as the current variable circuit, the rapid increase current period can be always supplied for the optimum time without making the sudden increase current period too long or too short. Therefore, high-speed state transition operation and low power consumption can be achieved at the same time.

In a semiconductor integrated circuit having an output-stage first-conductivity-type transistor that constitutes a complementary drive system for an output terminal together with an output-stage second-conductivity-type transistor, the output-level detection signal of the level-detection-switching-type current variable circuit is used. When a configuration is provided in which a closing timing circuit that inhibits simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor is provided, before the output stage second conductivity type transistor is opened, Even when a control signal for closing the output stage first conductivity type transistor is generated, the output stage first conductivity type transistor is not closed until the output stage second conductivity type transistor is actually opened by the closing timing circuit. As a result, it is possible to eliminate a through current in the output stage and to achieve a significant reduction in power consumption.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

[0042]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

[Embodiment 1] FIG. 1 is a circuit diagram showing an output stage transistor together with a level shift circuit according to Embodiment 1 of the present invention.

The level shift circuit 40 of the present embodiment is a signal voltage level converter in which the drain node N ₂ of the level shift circuit 30 shown in FIG. 9 is not connected to the gate G of the power P-channel MOSFET 5 in the output stage. Circuit 30 '
When the output buffer to rapidly charge and discharge the gate capacitance C ₅ of the power P channel type MOSFET5 the output stage based on the node voltage V _g of the flip-flop FF inverted input signal V _IN ^* of the signal voltage level conversion circuit 30 ' And a circuit 50.

The signal voltage level conversion circuit 30 'generates an inverted 3V-system inverted signal V _IN ^* from a logic input signal V _{IN having} a narrow logic amplitude (3V = Vdd-Vss) by a 3V power supply.
MOS inverter INV1 and first high-breakdown-voltage N-channel MOSFET controlled to open / close by a logical input signal V _IN
1 and an inverted signal V _IN ^* to generate a first N-channel MOS
The first high-voltage N-channel MOSFET 2 that is exclusively controlled to open and close with the FET 1 is connected to a 30 V (Vcc) power supply by a first power supply.
A first P-channel MOSFET 3 which forms a two-stage series circuit together with the N-channel MOSFET 1 and is controlled to be closed by closing the second N-channel MOSFET 2;
Second N-channel MOSFET between 30V (Vcc) power supply
2 together with the first N-channel type M
A second P-channel MOSFET 5 controlled to be closed by closing the OSFET 1, and a first P-channel MOSFET 3 and a second P-channel MOSFET
5 is a flip-flop FF by a feedback loop via drain nodes (storage nodes) N ₁ and N ₂
Is composed.

Then, the first P-channel type MOSFET
The gates (drain nodes N ₁ , N ₂ ) of the third and second P-channel MOSFETs 4 are connected to a Vcc power supply via constant voltage diodes D ₁ , D ₂ for diode clampers.

The signal voltage level conversion circuit 3 of this embodiment
0 'also has drain current variable circuits 32 and 34.
The first drain current variable circuit 32 includes series source resistances R ₁₁ and R ₁₂ constituting a source follower circuit (constant current circuit) together with the first N-channel MOSFET 1 operating in the unsaturated region, and one of the sources. source resistance value switching N-channel type to short-circuit the resistor R ₁₂ MOSFET 6
When, the switching timed pulse P1 having a predetermined pulse width [Delta] T ₁ at time t ₁ the logic input signal V _IN rises MOSFET6
And a one-shot circuit (monostable multivibrator) 7 for applying a voltage to the gates. Further, the second drain current variable circuit 34 also includes a series source resistance R ₂₁ and R ₂₂ constituting a source follower circuit (constant current circuit) together with the second N-channel MOSFET 2 operating in the unsaturated region, and one of the two. source resistance switching N-channel type MOSFET8 to short the source resistor R _22, logic input signal V _IN
At a time point t ₂ at which the pulse width falls, a predetermined pulse width ΔT ₂ (= Δ
And a one-shot circuit 9 for applying the switching timed pulse P2 of T ₁ ) to the gate of the MOSFET 8.

The output buffer circuit 50 includes a gate capacitance charging circuit 52 for rapidly charging the gate capacitance C ₅ of the power P-channel type MOSFET 5 at the output stage during one state transition of the flip-flop FF, and a gate capacitance charging circuit 52 for the flip-flop FF. At the time of the other state transition, the power P-channel type MO of the output stage
And a gate capacitance discharging circuit 54 for rapidly discharging the gate capacitance C5 of the SFET ₅ .

The gate capacitance charging circuit 52 has a gate capacitance C ₅
Of a charge pump to lower the voltage of the gate G from the V _cc voltage (source voltage) by pulling out the electric charge from the gate G is supplied to the ground (Vss), a second high-voltage N-channel by inverting the input signal V _IN ^* -Voltage N-channel MOSFET for charging and opening controlled in synchronization with the MOSFET 2
52a and a series source resistance R ₃₁ and R forming a source follower circuit (constant current circuit) together with a charging high breakdown voltage N-channel MOSFET 52a operating in an unsaturated region.
_32, has a source resistance for switching N-channel type MOSFET52b shorting one of the source resistor R ₃₂ thereof, the MOSFET52b is opened and closed controlled by receiving timed pulses P2 from the one-shot circuit 9 to the gate.

The gate capacitance discharging circuit 54 has a gate capacitance C
Connect to both ends (between source and drain) of ₅
Discharging P-channel type MOSFET54a relatively large elements to be opened and closed controlled by the node N ₁ of the node voltage V _g
If, and a constant voltage diode D ₃ of connected diodes for clamper between the gate and the Vcc power supply for this MOSFET54a.

First, as shown in FIG. 2, at time t ₁ , a logic input signal V _IN having a narrow logic amplitude (0 to 3 V) rises,
When the first N-channel MOSFET 1 is closed and the second N-channel MOSFET 2 is opened, the current I suddenly increases due to the timed pulse P1 of the drain current variable circuit 32.
_{Since MAX} flows through the first N-channel MOSFET 1, the node voltage V _g is because the sudden drop by the Zener voltage V _Z of the Zener diode D ₂ than Vcc, the second P-channel type MOSFET4 and discharging MOSFET54a is closed .

Incidentally, in this example, the second P-channel type M
OSFET4 is a power P-channel type MOSFE at the output stage
It is not necessary to rapidly discharge the gate capacitance C ₅ of T5,
It is formed as a small-scale element. On the other hand, P-channel type MOSFET54a discharge is formed as a large-scale device for rapidly discharging the gate capacitance C _5, but not negligible gate capacitance C ₆ parasitic thereto, the pulse current value of surge current I _MAX here By increasing the width, the node voltage _Vg can be rapidly reduced. Then, the node N is closed by closing the second P-channel MOSFET 4 and the discharging P-channel MOSFET 54a.
_{The second} voltage becomes the high level Vcc, whereby the first P-channel MOSFET 3 is opened. Opening time of this first P-channel type MOSFET3 is equivalent approximately to a time point t ₁₁ where the drain current of the first N-channel type MOSFET1 returns to save current I _MIN by the drain current variable circuit 32. Thereafter, most of the saving current I _MIN is used to maintain the zener voltage V _Z of the constant voltage diode D ₂ .

When the node voltage _Vg is more than the Zener voltage Vcc
At the time when the voltage drops by _Z , the discharging P-channel type MOSF
Since the ET 54a is also closed, the gate capacitance C5 of the output power P-channel MOSFET ₅ is instantaneously discharged. As a result, the power P-channel MOSFET 5 in the output stage turns off sharply.

Next, the second N-channel type MOSFET2 at time t ₂ which falls logic input signal V _IN is closed, the first N-channel MOSFET1 is opened, at the same time, closing the charging MOSFET52a I do. Therefore, on the one hand, the second N-channel type MOSFE
Rapidly increasing drain current I _MAX flows, but by the closing of T2,
Since the gate G of the power MOSFET 5 in the output stage is not connected to the node N ₂ and the gate capacitance C ₅ does not need to be charged, the voltage of the node N ₂ drops rapidly, and the first P-channel MOSFET 3 is immediately turned off. And the gate capacitance C
₆ discharges, and the discharge MOSFET 54a opens promptly. On the other hand, when the charging MOSFET 52a is closed, the power P-channel MOSFET 5 in the output stage is closed.
Since the flows as the gate capacitance C ₅ drain withdrawn charges from the current I _D3, the gate capacitance C ₅ is charged promptly. As a result, the output voltage V _OUT decreases, so that the power P-channel MOSFET 5 in the output stage turns on sharply.

By the way, the energization time [Delta] T ₂ flowing a surge drain current I _MAX to the N-channel type MOSFET2 is substantially possible in a short time as compared with the energizing time [Delta] T ₁ to flow a surge drain current I _MAX to the N-channel type MOSFET 1. The second P-channel type MOSF small element in the node N ₁
And ET4 to discharge MOSFET54a large elements are connected merely by a first P-channel type MOSFET3 small element is connected to the node N _2, the first P-channel type MOSFET3 Is negligible. Therefore, the charge amount q2 in FIG.
Is a very small amount. When a further increased drain current I _MAX ′ flows through the N-channel MOSFET 2, the charging time can be further reduced, and the closing time t _{21 of} the first P-channel MOSFET 3, and hence the discharging MO
The opening time of the SFET 54a can be advanced. On the other hand, the drain current I _D3 flowing through the charging MOSFET52a was closed at time t _21, although flows slightly its initial as through current, as described above, immediately discharge MOS
Since the FET 54a is opened, the conduction time of the through current is t
Is about a period of ₂ ~t _21, because this is may be a very short time, it is possible to suppress as electric power consumption of q3. The ability to shorten the conduction period of the through current can be _achieved by increasing the drain current I _D3 and increasing the drain current I _D3.
Although the power consumption even if _MAX does not change much, the effect is to shorten the charging time of the gate capacitance C _5. As a result, the second N-channel type MOSFET 2 and the charging MOSFET
While reducing power consumption by reducing the reactive current in T52a, the output stage power P-channel MOSFET
The turn-on time T _{ON of} T5 can be reduced, and can be balanced with the turn-off time T _OFF . This leads to an improvement in switching speed.

The drain current variable circuit 34 allows the drain current I _D3 to rapidly decrease after the time ΔT ₂ of the rapid increase of the drain current I _MAX has passed, but the gate G has a constant voltage diode for a voltage clamper. Since they are not connected, the value of the drain current _ID3 is desirably as small as possible, and the source resistance _{R32 is set} to a high resistance. FIG.
In the circuit arrangement of, but when the start to flow surge drain current I _MAX of the charging MOSFET52a has become rapidly drain current I time t ₁ to start the flow of _MAX the MOSFET 2, a dedicated one-shot circuit and a delay element or the like The time point t ₁ may be slightly delayed. MOSFET for charging 5
2a can be further suppressed, and the power consumption indicated by q3 in FIG. 2 can be substantially eliminated.

[Embodiment 2] FIG. 3 is a circuit diagram showing an output stage transistor in addition to a level shift circuit according to Embodiment 2 of the present invention.

The level shift circuit 40 'of this embodiment comprises a signal voltage level conversion circuit 30' and a simplified output buffer circuit 50 '. The gate capacitance charging circuit 52 'of the output buffer circuit 50' has a charging high-breakdown-voltage N-channel MOSFET 52 whose opening and closing are controlled in synchronization with the second high-breakdown-voltage N-channel MOSFET 2 by the inverted input signal V _IN ^* .
a, series source resistances R ₂₁ ′ and R ₂₂ ′ of a signal voltage level conversion circuit 30 ′ forming a source follower circuit (constant current circuit) together with a charging high-breakdown-voltage N-channel MOSFET 52 a operating in an unsaturated region; It has an N-channel MOSFET 8 for switching the source resistance value for short-circuiting one of the source resistances R ₂₂ ′, and a one-shot circuit 9. The source resistances R ₂₁ ′ and R ₂₂ ′, the source resistance switching N-channel MOSFET 8 and the one-shot circuit 9 are all connected to the second N-type of the signal voltage level conversion circuit 30 ′.
The channel type MOSFET 2 is also used. The gate capacitance discharge circuit 54 ', both ends of the gate capacitance C ₅ - connected to (source-drain), drain node N ₁ of the node voltage V _g by opening and closing controlled by relatively discharging P-channel of larger elements type MOSFET54a consist only, not provided with a constant voltage diode D ₃ for diode clamper shown in Figure 1. Source resistances R ₂₁ ′ and R
By optimizing the value of ₂₂ ', the rapidly increasing drain current I _MAX and power saving current I _MIN to be passed through the second N-channel MOSFET 2, and the high withstand voltage N-channel MM for charging
The respective values of the rapidly increasing drain current and the minimum current to be passed through the OSFET 52a can be set.

Incidentally, even if the constant voltage diode D ₃ is not provided,
Since a constant voltage diode D ₂ parallel thereto there are enabled to clamp the gate voltage of the discharge P-channel type MOSFET54a.

[Embodiment 3] FIG. 4 is a circuit diagram showing an output stage transistor in addition to a level shift circuit according to Embodiment 3 of the present invention.

The level shift circuit 60 of this embodiment is different from the level shift circuit 40 'shown in FIG. 3 in that output voltage level change detection circuits 62 and 64 are provided instead of the one-shot circuits 7 and 9 of the drain current variable circuits 32 and 34. And a two-constant current source type current mirror circuit 66 of a constant current circuit through which constant currents I ₁ and I ₂ flow. The second constant current source-type current mirror circuit 66, the gate flow drain current by the current source 66a from the Vcc power supply - and P-channel type MOSFET66b the drain connection, a constant current I ₁ from the Vcc power source gate connected to the gate a first mirror P-channel type MOSFET66c flow, and a second mirror P-channel type MOSFET66d flowing a constant current I ₂ from the Vcc power source gate connected to the gate of MOSFET66b.

The first output signal level change detection circuit 62 is closed by the falling change of the voltage of the first node N ₁ and outputs a high voltage for detecting the rising of the output voltage which flows the constant current I ₁ as the drain current. Withstand voltage P-channel MOSFET
62a and the current-voltage conversion resistor r passing the constant current I ₁
Has _1, the CMOS inverter INV2 for generating a gate signal S1 as an input the voltage drop across the resistor r _1. Further, the second output signal level change detection circuit 64
Is closed by the falling change of the gate voltage (output voltage V _OUT ) of the power MOSFET 5 in the output stage and the constant current I
₂ and the high voltage P-channel type MOSFET64a for detecting falling output voltage falling flow as the drain current, a current-voltage conversion resistor r ₂ to flow the constant current I _2, the resistance r ₂
That generates a gate signal S2 using the voltage drop of
OS inverter INV3.

First, as shown in FIG. 5, immediately before the time t ₁ at which the logic input signal V _IN having a narrow logic amplitude rises, the voltage V _g of the node N ₁ is the high voltage Vcc (30 V) and the output voltage is high. The voltage V _OUT is Vss (0 V), while one P-channel MOSFET 62a is open and the other P-channel MOSFET 64a
Is in a closed state. Therefore, no voltage drop occurs in one of the voltage conversion resistors r ₁ , so that the CMOS inverter IN
The output S1 of the V2 has become a high level of 3V, but the N-channel type MOSFET6 is in the closed state, since the other voltage conversion resistor r ₂ voltage drop is generated by the constant current I _2, CMOS The output S2 of the inverter INV3 is 0
Low level of V, N-channel MOSFET
8, 52b is in an open state.

At time t ₁ , the logic input signal V _IN having a narrow logic amplitude rises, and the first N-channel MOSFE
T1 closes and a second N-channel MOSFET
When 2 is opened, since the N-channel type MOSFET6 the drain current variable circuit 32 'is already in the closed state, the surge current I _MAX flows as the drain current I _D1, thereby the voltage V _g at the node N ₁ is lowered At the same time, the output voltage V _OUT starts to rise. During the rising transition of the output voltage V _OUT , the voltage V _{g of the} inverted node N ₁ is output.
Is monitored, and the voltage _Vg becomes (Vcc
−V _Z ), a P-channel MO
Closed at t ₁₂ SFET62a detects this, the gate voltage S1 is a low level (0V) and a voltage drop occurs in the current-voltage conversion resistor r _1, N-channel type MO
The SFET 6 opens, whereby the drain current I _D1 switches to the power saving drain current I _MIN . Therefore, the voltage V
_g is Tachiagariru output voltage V _OUT contrary to the falls, or because this rising of the output voltage V _OUT ceases the supply of surge current I _MAX at t _12, which was completed in reality, the supply time is too short, Since the length is optimized without being too long, both the reduction of the turn-off time T _{OFF and} the reduction of power consumption can be achieved.

[0065] When the output voltage V _OUT at t ₁₂ rises, since the P-channel type MOSFET64a is opened, the constant current I ₂ stops flowing, the current-voltage conversion resistor r ₂
, And the gate signal S2 rises. Thereby, the N-channel type M of the drain current variable circuit 34 '
The OSFET 8 and the N-channel MOSFET 52b of the gate capacitance charging circuit 52 are closed.

Next, the second N-channel type MOSFET2 at time t ₂ which falls logic input signal V _IN is closed, the first N-channel MOSFET1 is opened, at the same time, closing the charging MOSFET52a I do. Here, the N-channel type MO of the drain current variable circuit 34 '
Since the SFET 8 and the N-channel MOSFET 52b of the gate capacitance charging circuit 52 are already closed, the second N-channel MOSFET 2 has a rapidly increasing drain current I>
_MAX flows, the voltage V ₂ at the node N ₂ is rapidly lowered, first
The gate capacitance C ₆ is discharged P-channel type MOSFET3 is closed immediately, and the discharge MOSFET54a is opened quickly. On the other hand, the charging MOSFET 52a
Surge drain current I _MAX flows in, rapidly charges the gate capacitance C ₅ of the power P-channel MOSFET 5, the output voltage V _OUT falls. During the falling transition period of the output voltage V _OUT, the change in the falling is monitored by the P-channel MOSFET 64a, and the output voltage V _OUT
When the voltage falls to a value close to the voltage Vss, the P-channel type MO
Closed at t ₂₄ SFET64a detects this, the gate voltage S2 is falls to a low level (0V) and a voltage drop occurs in the current-voltage conversion resistor r _2, the N-channel type MOSFET8,52b The drain currents I _D2 and I _D3 are switched to the power saving drain current I _MIN . For this reason, the supply of the rapidly increasing drain current I _MAX is stopped at the time point t ₂₄ when the fall of the output voltage V _OUT is actually completed, so that the supply time is optimized without being too short or too long. As described above, in this example, the level detection switching type current variable circuit is used, so that the turn-on time T _ON
And power consumption can be both reduced.

In the transition period when the output voltage V _OUT falls at time t ₂₄ , V _g has already risen, so that the P-channel MOSFET 62 a is opened and the constant current I ₁ does not flow. voltage drop across the resistor r ₁ disappears, the gate signal S1 rises. Thereby, the N-channel MOSFET 6 of the drain current variable circuit 32 '
N-channel MOSFET 6 is closed.

In this example, the MOSFETs 8 and 52b are opened in synchronization with the fall of the gate signal S2, and the drain currents I _D2 and I _D3 are simultaneously switched from the rapidly increasing drain current I _MAX to the power saving drain current I _MIN . However, if the switching point of the drain current I _D2 is advanced to the rising point of the gate voltage, the power consumption can be reduced.

[Embodiment 4] FIG. 6 is a circuit diagram showing an output stage transistor together with a level shift circuit according to Embodiment 3 of the present invention.

In this embodiment, the output stage of the level shift circuit 60 is a power high withstand voltage N-channel type MO of the output stage constituting a two-stage series circuit with the power P-channel type MOSFET 5.
An SFET 15 having a high withstand voltage P-channel type driving
The gate G of the SFET 25 is connected. The gate withstand voltage of the driving high-breakdown-voltage P-channel MOSFET 25 is 30 V or more, and drives an inductance load L of an inverter circuit, for example. The gate of the N-channel MOSFET 15 as a complementary transistor of the P-channel MOSFET 5 is driven by the output signal CT of the closing timing circuit 70.
The closing timing circuit 70 includes a NAND gate 70a having two inputs, a logic input signal V _IN having a narrow logic amplitude and the output S2 of the CMOS inverter INV3, and a NAND gate 70a.
and an inverter 70b for inverting the output of a and amplifying the power.

In this embodiment, the driving MOSFET 25 having a high withstand voltage and large current capacity is switched by a complementary (complementary) gate driving method of the P-channel MOSFET 5 and the N-channel MOSFET 15. When a logic input signal V _IN is applied via a buffer circuit to drive the gate of the N-channel MOSFET 15, the switching control of the N-channel MOSFET 15 is possible.
Since the output voltage V _OUT for driving the gate of No. 5 is formed via the level shift circuit 60, a phase delay is inevitably generated with respect to the logic input signal V _IN . If the phase delay is large, the complementary P-channel type M that should be opened and closed exclusively
Since the simultaneous closing period is mixed in the OSFET 5 and the N-channel type MOSFET 15, a through current having a high current value is generated, and a large power consumption is caused. To mitigate this, N
It is possible to take measures to provide a delay circuit in the transmission system of the logic input signal V _IN on the channel type MOSFET 15 side. However, since the delay amount of the delay circuit is determined only by the expected amount, the simultaneous closing period is actually mixed in due to manufacturing variations of semiconductor elements, and a through current that cannot be ignored is generated.

However, in this example, as shown in FIG. 6, when the logic input signal V _IN is at a low level, the rapid increase of the drain current I
Due to _MIN , the output voltage V _OUT immediately drops, and the P-channel MOSFET 5 is turned on. Since the output voltage V _OUT is at a low level when the P-channel MOSFET 5 is closed, the output S2 of the CMOS inverter INV3 of the output voltage level change detection circuit 64 is also at a low level. As long as the output S2 is at a low level, even if the logic input signal V _IN quickly goes to a high level, the NAND gate 70
The output of a remains at a high level and an N-channel MOS
FET 15 is not closed. The output S2 becomes high level,
When the P-channel MOSFET 5 is turned off, the N-channel MOSFET 15 is closed for the first time. Therefore,
When the P-channel MOSFET 5 is turned off, N
The simultaneous closing time when the channel type MOSFET 15 is turned on does not occur, and the through current can be eliminated.
When the N-channel MOSFET 15 turns off and the P-channel MOSFET 5 turns on, the N-channel MOSFET 15 receives the input signal V _IN.
, The opening is controlled directly, and the opening is performed earlier, so that no through current is generated.

In the above embodiments, the P-channel type M
A flip-flop FF is composed of OSFETs 3 and 4,
The pull-down MOSFETs 3 and 4 for writing potentials to the recording nodes N _{1 and} N ₂ are of the N-channel type. However, the conductivity type is reversed, and a flip-flop FF is formed by N-channel MOSFETs. N1 _,
The pull-up MOSFET for writing the potential to N ₂ may be of a P-channel type.

In the above embodiment, the logic input V having the narrow logic amplitude
The low level voltage V _ss of _IN is 0 V, the high level voltage V _dd is 3 V, the low level voltage V _ss of the logic output V _{OUT having} a wide logic amplitude is 0 V, and the high level voltage V _cc is 30 V. In the present invention, _{assuming that} the low-level voltage V _ee of the logic output V _OUT has a wide logic amplitude, it suffices to satisfy the relationship of low voltage source (V _dd −V _ss ) <high voltage source (V _cc −V _ee ). in the above embodiment only in the case of _{V ss = V ee <V dd} <V cc. _{V ee <V cc ≦ V ss} <V dd, V ee <V ss <V cc ≦
V _dd , V _ss ≦ V _ee <V _dd ≦ V _cc , V _ss <V _dd ≦ V _ee <V
_It goes without saying that the case of _cc is also included.

[0075] Further, if set to be equal to the resistors R _11, the value of R _21, R ₃₁ the on-resistance of MOSFET6,8,52b, it is possible to omit the resistors R _11, R _21, R ₃₁ .

Further, the level shift circuit may be formed using not only a monopolar transistor such as a MOSFET (insulated gate type field effect transistor) but also a bipolar transistor.

[0077]

As described above, in the level shift circuit according to the present invention, the control terminal of the output stage transistor is parasitic, apart from the first and second conductivity type transistors forming the flip-flop. In order to charge and discharge the capacitance, the first transistor includes a discharging transistor that is opened and closed based on the voltage of one of the storage nodes, and a charging transistor that is opened and closed by a logical input or an inverted input thereof .
Between the second storage node and the high-voltage power supply.
It is characterized in that an ion clamper is connected . Therefore, the following effects are obtained.

Since none of the storage nodes is connected to the control terminal of the output-stage second-conductivity-type transistor, the discharge transistor is opened quickly without being affected by the parasitic capacitance of the control terminal. Is difficult to flow as a through current, and the parasitic capacitance of the control terminal can be rapidly charged. Therefore, the switching speed of the output stage second conductivity type transistor can be increased. Further, since the through current decreases, power consumption can be reduced. In addition, the first and second storage nodes are
Diode clampers are connected between the power supply and
Of the flip-flop
The withstand voltage of an element such as a resistor can be reduced.

In a configuration having a current variable circuit,
Indicates that the state transition of the flip-flop is
It contributes to the improvement of the switching speed because it is faster. Also
At the same time, the opening operation of the discharging transistor is accelerated,
The duration of the through current through this is shortened, and the power consumption is further improved.
To be reduced.

In particular, as a current variable circuit, a level detection
According to the configuration using the output switching type current variable circuit,
Current time is not too long or too short, always optimal time
Only a sudden increase in current can flow.
High speed and low power consumption can be achieved at the same time.

Output Stage Together with Second Conduction Type Transistor
Output that constitutes a complementary drive system for output terminals
Semiconductor integrated circuit having a first-conductivity-type transistor
And the output level of the above level detection switching type current variable circuit.
Using the bell detection signal, the output stage first conductivity type transistor
And the output stage second conductivity type transistor are closed at the same time.
If a configuration with a closing timing circuit to stop is adopted,
Until the output stage second conductivity type transistor is actually opened,
The output stage first conductivity type transistor is not closed.
Output current can be eliminated,
Wide reduction in power consumption can be achieved.

[0082]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output stage transistor together with a level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms of respective units in the first embodiment.

FIG. 3 is a circuit diagram showing an output stage transistor together with a level shift circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an output stage transistor in addition to a level shift circuit according to a third embodiment of the present invention.

FIG. 5 is a timing chart showing waveforms of respective units in a third embodiment.

FIG. 6 is a circuit diagram illustrating an output stage transistor in addition to a level shift circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing an output stage transistor in addition to a conventional basic level shift circuit.

FIG. 8 is a circuit diagram showing an output stage transistor in addition to a conventional level shift circuit having a diode clamper.

9 is a circuit diagram showing an output-stage transistor in addition to a level shift circuit obtained by improving the level shift circuit shown in FIG. 8;

FIG. 10 is a timing chart showing waveforms at various parts of the circuit shown in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st high voltage N-channel MOSFET 2 ... 2nd high voltage N channel MOSFET 3 ... 1st high voltage P channel MOSFET 4 ... 2nd high voltage P channel MOSFET 5 ... Power of output stage P-channel MOSFETs 5a, 5b output terminals 6, 8, 52b N-channel MOSFETs for source resistance switching 15 power N-channel MOSFETs in output stage 25 high-voltage P-channel MOSFETs for driving 30 ', 30 " ... Signal voltage level conversion circuit 32 ... First drain current variable circuit 34 ... Second drain current variable circuit 40,40 ', 60 ... Level shift circuit 50,50' ... Output buffer circuit 52,52 '... Gate capacitance charging Circuit 52a: High voltage N-channel MOSFET for charging 54, 54 '... Gate capacitance discharge circuit 54a ... High withstand voltage P-channel MOSFETs 62, 64 ... Output voltage level change detection circuit 62a: High-breakdown-voltage P-channel MOSFET 64a for detecting rising output voltage 64a: High-breakdown P-channel MOSFET 66: 2 for detecting falling output voltage Constant current source type current mirror circuit 66a current source 66b P-channel MOSFET 66c first mirror P-channel MOSFET 66d second mirror P-channel MOSFET 70 closing timing circuit 70a NAND gate 70b inverter P1 , P2 ... switching timed pulses r _1, r ₂ ... current-voltage conversion resistor S1, S2 ... Zener diode FF ... flip-flop of a gate signal INV1 to INV3 ... CMOS inverter _{D 1, D 2, D 3} ... diode clamper V _g ... node voltage V _IN ... narrow Sense the amplitude of the logic input signal V _IN ^* ... inverted input signal V _OUT ... wide logic logic output signal N 1 of the _amplitude, N ₂ ... flip-flop drain node (storage node) C _5, C ₆ ... gate capacitance CT ... Output signal.

Claims (5)

(57) [Claims] 1. A first transistor of a first conductivity type, which is opened and closed by a logic input having a narrow logic amplitude by a low-voltage power supply, and a first first transistor having an inverted input having a phase opposite to that of the logic input.
A second first conductivity type transistor that is exclusively opened and closed with the conductivity type transistor;
A first second conductivity type transistor connected in series to the conductivity type transistor and controlled to be closed by closing a second first conductivity type transistor; and a second first conductivity type transistor between the high voltage power supply. A first first transistor connected in series with the transistor;
And a second second conductivity type transistor that is controlled to be closed by closing the conductivity type transistor.
Wherein the second conductivity type transistor forms a flip-flop via first and second storage nodes, wherein the discharge transistor is opened / closed based on the voltage of any one of the storage nodes And a charge discharging circuit that discharges a parasitic capacitance at a control terminal of the second-conductivity-type transistor at the output stage; and a charging transistor that is opened and closed based on the logical input or the inverted input to charge the capacitance. capacitive discharge circuits SQLDESC_BASE_TABLE_NAME This adds formed, said first and second memory that
A diode clamp between the node and the high-voltage power supply.
A level shift circuit comprising a lamper connected . 2. The level shift circuit according to claim 1 , wherein a sudden increase current flows through the first and second first conductivity type transistors and the charging transistor during a level change transition of the logic input. A level shift circuit comprising a current variable circuit for lowering the current to a low current. 3. The level shift circuit according to claim 2 , wherein the current variable circuit switches the sudden increase current to a low current after a predetermined period from the level change of the logic input. A level shift circuit characterized by the following. 4. The level shift circuit according to claim 2 , wherein the current variable circuit detects the end of the level change of the output voltage appearing at the control terminal of the output stage second conductivity type transistor, and reduces the sudden increase current. A level shift circuit characterized by being a level detection switching type current variable circuit for switching to current. 5. The level shift circuit according to claim 4 , wherein said output stage first conductive type transistor and said output stage first stage compose a complementary drive system of an output terminal.
A closing timing circuit for inhibiting simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor using a conductivity type transistor and an output level detection signal of the level detection switching type current value variable circuit; A level shift circuit comprising: