JP3309498B2 - Digital clock recovery device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital clock reproducing apparatus, and more particularly, to a digital clock reproducing apparatus which outputs data for each reproduction clock timing with respect to input data sampled by a predetermined sampling clock.

[0002]

2. Description of the Related Art Generally, a PLL (Phase Lock Loop) circuit for reproducing a clock of an input signal is a phase locked loop circuit that follows the phase of the input signal. And so on.

However, such analog PLLs
Circuits generally require time and labor for adjustment and the like, which causes an increase in cost. When a digital circuit is used in a device to which a PLL circuit is applied, for example, when a digital equalizer is used to have an automatic equalization function, a signal once digitized is converted into an analog signal. Analog P
An operation for supplying the signal to the LL circuit is required, and when a digital circuit is used on the subsequent stage, it is necessary to convert the digital signal again into a digital signal. Further, when the PLL is configured by an analog circuit, for example, depending on the operation status such as a track jump in a disk reproducing device,
It is difficult to change the operation environment, and the circuit configuration becomes complicated.

[0004] In view of the above, a digital PLL circuit has recently been proposed in which the operation inside the PLL circuit is performed digitally.

In this digital PLL circuit, for example, a configuration in which the phase difference between a PLL output signal and an input signal is measured using a high-speed (high-rate) master clock is often adopted. That is, the time difference between the edge (transient) of the input signal and the output clock generated inside the PLL circuit, that is, the phase difference, is detected and counted with the accuracy of the high-speed master clock, and the phase of the output clock from inside the circuit is detected. It is controlled to synchronize with the clock of the input signal. In this case, the master clock is required to have an accuracy higher by one digit or more than the bit clock of the input signal.

However, as the clock frequency of the input signal increases, it becomes difficult to increase the frequency of the master clock by one digit or more. This is because the operating clock frequency cannot be extremely increased due to limitations due to the physical characteristics of the semiconductor element. Therefore, it is desired to configure a digital PLL device capable of detecting an effective phase difference without extremely increasing the master clock frequency.

[0007]

In a conventional digital PLL device, an input signal is first sampled by a master clock and then extracted as a binary signal using a comparator. It is difficult to perform so-called Viterbi demodulation or the like because an output that is considered cannot be obtained.

That is, in the digital PLL device, since the level of the input signal itself is not used, only the time information is used, and a clock having a very high frequency is required. Therefore, if sampling is performed at a period as small as possible and edge times are not taken in accurately, data errors due to the PLL increase. However, even if the required reproduction clock frequency increases, the master clock frequency remains unchanged in the semiconductor process. There is a problem that can not be raised unnecessarily due to restrictions.

The present invention has been made in view of such circumstances, and a normal PLL operation is performed even when the master clock frequency is low. Further, the ratio of the master clock frequency to the reproduction clock frequency is larger than 1. Digital P that can secure a good error rate
The purpose is to provide an LL device.

[0010]

A digital clock reproducing apparatus according to the present invention obtains an edge position based on input data obtained by sampling an input signal to be clock-reproduced by a predetermined sampling clock, and obtains the edge position. Phase detecting means for outputting phase error information between a position and a reproduced clock; clock generating means for outputting reproduced clock information based on the phase detection error from the phase detecting means and reproduced clock cycle information; Clock cycle generating means for outputting the reproduced clock cycle information in accordance with the phase error information from the detecting means and the reproduced clock information from the clock generating means, wherein the phase detecting means linearly interpolates the input data. The interpolation data obtained by the above is output, and the interpolation at each reproduction clock timing is performed according to the reproduction clock information. By providing the data selection means for selecting and outputting data, to solve the problems described above.

[0011]

Further, the sampling clock frequency is set lower than the reproduction clock frequency, and the clock generation means is configured to output the reproduction clock information including two or more reproduction clock positions within one sampling period. Is preferred. The clock cycle generation means may adjust the reproduction clock cycle according to the result of adding the phase error information from the phase detection means over a predetermined period, and output the reproduction clock cycle information. Further, as the clock cycle generating means, it is checked whether or not the reproduction frequency is within a lock range, whether or not the fluctuation of the reproduction frequency is small,
It is desirable to select and output a reproduction clock cycle as appropriate according to an operation situation such as a track jump.

[0013]

The clock position is lower than the clock frequency to be reproduced because the edge position is obtained by interpolation or the like based on the input data and the clock reproduction is performed while adjusting the reproduction clock cycle based on the phase error between the edge position and the reproduction clock. An effective PLL operation can be performed even with a sampling clock. Further, since the digital PLL is used, no adjustment is required, and the PLL operating environment can be changed in accordance with an operating condition such as a track jump.

[0014]

FIG. 1 is a block circuit diagram showing a schematic configuration of a digital clock reproducing apparatus as one embodiment of the present invention.

In FIG. 1, data DI of an RF (high frequency) input signal whose clock is to be reproduced is supplied to an input terminal 11 and sent to a phase detection circuit 12. This input data DI is digital data of a sample value sampled by a predetermined master clock.
Clock information CS from the clock generation circuit 13 is supplied to the phase detection circuit 12, and edge error information PEG representing phase error information between the phase position and the edge position of the signal waveform corresponding to the input data DI; And outputs edge existence information EEX indicating whether an edge exists within each sampling interval. The edge error information PEG is sent to the clock generation circuit 13 and the clock cycle generation circuit 14, and the edge existence information EEX is sent to the clock cycle generation circuit 14, respectively. The clock cycle generation circuit 14 generates clock cycle information CP representing the cycle of the reproduced clock, and sends the clock cycle information CP to the clock generation circuit 13.

Further, the digital clock reproducing apparatus shown in FIG. 1 also reproduces data. That is, interpolation data CDD obtained by interpolating data between samplings is output from the phase detection circuit 12 and sent to the data selector 15. The data selector 15 includes the clock information C from the clock generation circuit 13.
S is also supplied, and the data of the reproduction clock timing (that is, data resampled by the reproduction clock) is selected from the interpolation data CDD based on the clock information CS, and the reproduction data DO is output.

Such a digital clock recovery device or digital PLL is used as a partial circuit of a device as shown in FIG. 2, for example. Input terminal 2 of FIG.
For example, a signal reproduced from a recording medium such as a magnetic tape or an optical disk, or a signal transmitted via a communication medium or the like is supplied to 1. This input signal is sent to an A / D (analog / digital) converter 24 as a so-called RF signal through an amplifier 22 and, if necessary, an analog equalizer (equalizer) 23. The A / D converter 24 samples at a predetermined sampling frequency (master clock frequency) and converts it into a digital signal. Thereafter, digital signal processing is performed.

A digital signal from the A / D converter 24 is converted into a digital equalizer (equalizer) 25 as necessary.
Then, after passing through a digital automatic asymmetry correction circuit 26, it is input to a digital PLL (digital clock reproducing device) 10 as shown in FIG. In the digital PLL 10, the data equalized as required and subjected to asymmetry correction or not,
It receives asynchronously, extracts the clock component contained therein, resamples the data in synchronization with the clock, and sends it to the demodulator 27 together with a signal indicating the validity.

Next, the basic operation of the PLL will be described with reference to FIG. RF input to PLL
The edge of the signal is determined by a predetermined level (threshold level). The clock to be reproduced is required to be synchronized with this edge, and the PLL is required to generate a reproduced clock synchronized with this edge. However, in practice, an error is generated between the edge of the RF signal and the clock, and this error must be corrected. For this reason, the difference between the edge of the RF signal and the edge of the reproduced clock is accumulated as an error signal, and synchronization is thereby performed.

[0020] That is, at time t _1, t ₂ of FIG. 3, although the recovered clock edges of edge and B of the RF signal A is consistent, the edge of the RF signal at time t _3, the reproduction clock An edge error PEG is generated between the edge and the edge. By accumulating this edge error PEG,
Synchronization takes place.

Here, the digital PLL of the embodiment of the present invention
In the above, the use of the level information from the A / D converter 24 realizes a higher resolution than the PLL operation using only the time information based on a simple binary sample.

FIG. 4 shows a continuous signal S such as the RF signal.
Is restored at a given point in time from data strings a, b, c,... Obtained by sampling at a predetermined period X. This is because if the band of the continuous signal S is limited by the so-called sampling theorem, the original signal S can be uniquely restored by sampling (sampling) at a frequency equal to or more than half of the upper limit frequency. . Specifically, a so-called convolution operation is performed on the sample values a, b, c,... Around the point to be restored, thereby obtaining a value y at an arbitrary point.

By performing the convolution operation described above, the original signal S can be completely restored. However, in actuality, the number of sample points and the amount of operation required for this operation are enormous, and high-speed clock reproduction is not possible. In consideration of being unsuitable, in this embodiment, linear interpolation is used, which simplifies the calculation. When the low-speed clock is reproduced, the convolution operation may be performed.

FIG. 5 is a diagram for explaining the operation for obtaining the edge of the signal S using the above-described linear interpolation. This figure 5
As is clear from, when linear interpolation is performed, it is not always possible to restore the values at all times,
The error at the so-called zero-cross point (point P in the figure) serving as the edge can be made very small if certain conditions are satisfied.

This condition depends on the minimum repetition period (or twice the minimum inversion interval) of the RF signal S and the sampling interval (sampling period) X. That is, if the sampling interval X is sufficiently smaller than the minimum repetition period, the edge position can be restored with considerable accuracy although there is a shift.

The method of calculating the edge position will be described with reference to FIG. In FIG. 6, the minimum repetition cycle of the signal S is normalized to 1, and a sine wave of cycle 1 is used as the signal S. When each value of the first sampling point x and the second sampling point x ₂ of the sampling interval X (sample value) and y ₁ and y _2, (of the original signal S) original edge should be the position of 0 although, the position of x ₀ occurs is shifted for the linear approximation. This x ₀
Is an edge position error, indicated by _{x 0 = (xy 2 -x 2} y 1) / (y 2 -y 1).

Here, in the case of a sine wave with a period 1, y ₁ = sin (2πx) y ₂ = sin (2πx ₂ ) = sin (2π (x + X)). However, the possible values of x is the -1/2 <x <1/2- X, and x ₀ becomes valid in the range of -X <x <0.

FIG. 7 shows the edge position error x ₀ corresponding to x, where x is plotted on the horizontal axis and x ₀ is plotted on the vertical axis. In FIG. 7, a region Rx where x can take are the -1/2 <x <1/2- X, a region R _x0 which region the zero crossing linear approximation in this region Rx or x _0, is present Is -X <x <0. A region R other than the region R _x0 in the region Rx
In _NZ, it does not occur and the zero-crossing, the x ₀ does not exist.

As for x ₀ , as the sampling interval X increases, the area of x that crosses gradually widens, and the possible value of x ₀ also increases rapidly. X is, 0 <X <may take half, but from the above description, X can exceed 0.45 when edge position error x ₀ becomes very large. Since x ₀ is evaluated as jitter on the time axis when calculating an edge error, the smaller the better, the better. As a result, X should be, for example, 0.45 or less, and practically 0.4 or less. desirable.

In the digital PLL according to the embodiment of the present invention, synchronization is established by using x ₀ obtained by linear approximation or an edge position obtained by convolution as a difference from a clock represented by a number as an error signal. .

Next, referring to FIGS. 1 and 8,
An example of a specific circuit configuration of a digital PLL (digital clock reproducing device) will be described. First, the input data DI input to the input terminal 11 is a digital sample value obtained by being sampled at the predetermined sampling interval X (sampling cycle, ie, master clock cycle T _M ). Phase detecting circuit the input data DI is supplied 12, and requests the edge error information PEG by the aforementioned interpolation (linear approximation) (corresponding to the x _0). Specifically, n (n is an integer of 2 or more) data is obtained between samplings by, for example, linear interpolation, and interpolated data (interpolated data) CDD is generated. Using these n pieces of interpolation data, the presence or absence of an edge (zero cross) during the sampling period is determined, edge existence determination information EEX is output, and the position of the edge is obtained.
The edge position is compared with the clock information CS obtained from the clock generation circuit 13 to generate edge error information PEG.

Here, a specific example of the phase detection circuit 12 shown in FIG. 8 will be described. The digital input data DI of the input terminal 11 is supplied to an interpolation filter (C
F) 31, n linear interpolation data CDD ₀ , CDD ₁ ,..., CDD _n−1 are obtained during one sampling interval (master clock cycle T _M ). These data strings CDD ₀ , CDD ₁ ,..., CDD _n−1 are sent to an edge position detector (EGD) 32 and an edge detector (EEXD) 33. The edge position detection unit (EGD) 32 generates position information (information indicating the number of the n interpolation points) of the interpolation point corresponding to the edge position (the zero cross point) E
G is generated and sent to the phase error calculator (PERG) 34. The edge detection unit (EEXD) 33 generates edge existence determination information EEX indicating whether or not an edge exists between samplings, and sends it to the phase error calculation unit (PERG) 34 and the clock cycle generation circuit 14. Phase error calculator (PERG) 34
Is the edge position information EG and the edge existence determination information EEX
The difference between the edge position and the clock position is extracted as phase error (edge error) information PEG based on the clock information CS and sent to the clock generation circuit 13 and the clock period generation circuit 14. The digital PLL of this example is
By controlling the clock cycle information CP generated by the clock cycle generation circuit 14 using the phase error (edge error) information PEG, synchronization is achieved.

Here, the period of the sampling clock (master clock) is T _M , the frequency is f _M (= 1 / T _M ), the period of the reproduction clock is T _CK , and the frequency is f _CK (= 1 / T _M ).
T _CK ), it is assumed that the digital PLL of the present embodiment satisfies the relationship of 1.0 <T _M / T _CK <2.0 or 1.0 <f _CK / f _M <2.0. I have.

FIG. 9 shows a specific example of the master clock and the reproduced clock satisfying the above relationship. That is,
During one period T _M of the master clock MCLK shown in FIG. 9A, one or two pulses of the reproduction clock CLK (period T _CK ) shown in B exist (exist). In FIG. 9, the sampling timing of the master clock MCLK of A is indicated by t _M1 , t _M2 ,..., And the timing of the pulse of the reproduction clock CLK of B is t ₁ , t ₂ , respectively.
... are indicated.

Next, in the clock generation circuit 13 of FIG.
Clock cycle information CP from clock cycle generation circuit 14
(NCG) 36 and a latch circuit (D-flip-flop) 37 to output the clock information CS. At this time, the cycle is adjusted using the error information PEG. While performing, it outputs the clock information CS. That is, the clock cycle generation circuit 14
Is the basic period information of the reproduction clock period _TCK , and calculates the next reproduction clock position while adjusting the CP with the error information PEG to generate the clock information CS. I do. As described above, the error information PEG always affects the clock information CS.
Will be affected. The clock information CS indicates the position of the reproduced clock CLK with reference to the master clock MCLK, as shown in FIG. 9C.
Number of reproduction clocks that can exist during the sampling period (master clock period) T _M (maximum two in this embodiment)
And clock value (clock position) information parallelized in accordance with, and clock valid information CV indicating whether or not the clock value is valid. In addition, the phase detection circuit 1
In order to easily use the information CS in step 2, information indicating the interval between clocks (clock interval) may be included. The adder (NCG) 36 is used several times during the sampling clock (master clock) (twice in this embodiment).
Is not synchronized with the sampling clock, and is synchronized by the latch circuit (D) 37.

Next, the clock cycle generation circuit 14 is for generating basic cycle information (clock cycle information) CP of the recovered clock, and is effective for the clock information CS from the clock generation circuit 13 and for detecting the phase. Based on the edge error information PEG and the edge presence determination information EEX from the circuit 11, a deviation from the basic period (CP) is accumulated.
In this method, the information PEG and EEX are used as deviations, and the basic period CP is added according to the basic count condition according to the clock valid information CV in the clock information CS, and the deviation from the original is accumulated. By looking at the obtained period information CP, the frequency of the reproduced clock is determined. Further, the clock cycle generation circuit 14 checks whether or not the reproduced clock is within a preset lock range, thereby preventing malfunction or the like, or combining with the phase lock situation to determine the basic cycle. For example, storage can be performed, thereby making it possible to withstand a disturbance such as a loss of an RF signal at the time of a track jump in a disk reproducing apparatus. By providing a stop signal, a lock range control signal, and the like to the clock cycle generation circuit 15, the operating environment of the digital PLL can be changed. The control of the operating environment can also be performed by a multiplier by which the value of the error information PEG is multiplied.

In FIG. 8, the clock cycle generation circuit 14
Base counter (BC) 42 counts up by one for each sampling clock (master clock), but the clock validity information CV supplied via the latch circuit (D-flip-flop) 41 is "1" (valid )), Two reproduction clocks are present within one sampling interval (the master clock period T _M ), and thus two are counted up. This count operation is performed for a sufficient length, and is used as basic information for checking how many times the reproduction clock is within the master clock. An output signal BC from the base counter (BC) 42
C is a signal indicating whether or not the counter 42 has made one turn. The clock cycle generation circuit 14 calculates the next clock cycle CP with the signal BCC as a trigger.

A basic (base) clock period generator (BCP)
G) 46 adds the edge error information PEG obtained from the phase detection circuit 12, and when the output signal BCC from the counter 42 is input, adds the added value to the clock cycle CP, and Output as clock cycle information BCP. As a result, the frequency deviation is accumulated. The basic clock cycle information BCP includes a basic (base) clock cycle register (BCPR) 45, a clock cycle selector (CPS) 48, and a lock range checker (LRCK).
53 and a frequency lock checker (FLCK) 54.

A lock range checker (LRCK) 53 determines whether the value of the basic clock cycle information BCP is within a predetermined lock range, and outputs the result as a lock range check goodness determination signal LRCKOK. . This discrimination signal LRCKOK is set in the basic clock cycle register (BCPR).
45 and a clock cycle selector (CPS) 48. This means that when a signal that cannot be locked is input, the period corresponding to the center frequency (reference period T _rf )
Can be used to perform a control to output as a basic reproduction clock cycle.

The frequency lock checker (FLCK) 54 checks whether the value of the basic clock period information BCP is small during the cycle of the counting of the base counter (BC) 42 several times. , And outputs the result as a determination signal FLCKOK. The determination signal FLCKOK is sent to the basic clock cycle register (BCPR) 45. As a result, it is known whether the frequency of the digital PLL has been sufficiently pulled in, and the locked state can be known.

The phase lock checker (PLCK) 52 uses the edge error information PEG from the phase detection circuit 12 and the edge existence determination information EEX obtained via the latch circuit (D-flip-flop) 51 to determine the phase. It is determined in a certain period whether or not the signal is concentrated near the clock position. If the signal is concentrated, a determination signal PLCKOK is output. This discrimination signal PL
CKOK is also sent to the basic clock cycle register (BCPR) 45. This signal PLCKOK is used together with the frequency lock check discrimination signal FLCKOK to generate a digital PLCKOK signal.
It can be used to determine whether L is locked.

Next, a basic (base) clock cycle register (BCPR) 45 stores the basic clock cycle information BCP. That is, each of the above-described determination signals LRCKOK, FLCKOK,
When all of PLCKOK is OK (OK), the digital P
Since the LL is locked, the basic clock cycle information BCP at that time is stored so that the digital PLL can be used in the event of a sudden phenomenon such as a track jump.
The sudden phenomenon can be ignored by using the stored information without abruptly changing the operation. The output signal BCPRO read from the basic clock cycle register (BCPR) 45 is sent to a clock cycle selector (CPS) 48.

The clock cycle selector (CPS) 48 receives information (reference clock cycle information) RCP from the reference clock cycle generator (RCPG) 47 indicating a reference cycle T _rf corresponding to the operating center frequency (reference frequency) of the PLL. One of the basic clock cycle register output BCPRO and the basic clock cycle information BCP is selected based on the track jump signal TRJ and the lock range check good determination signal LRCKOK. Clock cycle information C
It is output as P. That is, the discrimination signal LRCK
When OK is “0” (defective, NG, out of lock range), the reference clock cycle indicating the reference cycle T _rf from the reference clock cycle generator (RCPG) 47 regardless of the state of the track jump signal TRJ. Information RCP is selected and taken out as clock cycle information CP. When the discrimination signal is "1" (good, OK, within the lock range), the basic clock cycle generator (BCPG) is used when the signal TRJ is "0" (other than track jump) according to the track jump signal TRJ.
The basic clock cycle information BCP from the block 46 is selected and taken out as the clock cycle information CP. When the signal TRJ is “1” (during track jump), the clock cycle information (register) stored in the basic clock cycle register (BCPR) 45 Output signal) BCPRO and select the clock cycle information CP
Take out as. The track jump signal TRJ is
This signal is used when a head of a disk reproducing apparatus or the like is moved by jumping. In general, a signal indicating a situation where the PLL operation is temporarily stopped can be used.

Each of the latch circuits (D-flip-flops) 41 and 43 in the clock cycle generation circuit 14 shown in FIG.
Reference numerals 44 and 51 operate with a master clock and are used for time alignment.

Next, in the data selector 15, the interpolated data sequence CDD ₀ generated by the phase detection circuit 12,
CDD _1, ..., a CDD _n-1, and sends to the selector 39 through the latch circuit (D-flip-flop) 38, generated by the clock generation circuit 13 clock (position) information C
S is sent to the selector 39. The selector 39 selects the data strings CDD ₀ , CDD ₁ ,..., CDD _{n−1 based} on the clock information CS, outputs the data as data outputs DO ₀ , DO ₁ , and outputs data valid information DOV.

Here, D in FIG.
This is for explaining the main operation in L. That is, in FIG. 9D, the original RF signal S
Are sampled at the respective timings t _M1 , t _M2 ,... Of the master clock MCLK, and the digital data of the obtained sample value is used as the input data DI as the phase detection circuit 12.
Is input to The above CDD ₀ , CDD which is n interpolation data by linearly interpolating between the samplings of the input data DI
_1, ..., the required CDD _n-1, these interpolated data CDD _0,
The edge position is obtained from the values of CDD ₁ ,..., CDD _n-1 . In the specific example shown in FIG. 9D, times t ₁ ′, t ₄ ′,
t ₈ ′ and the like are edge positions, and the edge existence determination information EEX between samplings where this edge exists becomes “1” (see E in FIG. 9). The edge at time t ₁ ′ in FIG. 9 coincides with the reproduction clock timing t ₁ , and the phase error PEG
Is 0. An error PEG between the time t ₄ ′ edge and the reproduction clock timing t ₄ is a non-zero value (t ₄ −
t ₄ ′), and this phase error affects the clock cycle information CP after time t ₄ . By accumulating and adding the clock cycle information CP while adjusting the clock cycle information CP in this manner, each timing (t ₁ , t ₂ ,...) Of the reproduced clock CLK is
It is calculated and obtained as information (CS) of the reproduction clock position with respect to the master clock MCLK. The clock position information (CS) is information indicating the number of the reproduction clock position of the n pieces of interpolation data CDD ₀ , CDD ₁ ,..., CDD _n−1. , One sampling period (master clock cycle T
_The clock validity information CV is provided because two reproduced clocks and one reproduced clock are included in _M ), and CV = “1” for two and CV =
It is set to “0” (see C in FIG. 9). The data selector 15 outputs the n pieces of interpolation data CDD ₀ , CDD ₁ ,.
From the CDD _n−1 , data at each reproduction clock position based on the clock information CS is selected, and two data DO ₀ ,
Output as DO _1, but when the reproduction clock to the sampling period (T _M) within from entering only one data DO
_Since only ₀ is valid and the data DO ₁ is invalid, the data valid information DOV is set to “0”. That is, when the data valid information DOV is “1”, the two output data D
O ₀ and DO ₁ are both valid. When DOV is “0”, data DO ₁ is invalid and only data DO ₀ is valid.

As described above, the master clock (frequency f _M ) lower than the clock frequency to be reproduced (f _CK )
, Normal digital PLL operation becomes possible, and the operating frequency of the digital PLL circuit is kept low.
Inexpensive circuits that do not require high-speed elements are sufficient. Also, since the digital PLL is used, no adjustment is required and the operating environment is
Can be changed during L operation. Also, multi-valued level output is possible as reproduction data, and for example, a reproduction output suitable for sending to a Viterbi demodulator or the like can be obtained.

Here, a specific example in which the above embodiment of the present invention is applied to an optical disk reproducing apparatus will be described. As basic parameters at this time, when the channel clock frequency (the reproduced clock frequency f _CK ) is 60 MHz, the optical cutoff frequency of the optical system is 11 to 12 MHz, and the minimum inversion interval T _min of the modulation signal is 5 T _CK , FIG. 10 shows the relationship between the frequencies. As a result, the required bandwidth is
11M~12MHz below and since the shortest and is periodically a frequency corresponding to the T _min is is a 6 MHz,
When linear interpolation is used as described above, FIGS.
In consideration of the evaluation of X described above, when the value is 0.4, the minimum value f _Mmin of the sampling clock is about 30 MHz. Since this is the minimum, it is considered that about 35 MHz is appropriate as the actual sampling clock frequency f _M with some allowance.

As described above, the sampling clock frequency f _M (35 MHz) is changed to the clock frequency f _CK (6
0 MHz), and even in a so-called sub-sampling state, by processing two pieces of clock position information in parallel within one sampling interval as described above,
An effective digital PLL operation can be realized.

[0050] The present invention is not limited to the above embodiments, for example, the sampling frequency of the input data relationship with (the master clock frequency) f _M and the reproduction clock frequency f _CK (ratio) f _M / f _CK May be 以下 or less, or 1 or more. Further, normal convolution interpolation may be used for the interpolation in the phase detection circuit 12. In addition, it goes without saying that various changes can be made without departing from the spirit of the present invention.

[0051]

As is apparent from the above description, according to the digital clock reproducing apparatus of the present invention, an edge position is obtained based on input data given at a predetermined sampling period, and the edge position and the reproduced clock are determined. Since the recovered clock information is obtained based on the phase error information and the reproduced clock cycle information, and the reproduced clock cycle information is output according to the phase error information and the reproduced clock information, a PLL configuration is used. An effective PLL operation can be performed even with a sampling clock lower than the clock frequency to be reproduced. Therefore, it is not necessary to use a high-speed element in the PLL circuit, the circuit configuration can be simplified, and the cost can be reduced. Further, since the digital PLL is used, no adjustment is required, and the PLL operating environment can be changed in accordance with an operating condition such as a track jump.

Further, at the time of the phase detection, interpolation data obtained by interpolating the input data is output.
By selecting and outputting interpolation data at each reproduction clock timing according to the reproduction clock information, it is possible to obtain an output considering the level,
This is suitable, for example, when performing so-called Viterbi demodulation on the subsequent stage.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a digital clock reproducing apparatus as one embodiment according to the present invention.

FIG. 2 is a block diagram showing an example of a schematic configuration of a device to which the digital clock reproducing device of the embodiment is applied.

FIG. 3 is a diagram for explaining the operation principle of the digital PLL.

FIG. 4 is a diagram illustrating a data restoration operation by a convolution operation.

FIG. 5 is a diagram for explaining an operation of detecting an edge position by linear interpolation.

FIG. 6 is a diagram for explaining calculation of an edge position by linear interpolation.

FIG. 7 is a diagram illustrating an error in an edge position obtained by linear interpolation.

FIG. 8 is a block circuit diagram showing an example of a more specific configuration of a digital clock reproducing device as one embodiment according to the present invention.

FIG. 9 is a diagram for explaining the operation of the embodiment.

FIG. 10 is a diagram showing a frequency relationship in a specific example in which the embodiment is applied to an optical disk reproducing device.

[Explanation of symbols]

 11 RF signal (input data) input terminal 12 Phase detection circuit 13 Clock generation circuit 14 Clock cycle generation circuit 15 Data selector

Claims (3)

(57) [Claims] 1. An edge position is obtained based on input data obtained by sampling an input signal to be clock-reproduced by a predetermined sampling clock, and phase error information between the edge position and the reproduced clock is output. Phase detection means, clock generation means for outputting reproduction clock information based on the phase detection error from the phase detection means and the reproduction clock cycle information, phase error information from the phase detection means, and Clock cycle generating means for outputting the reproduced clock cycle information according to the reproduced clock information, wherein the phase detecting means obtains the input data by linear interpolation.
Output the interpolated interpolation data, and output each reproduction clock timing according to the reproduction clock information.
Data selection means to select and output interpolation data
Digital clock recovery device characterized by providing. 2. The method according to claim 1, wherein the sampling clock frequency is set lower than the reproduction clock frequency, and the clock generation means outputs the clock information including two or more reproduction clock positions within one sampling period. 2. The digital clock reproducing apparatus according to claim 1, wherein: 3. The clock cycle generating means adjusts a reproduction clock cycle according to a result of adding the phase error information from the phase detection means over a predetermined period, and outputs the adjusted reproduction clock cycle information as the reproduction clock cycle information. 2. The digital clock reproducing apparatus according to claim 1, wherein: