JP3308813B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a highly reliable programmable controller in which a plurality of controllers execute the same control program and compare and judge the respective computation results to perform control.

[0002]

2. Description of the Related Art Programmable controllers are used for processing,
It is widely used for controlling industrial systems such as machine control for assembly, control of production lines, plant control for steel and papermaking, water and sewage, and building management. In particular, when reliability is required, such as in public systems and transportation systems, the same control program is executed using a plurality of controllers, and the respective calculation results are compared with each other to determine a correct calculation result and perform control. A highly reliable programmable controller is used.

FIG. 4 shows an example of such a highly reliable programmable controller. In this example, three programmable controllers are used. The programmable controllers 1, 2, and 3 execute the same program, compare the respective operation results with each other, determine the correct operation result by majority logic, and execute the program. Perform control.

[0004] Each programmable controller 1, 2, 3
Are processors 1-1, 2-1 and 3-1 for performing control operations.
And the processor of the programmable controller itself writes the operation result, and the processors of the other two programmable controllers write the operation result.
Dual port memories 1-2 and 1-3, 2-2 and 2
-3, 3-2 and 3-3.

The processor 1-1 is connected to dual port memories 1-2 and 1-3 via a bus 1-12 and to dual port memories 2-2 and 3-2. The processor 2-1 is connected to the dual port memories 2-2 and 2-3 via the bus 2-12 and to the dual port memories 1-2 and 3-3. The processor 3-1 is connected to the dual port memories 3-2 and 3-3 via the bus 3-12, and is also connected to the dual port memories 1-3 and 2-3. Accordingly, the processor 1-1 stores the operation result in the dual port memory 1-2, 1
-3, and the dual port memory 2-2,
3-2, the processor 2-1 can write the operation result to the dual port memories 2-2, 2-3, and also can write the operation result to the dual port memories 1-2, 3-3. 1 can write the operation result to the dual port memories 3-2 and 3-3 and also write the result to the dual port memories 1-3 and 2-3.

Each of the processors 1-1, 2-1 and 3-1 includes:
A control operation (scan) of the program is performed based on a control program stored in a program memory (not shown), and each time the scan is performed, the operation results are collated with each other, and the program control is executed based on the operation result determined by majority decision.

FIG. 5 shows the collation processing of the processor 1-1. When the control operation of one scan (processing 10) is completed, the operation result is written (transferred) to the dual port memories 2-2 and 3-2. (Process 11) is performed, and the calculation result of the processor 2-1 written in the dual port memory 1-2 and the calculation result of the processor 3-1 written in the dual port memory 1-3 are read (Processes 12 and 13). , Collation (comparison) with the operation result of the processor 1-1 itself (Process 1
4) is performed, when all the operation results of the three programmable controllers are equal, it is determined that the operation results have been normally performed. When two operation results among the three operation results are equal and differ only by one operation result, The operation result is discarded, two equal operation results are adopted, and one operation result is determined by majority decision. The processors 2-1 and 3-1 also perform the same collation processing as the processor 1-1.

FIG. 6 shows the timing of the progress of the scan execution of each processor. When the control operation of one scan is completed, the operation results are transferred to each other. When the transfer operation is completed, the transferred operation results and Comparison (judgment)
Processing is performed, one operation result is determined by majority decision, and program control is executed based on the determined operation result. As described above, the program control is performed by the majority decision of the operation results of the three programmable controllers.

[0009]

As described above, in the conventional programmable controller, after the control operation of one scan is completed, the operation results are transferred to each other.
After that, since the comparison and determination processing of the calculation result is performed, there is a problem that the scan time becomes longer and the real-time controllability is impaired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable controller which enables a high-speed scan by shortening the processing time required for comparison and judgment and has improved real-time controllability. It is in.

[0011]

In order to achieve the above object, a programmable controller according to the present invention comprises a processor which scans a control program and repeats a control operation. The plurality of operation results obtained by the control operation are written to a dual-port memory in ascending order of address, and the address output from the processor is compared with the address output from another programmable controller in the same manner to obtain a value. Reading means for selecting a smaller address and reading an operation result written in the selected address of the dual port memory; and a read operation result and an operation result similarly read from another programmable controller. Normal operation when Comprising a determination unit, two programmable controller performs control calculation based on the same control program, to synchronize the start of the scan is performed in parallel with writing and reading and the comparison determination of the plurality of operation results. In a programmable controller having a processor that scans a control program and repeats a control operation, the processor sorts a plurality of operation results obtained by the control operation in ascending order of address each time the control operation ends. Writing to a dual-port memory, comparing the address output from the processor with a plurality of addresses similarly output from a plurality of other programmable controllers and selecting an address with the smallest value, Reading means for reading the operation result written at the selected address; comparing the read operation result with a plurality of operation results similarly read from another plurality of programmable controllers; Judgment means for determining one calculation result, and at least Also, the three programmable controllers perform control calculations based on the same control program, synchronize the scan start time, and write, read, and compare and determine a plurality of calculation results in parallel. (Claim 2) Further, the reading means may be configured such that an input side includes an address bus and a control bus for the processor to write an operation result to the dual port memory, and a similar address bus and control bus drawn from another programmable controller. The output side is connected to an address bus and a control bus for reading an operation result from the dual-port memory, and a plurality of input addresses are compared to select and output a minimum address and output a read command. It comprises address / command generating means. (Claim 3) Further, the determination means is connected to a data bus for reading the operation result from the dual port memory and a similar data bus drawn from another programmable controller, and the plurality of read operation results are read out. And a data comparing means for comparing and judging to determine one operation result. (Claim 4) Further, when the processor finishes the control operation and writes a plurality of operation results to the dual port memory, when the start of writing is earlier than the start of writing of the other programmable controller, Arbitration means for waiting for reading of the operation result until an address is provided is provided, and reading of the operation result is synchronized. (Claim 5) When the determining means determines that there is a difference in the calculation results by comparing the plurality of calculation results, the read address of the dual port memory, each calculation result, and the programmable controller that outputs the calculation result are determined. A maintenance memory for storing the type data to be distinguished is provided. (Claim 6)

[0012]

FIG. 1 shows an embodiment of a programmable controller according to the present invention. This embodiment is an example using three programmable controllers 1, 2, and 3.
Each of the programmable controllers 1, 2, and 3 includes a processor 1-1, 2-1 and 3-1 and a dual port memory 1
-2, 2-2, 3-2, address / command generating circuits (reading means) 1-4, 2-4, 3-4, and data comparing circuits (determining means) 1-5, 2-5, 3 Each processor 1 scans the same control program stored in a program memory (not shown) to perform a control operation, and writes the operation result to the dual port memory 2 each time the scan is performed. . Each address
When each processor 1 writes an operation result, the command generation circuit 4 receives three write commands via the control buses 1-6, 2-6, and 3-6, and outputs the address bus 1-7, Three addresses are input via 2-7 and 3-7, the address having the smallest value is output via address buses 1-10, 2-10 and 3-10, and the control buses 1-9 and 2-9 are output. A read command is output through -9 and 3-9, and the operation result written in the dual port memory 2 is read. Each data comparison circuit 5
The operation result of each processor read from each dual port memory 2 is transmitted to data buses 1-11, 2-11, and 3-1.
1, and one operation result is determined from the three operation results by majority logic.

In the above configuration, each processor 1 scans based on the same control program stored in a program memory (not shown), and executes a control operation of the program. In this case, you can synchronize the start of the scan,
Each time a scan is performed, as shown in FIG. 2, the program control is executed based on the operation result determined by majority decision by comparing the operation results with each other. That is, when the control operation (process 20) in one scan is completed, each processor 1 transmits a plurality of operation results obtained by the control operation to each of the data buses 1-8 and 2-8.
The data is written to each dual port memory 2 via 8 and 3-8 (process 21). At this time, writing is performed in ascending order of the address of each dual port memory. Also,
The write command and address output from each processor 1 for writing are stored in the control buses 1-6, 2-6, and 3-6.
Is input to each address / command generation circuit 4 via the address buses 1-7, 2-7, 3-7, and each address / command generation circuit 4 compares each address and selects the smallest address. Buses 1-10, 2-10, 3
-10, and at the same time control buses 1-9, 2-
A read command is output through 9, 3-9. Therefore, the operation result written in each dual port memory 2 is read out to the data buses 1-11, 2-11 and 3-11. (Process 24). In this case, if the timings at the start of writing of the processors 1 all match, the addresses input to the address / command generation circuits 4 all match, and immediately after the operation result is written, reading is performed. Reading is performed in parallel.

However, when there is a time difference between the timings at the start of writing of each processor 1 for some reason, each address / command generating circuit 4 stops its function until an address is given from all processors (processing 2).
3), the preceding processor writes only the operation result. When an address is given from the processor that has started writing last, each address / command generation circuit 4 selects the smallest address, outputs the address given from the processor that has started writing last, and reads the operation result. . When the preceding processor finishes writing, the address / command generation circuit 4 holds the last address until all addresses match. Therefore, in this case, after the calculation result is written, reading is performed with a delay of several steps, and writing and reading are performed in parallel. FIG. 3 shows a timing chart in this case.

Each time the operation results read from the dual port memories 2 of the programmable controllers 1, 2, and 3 are input to the data comparison circuit 5, each data comparison circuit 5 The results are compared and one operation result is determined by majority logic (Process 2
5). When writing and reading of all calculation results are completed, the next scan can be started (process 27).

As described above, according to the present embodiment, by synchronizing only the scan start points of the control programs of the plurality of programmable controllers, it is possible to completely synchronize the instruction execution level clocks of the processors without completely synchronizing them. The mutual comparison of the calculation results between the programmable controllers becomes possible, and the determination processing time can be performed almost within the transfer (write) processing time.

When each data comparison circuit 5 compares the plurality of operation results and determines that there is a difference between the operation results, the read address of the dual port memory 2, each operation result, and the programmable controller that outputs the operation result By providing a maintenance memory for storing type data for distinguishing the programmable controllers, and by monitoring the stored data, it is possible to easily find a programmable controller having an abnormal operation and improve the maintainability.

In the above description, an example in which three programmable controllers are used has been described. However, three or more programmable controllers can be used. Also, the data comparison circuits 1-5, 2-
Compare the two calculation results with 5 and 3-5 and determine that they are normal. If they do not match, perform processing such as referring to past calculation results and output one calculation result. Function can be implemented using two programmable controllers.

[0019]

According to the present invention, when a plurality of programmable controllers are scanned by the same control program and the operation results are compared with each other to execute program control,
By synchronizing only the scan start time of the control program, it is possible to perform writing, reading, and comparison judgment of a plurality of operation results in parallel without completely synchronizing the clock of the instruction execution level of the processor, The operation results can be compared simultaneously in the background for transferring the operation results, the processing time for the inter-comparison can be shortened, a high-speed scan can be performed, and a programmable controller with improved real-time controllability can be provided. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a programmable controller according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is a configuration diagram of a conventional programmable controller.

FIG. 5 is a flowchart for explaining the operation of the conventional device.

FIG. 6 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

1, 2, 3 ... programmable controller 1-1, 2-1, 3-1 ... processor 1-2, 2-2, 3-2 ... dual port memory 1-4, 2-4, 3-4 ... address Command generation circuit (reading means) 1-5, 2-5, 3-5 ... data comparison circuit (judgment means) 1-6, 2-6, 3-6 ... control bus (write command) 1-7, 2- 7, 3-7 ... address bus (write) 1-8, 2-8, 3-8 ... data bus (write) 1-9, 2-9, 3-9 ... control bus (read command) 1-10, 2-10, 3-10: Address bus (read) 1-11, 2-11, 3-11: Data bus (read)

Claims (6)

(57) [Claims] 1. A programmable controller comprising a processor which scans a control program and repeats a control operation, wherein the processor reads a plurality of operation results obtained by the control operation each time the control operation ends, in ascending order of address. Write to a memory, compare the address output from the processor and the address similarly output from another programmable controller, select the smaller address, select the address of the dual port memory Reading means for reading the written operation result; and determining means for judging a normal operation when the read operation result is equal to the operation result similarly read from another programmable controller. Are based on the same control program Performs control operation, synchronizing the start time point of the scan, the programmable controller and performing in parallel a plurality of operation results in writing and reading and comparison determination. 2. A programmable controller comprising a processor that scans a control program and repeats a control operation, wherein the processor reads a plurality of operation results obtained by the control operation each time the control operation is completed in the order of smaller addresses. Write to a memory, compare the address output from the processor with a plurality of addresses similarly output from a plurality of other programmable controllers, select the address with the smallest value, and select the dual port memory. Reading means for reading out the operation result written to the read address, and comparing the read operation result with a plurality of operation results similarly read from a plurality of other programmable controllers to perform one operation by majority logic. Equipped with determination means for determining results, at least three Programmable controller programmable controller performs control calculation based on the same control program, to synchronize the start of the scan, and performs in parallel a plurality of writing and reading and comparison and determination of the calculation results. 3. The programmable controller according to claim 1, wherein said read means includes an address bus, a control bus, and another programmable controller on an input side for said processor to write an operation result to said dual port memory. The output side is connected to an address bus and a control bus for reading out the operation result from the dual port memory, and a plurality of input addresses are compared to obtain a minimum value. A programmable controller comprising address / command generating means for selectively outputting an address and outputting a read command. 4. The programmable controller according to claim 1, wherein said determination means includes a data bus for reading an operation result from said dual-port memory and a similar data bus drawn from another programmable controller. And a data controller for comparing and judging a plurality of read operation results to determine one operation result. 5. The programmable controller according to claim 1, wherein when the processor finishes the control operation and writes a plurality of operation results to the dual port memory, the start of writing is performed by another programmable controller. A arbitration unit that waits for reading of the operation result until an address is given from another programmable controller when the writing of the operation result is earlier than the start of writing, and synchronizes the reading of the operation result. 6. The programmable controller according to claim 1, wherein said determination means compares a plurality of calculation results and determines that there is a difference between the calculation results.
A programmable controller comprising: a maintenance memory for storing a read address of a dual port memory, each operation result, and type data for distinguishing a programmable controller that has output the operation result.