JP3308460B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
The present invention relates to a data holding circuit such as a latch circuit.

[0002]

2. Description of the Related Art In recent years, dynamic random access memories (DRAMs) have been developed.
s memory), SRAM (static random access memory)
)), As the capacity of semiconductor storage devices increases,
The power consumption tends to increase. Conventionally, great efforts have been made to reduce power consumption during read operations and write operations. However, since the semiconductor storage device is driven by a battery particularly in a portable device, it is important not only to reduce power consumption during operation but also to reduce power consumption during standby in order to extend the life of the battery.

[0003] K. Sasaki et al., “A2
3ns 4Mb CMOS SRAM with 0.
5μA Standby Current ”, ISSC
CDigest of Technical Paper
rs, Feb. 1990, p. According to 130-131, the flip-flops required for the SRAM memory cells are composed of two CMOS inverters. Two NMOs
Polysilicon P as a load element of each S transistor
By employing the MOS transistors, an SRAM with a lower standby current is realized as compared with a case where a polysilicon resistor is used as a load element. In addition, the area of the memory cell is reduced by employing a polysilicon PMOS transistor having a two-layer structure.

Even if the flip-flop of the SRAM cell is simply composed of two CMOS inverters as described above,
The off-leak current of the OS transistor remains as a problem. Accordingly, the standby power consumption of the SRAM has not been sufficiently reduced.

As the capacity of the SRAM increases, the total amount of off-leak current tends to increase. Further, it is necessary to lower the threshold voltage of the MOS transistor in accordance with the lowering of the power supply voltage. However, the lowering of the threshold voltage also increases the off-leak current of each MOS transistor. Therefore, Japanese Unexamined Patent Application Publication Nos. Hei 5-210976 and Hei 6-29834 disclose an MT (Multiple Threshold) applicable to peripheral circuits of a semiconductor memory device.
ld) -CMOS technology has been proposed. This technology is
A MOS transistor having a high threshold voltage is interposed as a switch between a MOS transistor having a low threshold voltage and a power supply, and the switch is opened during standby. The off-leak current of the transistor is limited to a small value by the MOS transistor forming the switch.

[0006]

The above-mentioned MT-CMOS technology has not been able to reduce the off-leak current in a flip-flop type memory cell. This is because it was not possible to prevent the extinction of the data held in the memory cells during standby.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the off-leakage current of a transistor constituting a data holding circuit in a flip-flop type data holding circuit so as to reduce power consumption during standby while preventing the held data from disappearing. Is to do.

[0008]

In order to achieve the above object, the present invention provides a power supply for at least one of two power supply lines of a flip-flop constituting a data holding circuit in a semiconductor memory device or the like. The line is set to the floating state intermittently during standby.

For example, when the power supply line on the ground side is in a floating state, the power supply line is charged due to the off-leak current of the transistor constituting the flip-flop, and the power supply line voltage is raised. As a result, the off-leak current of the transistor decreases. However, if the voltage of the power supply line on the ground side continues to rise, the data held in the flip-flop cannot be read in a short time, and the data eventually disappears. Therefore, in the present invention, the power supply line of the flip-flop is set to the floating state intermittently during standby.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention.
2 shows a configuration of a RAM chip. The SRAM chip of FIG. 1 includes a memory cell array 10 and an address buffer 11
, A row decoder 12, a column decoder and an amplifier (including a sense amplifier and a write amplifier) 13, and an input / output circuit (I / O circuit) 16. The memory cell array 10 includes m × n (m and n are integers) memory cells (not shown), m word lines WL, and n pairs of bit lines BL and XBL. Address buffer 11
Receives the external address EA, supplies the row address RA to the row decoder 12, and supplies the column address CA to the column decoder and the amplifier 13, respectively. The row decoder 12 raises the voltage of one word line selected from the m word lines WL of the memory cell array 10 according to the row address RA. At the time of the read operation of the SRAM chip, the column decoder and the amplifier 13 reads the bit lines BL and XBL from the n memory cells connected to the word line WL selected by the row decoder 12 among the m × n memory cells. K selected from the output n-bit data signals according to the column address CA (k is n
A smaller integer) bit data signal is input to the input / output circuit 16.
Supply to The k-bit data signal supplied to the input / output circuit 16 is output to the outside of the chip via the data terminal DIO. At the time of a write operation of the SRAM chip, the input / output circuit 16 supplies a k-bit data signal applied to the data terminal DIO from outside the chip to the column decoder and the amplifier 13. The k-bit data signal supplied to the column decoder / amplifier 13 is a k-bit data signal selected according to the column address CA of the n memory cells connected to the word line WL selected by the row decoder 12. Bit lines BL, XBL
To be written through.

The SRAM chip shown in FIG.
4 and an activation circuit 15. The voltage control circuit 14 is a circuit for controlling the voltage of the ground power supply line of the flip-flop constituting each memory cell in the memory cell array 10, that is, the cell power supply line voltage VCN.
The activating circuit 15 receives the chip select signal CS, generates an internal chip select signal ICS for activating each of the address buffer 11, the row decoder 12, and the column decoder and the amplifier 13, and controls the operation of the voltage control circuit 14. An activation signal ACT for control is generated.

FIG. 2 shows a part of the memory cell array 10 and the internal configuration of each of the voltage control circuits 14 in FIG. As shown in FIG. 2, n memory cells 21 are connected to one word line WL, and the n memory cells 21
Are connected to a pair of bit lines BL and XBL. Each of the pair of bit lines BL and XBL is a PMOS
The power supply VDD is connected via the transistors QP1 and QP2. These two PMOS transistors QP
1 and QP2 constitute a precharge circuit 22, and a gate of each of the PMOS transistors QP1 and QP2 is supplied with a precharge signal PRE. Each memory cell 21 has two PMOS transistors QP3, QP
4 and four NMOS transistors QN1, QN2, Q
N3 and QN4. Of these, two P
The MOS transistors QP3 and QP4 and the two NMOS transistors QN3 and QN4 are connected to each other to form one flip-flop. N in FIG.
1 and N2 are first and second storage nodes of the flip-flop, respectively. The first storage node N1 is NM
One bit line BL via OS transistor QN1
And the second storage node N2 is connected to the NMOS transistor QN
2 are connected to the other bit lines XBL via
The gates of both NMOS transistors QN1 and QN2 are connected to word line WL. Further, the sources of the PMOS transistors QP3 and QP4 are connected to the positive voltage power supply line 23, and the sources of the NMOS transistors QN3 and QN4 are connected to the ground power supply line 24, respectively. The positive voltage power supply line 23 of each memory cell 21 is directly connected to the power supply VDD (its voltage is positive). The ground power supply line 24 of each memory cell 21 is connected to a power supply VSS (the voltage is a ground voltage, that is, 0 V) via another NMOS transistor QN5. The NMOS transistor QN5 constitutes the voltage control circuit 14, and an activation signal ACT is applied to the gate of the NMOS transistor QN5. The voltage of the ground power supply line 24 is the cell power supply line voltage VCN controlled by the voltage control circuit 14.

According to the configuration of FIG. 2, the NMOS transistor QN5 is turned on during the "H" level of the activation signal ACT, the ground power supply line 24 is connected to the power supply VSS, and the "L" level of the activation signal ACT is activated. , The NMOS transistor QN5 is turned off, and the ground power supply line 24 is connected to the power supply VS.
Separated from S. The chip select signal C shown in FIG.
During the standby time of the SRAM chip in which S is held at the “L” level, the activation signal ACT is intermittently set to the “L” level, so that the ground power supply line 24 intermittently enters a floating state. In addition, when the SRAM chip is on standby, the precharge signal PRE keeps the “L” level.
As a result of the OS transistors QP1 and QP2 being kept on, both bit lines BL and XBL are precharged to “H” level. Further, at the time of standby of the SRAM chip,
Since the word line WL holds the “L” level, the NMOS
Transistors QN1 and QN2 hold the off state. Therefore, each memory cell 21 applies a complementary voltage representing one-bit data to first and second storage nodes N1, N2.
To hold. For example, assuming that the first storage node N1 holds an “L” level (voltage of the power supply VSS) and the second storage node N2 holds an “H” level (voltage of the power supply VDD), respectively. Constituting 4
The states of the transistors QP3, QN3, QP4, and QN4 are off, on, on, and off, respectively.

As described above, when the SRAM chip is on standby, the four transistors (the transistors QN1, QN2, QP3, QN3 in the above example) in each memory cell 21 are used.
4) holds the off state. However, three of the transistors (the transistors QN1 and QN in the above example)
An off-leak current flows through P3 and QN4). In FIG.
The off-leak current flowing through each channel of the three transistors QN1, QP3, QN4 is I
1, I2 and I3. These off-leak currents I1, I2, and I3 are all supplied from the power supply VDD and are the main cause of standby power consumption of the SRAM chip. N memory cells 2 shown in FIG.
1 is equal to n × (I1 + I2 +
I3).

In the off period of the NMOS transistor QN5 forming the voltage control circuit 14, the stray capacitance attached to the ground power supply line 24 is the total amount of off leak current It = n × (I1 + I
2 + I3), the cell power line voltage V
CN gradually rises from the voltage (0 V) of the power supply VSS. Here, it is assumed that the off-leak current of the NMOS transistor QN5 is negligibly small as compared to the total current It.

FIG. 3 shows a temporal change of the cell power supply line voltage VCN when the NMOS transistor QN5 is kept off. When the NMOS transistor QN5 transitions from the ON state to the OFF state at time 0, the cell power supply line voltage VCN
Gradually rises from the voltage of the power supply VSS (0 V) toward the voltage of the power supply VDD. However, since the off-leak currents I1, I2, and I3 decrease due to the increase in the cell power supply line voltage VCN, the amount of increase in the cell power supply line voltage VCN per unit time decreases. The decrease in the off-leak current I1 of the NMOS transistor QN1 is caused by the cell power supply line voltage VC
As the voltage of N rises, the holding voltage of the first storage node N1, that is, the source voltage of the NMOS transistor QN1 is gradually raised from the "L" level.
This is because the gate-source voltage of the S transistor QN1 becomes negative, and the drain-source voltage thereof decreases. Since the substrate of the SRAM chip is fixed to the voltage of the power supply VSS, the NMOS transistor QN1
Is raised from the “L” level (voltage of the power supply VSS), this is equivalent to applying a negative bias voltage to the substrate of the source of the NMOS transistor QN1.
Off-leak current I1 of S transistor QN1 further decreases. Off-leak current I of PMOS transistor QP3
2 decreases with the rise of the cell power supply line voltage VCN, the holding voltage of the first storage node N1, that is, the PM
This is because the absolute value of the drain-source voltage of the PMOS transistor QP3 decreases as a result of the drain voltage of the OS transistor QP3 being gradually raised from the “L” level. The decrease in the off-leak current I3 of the NMOS transistor QN4 is caused by the fact that the source voltage of the NMOS transistor QN4 is gradually increased with the rise of the cell power supply line voltage VCN, so that the drain-source voltage of the NMOS transistor QN4 decreases. Because. When the source voltage of the NMOS transistor QN4 is raised, the NMOS transistor QN4
Is equivalent to the application of a negative bias voltage to the substrate with respect to the source of
Off-leak current I3 of S transistor QN4 further decreases. As described above, the off-leak currents I1, I2, and I3 all decrease due to the increase in the cell power supply line voltage VCN. It is to be noted that NMO is used for the high-speed operation of the memory cell 21.
The threshold voltage of S transistor QN1 can be reduced. Generally, a MOS transistor having a low threshold voltage has a large off-leak current. However, NM
The off-leak current I1 of the OS transistor QN1 is increased when the cell power supply line voltage VCN rises.
This is significantly reduced by the negative gate-source voltage of N1. Therefore, the NMOS transistor Q
The threshold voltage of N1 may be reduced. NMO
The same applies to S transistor QN2.

As shown in FIG. 3, when the NMOS transistor QN5 keeps turning off, the cell power supply line voltage VCN reaches the first limit voltage Vr at time Tr, and further reaches the second limit voltage Vr at time Th.
(Vh> Vr). While the second storage node N2 holds the "H" level, the holding voltage of the first storage node N1 gradually rises from the "L" level as the cell power supply line voltage VCN rises as described above. Can be When the hold voltage of the first storage node N1 is the first
Above the threshold voltage Vr, it becomes impossible to read the data stored in the memory cell 21 within a certain time. Further, when the holding voltage of the first storage node N1 becomes higher than the second limit voltage Vh, the data stored in the memory cell 21 cannot be read again. This means that the stored data has disappeared. Therefore, in the present embodiment, the cell power supply line voltage VCN
The activation signal ACT is set to the “H” level so that the NMOS transistor QN5 is turned on each time the voltage reaches the first limit voltage Vr or the second limit voltage Vh. That is, when the SRAM chip is on standby, the activation signal ACT is intermittently set to the “L” level.

FIG. 4 shows an example of the operation of the SRAM chip of FIG. 1 in a standby state based on the first limit voltage Vr.
According to FIG. 4, the activation signal ACT is “L” during the period T1.
Level, the NMOS transistor QN5 is off. Therefore, the cell power supply line voltage VCN is
The voltage rises from the voltage of SS (0 V), and the total amount It of the off-leak current falls from the maximum current amount Imax. At the end of the period T1, the cell power supply line voltage VCN becomes equal to the first limit voltage V.
r, and the total amount It of the off-leakage current reaches the current amount Ir corresponding to the first limit voltage Vr. At this point, the period T2 starts, and the activation signal ACT is set to the “H” level. As a result, the NMOS transistor QN5 is turned on. As a result, the cell power supply line voltage VCN is returned to the voltage of the power supply VSS, and the total amount It of the off-leak current is returned to the maximum current amount Imax. Hereinafter, the period T1 and the period T2 are repeated. NMOS transistor QN5
Keeps turning on, the total amount It of the off-leak current always becomes the maximum current amount Imax, whereas according to FIG.
Since the total amount It of the off-leakage current is reduced to 1, SR
The standby power consumption of the AM chip is reduced.

FIG. 5 shows an example of the operation of the SRAM chip of FIG. 1 in a standby state based on the second limit voltage Vh.
According to FIG. 5, the activation signal ACT is “L” during the period T1.
Level, the NMOS transistor QN5 is off. Therefore, the cell power supply line voltage VCN is
The voltage rises from the voltage of SS (0 V), and the total amount It of the off-leak current falls from the maximum current amount Imax. At the end of the period T1, the cell power supply line voltage VCN reaches the second limit voltage Vh higher than the first limit voltage Vr, and the total amount of off-leakage current It becomes the current amount Ih corresponding to the second limit voltage Vh. Reach. At this point, the period T2 starts, and the activation signal ACT is set to the “H” level. This allows NMO
As a result of turning on the S transistor QN5, the cell power supply line voltage VCN is returned to the voltage of the power supply VSS, and
The total amount It of the off-leak current is returned to the maximum current amount Imax. Hereinafter, the period T1 and the period T2 are repeated. According to FIG. 5, the total amount It of the off-leak current is reduced over a longer period than in the case of FIG.
The standby power consumption of the AM chip is further reduced. SRA
When the chip select signal CS is fixed at the “L” level and it is known that the read operation and the write operation of the memory cell 21 are not performed for a while, as in the battery backup even during the standby of the M chip. Is suitable for the operation based on the second limit voltage Vh as shown in FIG. On the other hand, the chip select signal CS
If it is necessary to start a read operation or a write operation of the memory cell 21 immediately in response to the change in
The operation based on the first limit voltage Vr as described above is suitable. It is preferable to use the standby operation depending on the case.

It is preferable that the cycle of the activation signal ACT, that is, the sum of the lengths of the periods T1 and T2 be kept constant. Considering manufacturing variations and temperature-dependent variations in the threshold voltage of each transistor constituting the memory cell 21 in FIG. 2, the maximum value I of the total amount of off-leakage current is considered.
It can be seen that max varies. Maximum current Imax
Is large, during the period T1, the cell power supply line voltage VCN rapidly rises from the voltage of the power supply VSS (0 V), and as a result, the total amount of off-leakage current It rapidly drops from the maximum current amount Imax. Conversely, when the maximum current amount Imax is small, the cell power supply line voltage V
As a result of the CN slowly rising from the voltage of the power supply VSS (0 V), the total amount of off-leakage current It slowly decreases from the maximum current amount Imax. That is, regardless of the magnitude of the maximum current amount Imax, the average value of the total amount of off-leak current It is kept substantially constant.

FIG. 6 shows an example of a read sequence of the SRAM chip of FIG. According to FIG. 6, the activation signal AC is synchronized with the rising edge of the chip select signal CS.
T rises, and then the voltage of the word line WL rises. The precharge signal PRE in FIG. 2 is generated based on the transition of the external address EA, and the bit line BL,
When the precharge of XBL is completed, the precharge signal PRE
Are set to the “H” level. "H" level activation signal A
Since the NMOS transistor QN5 of the voltage control circuit 14 turns on in response to CT, the cell power supply line voltage VCN is reduced to the voltage of the power supply VSS. Cell power line voltage VC
When N is lowered, the voltage of one of the first and second storage nodes N1 and N2 which has been raised to the "L" level is reduced, and the bit line BL, BL, Accurate reading of data to XBL is guaranteed. At the end of the read operation, the chip select signal CS is returned to "L" level. As the activation signal ACT falls in synchronization with the fall of the chip select signal CS, the cell power supply line voltage VCN starts to rise. When the standby operation based on the first limit voltage Vr as shown in FIG. 4 is employed, the activation signal A is activated after the voltage of the word line WL is raised.
Even when the CT is activated, accurate data reading from each memory cell 21 to the bit lines BL and XBL is achieved.

FIG. 7 shows an example of a write sequence of the SRAM chip of FIG. Since the write sequence in FIG. 7 is the same as the read sequence in FIG. 6, detailed description of the former is omitted.

Next, four internal configuration examples of the activation circuit 15 in FIG. 1 will be described. However, the activation signal ACT
Only a circuit configuration example for generating the internal chip select signal ICS will be described, and a description of the circuit configuration for generating the internal chip select signal ICS will be omitted.

FIG. 8 shows an example of the internal configuration of the activation circuit 15. 8, 31 is an oscillation circuit, 32
Is a waveform shaping circuit, 33 is a NOR circuit, and 34 is an inverter. The oscillation circuit 31 generates a signal having a constant frequency f regardless of the logic level of the chip select signal CS. The waveform shaping circuit 32 converts a clock signal CLK (its frequency is f) obtained by shaping the waveform of the signal generated by the oscillation circuit 31.
It is supplied to one input of a NOR circuit 33. NOR circuit 3
The other input of 3 is supplied with a chip select signal CS. The output of the NOR circuit 33 is converted into an activation signal ACT by an inverter 34.

According to the activation circuit 15 of FIG. 8, when the SRAM chip in which the chip select signal CS is held at the "L" level is on standby, one input of the NOR circuit 33, that is, the clock signal CLK of the frequency f is changed to " The transition is repeatedly made from the "H" level to the "L" level and from the "L" level to the "H" level. Therefore, activation signal ACT output from inverter 34 attains an “L” level intermittently according to frequency f of clock signal CLK. Here, the frequency f of the clock signal CLK is determined according to the length of the periods T1 and T2 in FIG. 4 or the length of the periods T1 and T2 in FIG. During a read operation and a write operation of the SRAM chip, the activation signal ACT rises by the NOR circuit 33 and the inverter 34 in synchronization with the rise of the chip select signal CS.

FIG. 9 shows another example of the internal configuration of the activation circuit 15. The configuration of FIG. 9 corresponds to the waveform shaping circuit 3 in FIG.
The level detection circuit 35 and the drive circuit 36 are inserted between the second circuit 2 and one input of the NOR circuit 33. The level detection circuit 35 generates an “L” active detection signal DET indicating that the cell power supply line voltage VCN has reached the first limit voltage Vr or the second limit voltage Vh. The generated detection signal DET is inverted by the drive circuit 36 and supplied to one input of the NOR circuit 33. The clock signal CLK generated by the oscillation circuit 31 and the waveform shaping circuit 32 has a frequency f '. In order to reduce the power consumption of the level detecting circuit 35 itself, the level detecting circuit 35 determines the magnitude of the cell power supply line voltage VCN only during the “L” level period of the clock signal CLK having the frequency f ′. ing.

FIG. 10 shows the internal configuration of the level detection circuit 35 in FIG. FIG. 10 shows a reference voltage generation circuit 41 for intermittently generating a reference voltage Vref2 in accordance with a clock signal CLK having a frequency f ', and the generated reference voltage Vref2 and the cell power supply line voltage VCN at a frequency f'. A comparison circuit 42 for performing intermittent comparison according to a clock signal CLK is shown.

The reference voltage generation circuit 41 includes one inverter 43 and three PMOS transistors QP21, QP
22, QP23 and three NMOS transistors QN2
1, QN22, QN23 and two capacitors C1, C
And 2. Of these, the two transistors QP21 and QN21 are the first switch, the other two transistors QP22 and QN22 are the second switch, and the other two transistors QP32 and QN32 are the third switch, respectively. Make up. Transistor QP2
1, QN21 is connected to power supply VD
It is interposed between D and the node of the reference voltage Vref1, and is controlled to close during the “L” level of the clock signal CLK and open during the “H” level of the clock signal CLK. A second circuit composed of transistors QP22 and QN22
Is connected between the node of the reference voltage Vref1 and the reference voltage Vre.
It is interposed between the node f2 and the node, and is controlled so as to be opened during the "L" level of the clock signal CLK and closed during the "H" level of the clock signal CLK. The third switch constituted by the transistors QP23 and QN23 is interposed between the node of the reference voltage Vref2 and the power supply VSS, and is closed during the "L" level of the clock signal CLK and at the "H" level of the clock signal CLK. It is controlled to open during the period. A capacitor C1 is interposed between the node of the reference voltage Vref1 and the power supply VSS, and another capacitor C2 is interposed between the node of the reference voltage Vref2 and the power supply VSS.

The comparison circuit 42 is composed of two PMOS transistors QP24 and QP25 and three NMOS transistors QN24, QN25 and QN26.
Among them, four transistors QP24, QP25, Q
N24 and QN25 are connected to each other so as to form a well-known comparison circuit connected to the power supply VDD. NMO
The reference voltage Vref2 is applied to the gate of the S transistor QN24.
However, the cell power supply line voltage VCN is applied to the gate of the NMOS transistor QN25. A connection node between the PMOS transistor QP25 and the NMOS transistor QN25 is a node for outputting the detection signal DET. The feature of the comparison circuit 42 shown in FIG.
The point is that the NMOS transistor QN26 is interposed between the power supply VSS and the connection node between the source of the S transistor QN24 and the source of the NMOS transistor QN25. The gate of this NMOS transistor QN26 has
A clock signal CLK is supplied.

FIG. 11 shows the operation of the level detection circuit 35 of FIG. According to FIG. 11, the clock signal CLK is at the “L” level during the period t1. Clock signal C
While LK is at “L” level, reference voltage generation circuit 41
, The first switch including the transistors QP21 and QN21 is closed, and the transistors QP22 and QN21 are closed.
The second switch constituted by 22 is open, and the third switch constituted by transistors QP32 and QN32 is closed. Therefore, one capacitor C1 is connected to the power supply VD
D, and the other capacitor C2 is connected to the power supply V
It is discharged to the voltage of SS (0 V). That is, the period t1
Then, the first and second reference voltages Vref1 and Vref2 are voltages represented by Vref1 = VDD Vref2 = VSS (= 0V), respectively. In the period t2, the clock signal CLK is at the “H” level. Clock signal CL
When K becomes “H” level, the transistors QP21, QP
The first switch composed of N21 is open, the second switch composed of transistors QP22 and QN22 is closed, and the third switch composed of transistors QP32 and QN32 is open. Therefore, in the period t2, 2
As a result of the charge redistribution between the capacitors C1 and C2, the first and second reference voltages Vref1 and Vref2 become voltages represented by Vref1 = Vref2 = {1 / (1 + r)} VDD. Where r = C2 / C1, V
SS = 0V. In this period t2, the second reference voltage Vref2 is equal to the first limit voltage Vr or the second limit voltage Vh.
(See FIG. 3), two capacitors C
A ratio r of the capacitance of C1 and C2 is set. Comparison circuit 42
Are turned off in the period t1 and turned on in the period t2. Therefore, the comparison circuit 42 compares the cell power supply line voltage VCN with the reference voltage Vref2 only during the period t2, and the cell power supply line voltage VCN becomes equal to the reference voltage Vref2, that is, the first limit voltage Vr or the second limit voltage Vh. When it has reached, an "L" level detection signal DET is generated.

Now, when the reference voltage generation circuit 41 in FIG. 10 is replaced with a well-known resistance voltage division type reference voltage generation circuit, the power supply VDD is changed to the power supply VSS in the reference voltage generation circuit.
As a result, the reference voltage generation circuit always consumes power. NMO in the comparison circuit 42 of FIG.
Even when the source of the S transistor QN24 and the source of the NMOS transistor QN25 are directly connected to the power supply VSS, a current always flows from the power supply VDD to the power supply VSS in the comparison circuit, so that the comparison circuit always consumes power. On the other hand, according to the level detection circuit 35 of FIG. 10, the reference voltage generation circuit 41 consumes power only during the charging period of the capacitor C1 in the period t1, and the comparison circuit 42
Consumes power only during the period t2. That is, the period t1
During the period other than the charging period of the capacitor C1, neither the reference voltage generation circuit 41 nor the comparison circuit 42 consumes power. Therefore, the level detection circuit 35 of FIG.
According to this, the power consumption in the level detection circuit 35 is reduced.

FIG. 12 shows still another example of the internal configuration of the activation circuit 15. 12, 31a is a first oscillation circuit, 31b is a second oscillation circuit, 32a is a waveform shaping and switching circuit, 33 is a NOR circuit, and 34 is an inverter. The first oscillation circuit 31a generates a signal having a constant frequency f1 determined according to the lengths of the periods T1 and T2 in FIG. Second oscillation circuit 31b
Generates a signal having a constant frequency f2 determined according to the lengths of the periods T1 and T2 in FIG. The waveform shaping and switching circuit 32a outputs the mode switching signal M
The signal of the frequency f1 generated by the first oscillation circuit 31a and the second oscillation circuit 3
1b, the clock signal CL obtained by shaping the waveform of any of the signals of the frequency f2
K (its frequency is f1 or f2) is supplied to one input of the NOR circuit 33. A chip select signal CS is supplied to the other input of the NOR circuit 33. N
The output of the OR circuit 33 is converted into an activation signal ACT by an inverter 34.

According to the activation circuit 15 of FIG. 12, the standby operation based on the first limit voltage Vr as shown in FIG.
It can be easily used in the standby operation based on the second limit voltage Vh as shown in FIG.

FIG. 13 shows still another example of the internal configuration of the activation circuit 15. In FIG. 13, 31c is an oscillation circuit, 32 is a waveform shaping circuit, 35a is a first level detection circuit, 35b is a second level detection circuit, 36 is a drive circuit,
33 is a NOR circuit, and 34 is an inverter. The oscillation circuit 31c generates a signal having a different frequency f1 'or f2' (f1 '>f2') according to the logic level of the mode switching signal MOD. The waveform shaping circuit 32
A clock signal CLK (its frequency is f1 'or f2') obtained by shaping the waveform of the signal generated by the oscillation circuit 31c is supplied to the first and second level detection circuits 35a and 35b. . Specifically, the frequency f2 '
Is longer than the "L" level period of the clock signal CLK having the frequency f1 '. First and second level detection circuits 35
a and 35b are configured so that only one of them operates according to the logic level of the mode switching signal MOD. The first level detection circuit 35a detects the cell power line voltage V
A detection signal indicating that CN has reached the first limit voltage Vr is generated in accordance with a clock signal CLK having a frequency f1 '. The second level detection circuit 35b generates a detection signal indicating that the cell power supply line voltage VCN has reached the second limit voltage Vh in accordance with the clock signal CLK having the frequency f2 '. The internal configuration of each of the first and second level detection circuits 35a and 35b is substantially the same as the configuration shown in FIG. The detection signal generated by one of the first and second level detection circuits 35a and 35b is supplied to one input of the NOR circuit 33 via the drive circuit 36. The other input of the NOR circuit 33 includes
A chip select signal CS is supplied. NOR circuit 33
Is converted into an activation signal ACT by an inverter 34.

According to the activation circuit 15 of FIG. 13, the standby operation based on the first limit voltage Vr as shown in FIG. 4 using the first level detection circuit 35a and the second level detection circuit It is easy to properly use the standby operation based on the second limit voltage Vh as shown in FIG.
In addition, the clock signal is generated by the oscillation circuit 31c so that the non-consumption period of the power in the second level detection circuit 35b is extended as compared with the case of the first level detection circuit 35a in accordance with the use of the standby operation. The frequency of CLK is changed. Note that the oscillation circuit 31c may be configured to generate a signal having a constant frequency regardless of the logic level of the mode switching signal MOD.

Instead of intermittently setting the ground power supply line 24 in FIG. 2 to a floating state during standby, an element having a constant impedance may be interposed between the ground power supply line 24 and the power supply VSS. . The impedance element has a function of limiting a floating width of the cell power supply line voltage VCN to a predetermined range.

FIG. 14 shows an SR according to another embodiment of the present invention.
2 shows a configuration of an AM chip. The SRAM chip of FIG. 14 has four blocks (BLK0 to BLK3) 121 to
124, the address buffer 111, and the activation circuit 11
5 and an input / output circuit (I / O circuit) 116. Each of the four blocks 121 to 124 corresponds to S
Similarly to the RAM chip, the memory chip includes a memory cell array, a row decoder, a column decoder and an amplifier (including a sense amplifier and a write amplifier), and an NMOS transistor (see FIG. 2) for controlling the cell power supply line voltage VCN. Voltage control circuit. The address buffer 111 receives the external address EA, and stores the row address RA and the column address CA in the four blocks 121 to
, And a 2-bit block address BA is supplied to the activation circuit 115. The input / output circuit 116
It is interposed between the blocks 121 to 124 and the data terminal DIO. The activating circuit 115 receives the chip select signal CS and the block address BA, generates an internal chip select signal ICS for activating the address buffer 111, and generates four blocks 121 to 124.
And internal chip select signals ICS0 to ICS3 for activating a row decoder, a column decoder and an amplifier in each of the four blocks, respectively.
Activation signals ACT0 to ACT3 for controlling the operation of the voltage control circuit in each of the circuits 21 to 124 are generated.

FIG. 15 shows an example of the internal configuration of the activation circuit 115 in FIG. However, here, only a circuit configuration example for generating the activation signals ACT0 to ACT3 will be described, and the internal chip select signals ICS and ICS0 to ICS0 will be described.
The description of the circuit configuration for generating the ICS3 is omitted. 15, reference numeral 131 denotes an oscillation circuit; 132, a waveform shaping circuit; 133a to 133d, NOR circuits;
4a to 134d are inverters, 141 is a decoder, 14
2a to 142d are AND circuits. Oscillation circuit 131
Generates a signal having a constant frequency f regardless of the logic level of the chip select signal CS. The waveform shaping circuit 132 is a clock signal C obtained by shaping the waveform of the signal generated by the oscillation circuit 131.
LK (its frequency is f) is supplied to one input of each of the four NOR circuits 133a to 133d. The decoder 141 decodes a given 2-bit block address BA. The four decode outputs of the decoder 141 are connected to four AND circuits 142a to 142a-1.
42d is provided to one input of each. The four ANs
A chip select signal CS is supplied to the other input of each of the D circuits 142a to 142d. The output of each of the four AND circuits 142a to 142d is connected to the four NO circuits.
It is supplied to the other input of each of the R circuits 133a to 133d. Outputs of the four NOR circuits 133a to 133d are converted into activation signals ACT0 to ACT3 by four inverters 134a to 134d, respectively.

In the standby state of the SRAM chip shown in FIG. 14 in which the chip select signal CS is held at "L" level, FIG.
5, one input of each of the four NOR circuits 133a to 133d, that is, the clock signal CLK of the frequency f repeatedly changes from "H" level to "L" level and from "L" level to "H" level. Transition. Therefore, 4
Activation signals ACT0 to ACT3 output from inverters 134a to 134d intermittently and simultaneously go to “L” level according to frequency f of clock signal CLK. As a result, in each of the four blocks 121 to 124, the ground power supply line of the flip-flop constituting the memory cell is intermittently brought into a floating state, so that standby power consumption of the SRAM chip is reduced.

In the read operation and the write operation of the SRAM chip of FIG. 14, only one of the four AND circuits 142a to 142d in FIG. 15 is selected by the decoder 141 in accordance with the block address BA. You. Then, the four NOR circuits 133a to 133d
Of the ANDs selected by the decoder 141
An “H” level signal synchronized with the rise of the chip select signal CS is supplied to only one input of one NOR circuit corresponding to the circuit. Therefore, four activation signals A
Only one activation signal selected according to the block address BA among CT0 to ACT3 rises in synchronization with the rise of the chip select signal CS. Thereby, the cell power supply line voltage VC of only one of the four blocks 121 to 124 that is actually accessed is
N is reduced to the voltage of the power supply VSS. That is, the cell power supply line voltages V of the remaining three unaccessed blocks
CN continues to rise and off-leakage current is reduced over time.

The portion constituted by the oscillation circuit 131 and the waveform shaping circuit 132 in FIG. 15 can be modified like the corresponding portion in FIG. 9, FIG. 12, or FIG.

FIG. 16 shows a modification of the voltage control circuit 14 in FIG. According to FIG. 16, each memory cell 21
Not only is the ground power supply line 24 connected to the power supply VSS via the NMOS transistor QN5, but also the positive voltage power supply line 23 of each memory cell 21 is connected to the PMOS transistor QP.
5 is connected to the power supply VDD. Both transistors QP5 and QN5 are connected to the positive voltage power line 23 and the ground power line 2
4, the cell power supply line voltages VCP and VC
And a voltage control circuit 14 for simultaneously controlling N. The first activation signal ACTP is provided at the gate of the PMOS transistor QP5, and the second activation signal ACTN is provided at the gate of the NMOS transistor QN5. Each given.

According to the configuration of FIG. 16, when the SRAM chip is on standby, the first and second activation signals ACTP and ACTP are activated.
As a result, the positive voltage power supply line 23 and the ground power supply line 24 both intermittently enter a floating state. This allows
The substrate bias effect is exerted also in the PMOS transistor QP3 or QP4 in each memory cell 21, and the effect of reducing the off-leak current in each memory cell 21 and the effect of reducing the standby power consumption of the SRAM chip in FIG. It becomes even larger than. The NMO in FIG.
The arrangement of S transistor QN5 is omitted, and ground power supply line 2
4 may be directly connected to the power supply VSS.

As described above, according to each of the above embodiments, the off-leak current of the transistor constituting the flip-flop of each memory cell 21 is reduced by devising the circuit configuration, and the standby power consumption of the SRAM chip is reduced. Is done. Further, since the off-leak current of the transistor is reduced, the threshold voltage of each transistor can be reduced. Therefore, a high-speed and low-power-consumption SRAM chip can be easily realized. That is, a high-speed SRAM suitable for driving a battery in a portable device can be provided.

In the operation example of the SRAM chip during standby shown in FIG. 4, every time the cell power supply line voltage VCN reaches the first limit voltage Vr, the cell power supply line voltage VCN is changed to the power supply VSS.
, The cell power supply line voltage VCN may be pulled back to a power supply voltage (positive voltage) between the first limit voltage Vr and the power supply VSS. As a result, the effect of reducing the off-leak current in each memory cell and the effect of reducing the standby power consumption of the SRAM chip are further increased. The same applies to the standby operation example of FIG. 5 based on the second limit voltage Vh.

Each of the above embodiments relates to an application example of the present invention to an SRAM chip. However, the present invention can be applied not only to a single memory chip but also to an embedded memory, for example, a memory core built in a microprocessor.

FIG. 17 shows an application example of the present invention to a latch circuit in a certain semiconductor integrated circuit. The latch circuit of FIG. 17 includes a latch cell 51 for holding data,
A voltage control circuit 52 for controlling cell power supply line voltages VCP, VCN, and complementary internal clock signals LCK, XLC
And an internal clock generation circuit 53 for generating K. Latch cell 51 and internal clock generation circuit 53
Share a positive voltage power supply line 54 and a ground power supply line 55. Positive voltage power supply line 54 is connected to PMOS transistor QP36.
To the power supply VDD (its voltage is positive), and the ground power supply line 55 to the power supply VSS (the voltage is the ground voltage, that is, 0 V) via the NMOS transistor QN36.
Connected to each other. Both transistors QP36,
QN36 constitutes a voltage control circuit 52 for simultaneously controlling the voltages of the positive voltage power supply line 54 and the ground power supply line 55, that is, the cell power supply line voltages VCP and VCN. The gate of the PMOS transistor QP36 has a 1
The activation signal ACTP of the NMOS transistor QN3
The gates 6 are supplied with the second activation signal ACTN.

The latch cell 51 includes five PMOS transistors QP31, QP32, QP33, QP34, QP
35 and five NMOS transistors QN31, QN3
2, QN33, QN34, and QN35. Among them, two PMOS transistors QP31,
QP32 and two NMOS transistors QN32, QN32
N31 forms a series circuit, and the series circuit is connected between the positive voltage power line 54 and the ground power line 55. 1
PMOS transistors QP3 forming the number of inverters
2 and an input signal IN are applied to the gates of the NMOS transistor QN32. PMOS transistor Q
The internal clock signal XLCK is applied to the gate of P31 by NM.
Internal clock signal LCK is applied to the gate of OS transistor QN31. Also, two PMOS
A series circuit is formed by the transistors QP33 and QP34 and the two NMOS transistors QN34 and QN33, and the series circuit is connected between the power supplies VDD and VSS. The connection point between the PMOS transistor QP34 and the NMOS transistor QN34 is supplied with the output of an inverter composed of the PMOS transistor QP32 and the NMOS transistor QN32. The gate of the PMOS transistor QP33 has an internal clock signal LCK.
However, the internal clock signal XLCK is applied to the gate of the NMOS transistor QN33. Furthermore, PM
OS transistor QP35 and NMOS transistor Q
N35 forms a series circuit, and the series circuit is connected between the positive voltage power supply line 54 and the ground power supply line 55. 2
The two PMOS transistors QP34 and QP35 and the two NMOS transistors QN34 and QN35 are connected to each other so as to form one flip-flop. The connection point between the PMOS transistor QP35 and the NMOS transistor QN35 supplies the output signal OUT of the latch cell 51.

The internal clock generation circuit 53 has five PMs.
OS transistors QP41, QP42, QP43, QP
44, QP45 and five NMOS transistors QN4
1, QN42, QN43, QN44, and QN45, which receive an external clock signal CK and complementary standby signals SBY and XSBY. Among them, two PMOS transistors QP
41, QP42 and two NMOS transistors QN4
2 and QN41 form a series circuit, which is connected between the positive voltage power supply line 54 and the ground power supply line 55. The PMOS transistor QP42 and the NMOS transistor QN42 constitute a first inverter for supplying the internal clock signal XLCK. The external clock signal C
K is given. The standby signal XSBY is supplied to the gate of the PMOS transistor QP41, and the standby signal SBY is supplied to the gate of the NMOS transistor QN41. Also, two PMOS transistors QP
43, QP44 and two NMOS transistors QN4
4, QN43, and a series circuit is connected between the positive voltage power supply line 54 and the ground power supply line 55. The PMOS transistor QP44 and the NMOS transistor QN44 constitute a second inverter for supplying the internal clock signal LCK, and each gate of the two transistors has an internal clock signal supplied from the first inverter. XLCK is provided. P
The standby signal XSBY is supplied to the gate of the MOS transistor QP43, and the standby signal SBY is supplied to the gate of the NMOS transistor QN43. Further, the power supply VDD and the internal clock signal X are fixed so that the voltage of the internal clock signal XLCK is fixed to the voltage of the power supply VDD when the semiconductor integrated circuit having the latch circuit of FIG.
A PMOS transistor QP45 between the LCK signal line
Is connected. An NMOS transistor QN45 is connected between the signal line of the internal clock signal LCK and the power supply VSS so that the voltage of the internal clock signal LCK is fixed to the voltage of the power supply VSS when the semiconductor integrated circuit is on standby. The standby signal SBY is supplied to the gate of the PMOS transistor QP45 by the NMOS transistor QN4.
The standby signal XSBY is supplied to each of the gates 5.

In FIG. 17, P in the latch cell 51
MOS transistor QP34 and NMOS transistor QN34, and PMOS transistor QP36 and NMOS transistor QN36 forming voltage control circuit 52
And the PMOS transistor QP45 and the NMOS transistor QN45 in the internal clock generation circuit 53,
Each of the transistors has a high threshold voltage. The other MOS transistors except these have a low threshold voltage.

During the operation of the latch circuit shown in FIG. 17, the first activation signal ACTP is set to "L" level and the second activation signal is set to "L" level so that both the PMOS transistor QP36 and the NMOS transistor QN36 forming the voltage control circuit 52 are turned on. Activation signal ACTN is set to "H" level. Therefore, the positive voltage power supply line 54 is connected to the power supply VDD.
The ground power supply lines 55 are connected to the power supply VSS. During the operation of the latch circuit, two PMOS transistors QP
41, QP43 and two NMOS transistors QN4
1 and QN43 are turned on, and the standby signal XSBY is set to “L” so that both the PMOS transistor QP45 and the NMOS transistor QN45 are turned off.
And the standby signal SBY is set to the “H” level. Therefore, complementary internal clock signals LCK and XLCK synchronized with the external clock signal CK are:
It is supplied to the latch cell 51. At this time, two PMOS
Since the threshold voltages of the transistors QP42 and QP44 and the two NMOS transistors QN42 and QN44 are low, the internal clock signals LCK and XLCK quickly follow the external clock signal CK. Latch cell 51
Is synchronized with the rise of the internal clock signal LCK,
Also, according to the logic level of the input signal IN, the output signal OU
Update the logic level of T. At this time, the four PMOS transistors QP31, QP32, QP33, QP35
And four NMOS transistors QN31, QN32,
Since the threshold voltages of QN33 and QN35 are low, the delay from the rising transition of internal clock signal LCK to the transition of output signal OUT is very small. PMOS transistors QP3 each having a high threshold voltage
4 and the NMOS transistor QN34 output signal OUT
It does not hinder the fast determination of. Then, even if the internal clock signal LCK goes low, the two PMOs
A flip-flop constituted by S transistors QP34 and QP35 and two NMOS transistors QN34 and QN35 works so as to hold the logic level of the output signal OUT.

During standby, the first and second activation signals A
CTP and ACTN intermittently go to “H” level,
As a result of being set to the “L” level, both the positive voltage power supply line 54 and the ground power supply line 55 intermittently enter a floating state. On the other hand, when the latch circuit is on standby, two PMOS transistors QP
41, QP43 and two NMOS transistors QN4
1 and QN43 are turned off, and the standby signal XSBY is set to “H” so that both the PMOS transistor QP45 and the NMOS transistor QN45 are turned on.
And the standby signal SBY is set to the “L” level. Therefore, internal clock signal XLC
The voltage of K is equal to the voltage of the power supply VDD and the internal clock signal LC.
The voltage of K is fixed to the voltage of the power supply VSS. As a result, the PMOS transistor Q in the latch cell 51
The P31 and the NMOS transistor QN31 maintain the OFF state, and the PMOS transistor QP33 and the NMOS transistor QN33 maintain the ON state, respectively. Here, assuming that the output signal OUT is to maintain the “H” level, the states of the four transistors QP34, QN34, QP35, and QN35 forming the flip-flop are off, on, on, and off, respectively. . In other words, the off-leak current during standby must be taken into account in the four PMOS transistors QP31 and QP3.
4, QP41, QP43 and four NMOS transistors QN31, QN35, QN41, QN43.

The PMO constituting the voltage control circuit 52 will now be described.
S transistor QP36 and NMOS transistor QN
In the OFF period of 36, one cell power supply line voltage VCP gradually decreases from the voltage of the power supply VDD, and the other cell power supply line voltage VCN gradually increases from the voltage of the power supply VSS.
As a result, the off-leak current of each transistor decreases. Description will be made by taking an NMOS transistor QN35 having a low threshold voltage as an example. Since the two NMOS transistors QN33 and QN34 are both on, the gate voltage of the NMOS transistor QN35 is equal to the voltage of the power supply VSS. Even if the cell power supply line voltage VCN fluctuates, the gate voltage of the NMOS transistor QN35 does not fluctuate. On the other hand, NMOS
The source voltage of the transistor QN35, that is, the cell power supply line voltage VCN becomes higher than the voltage of the power supply VSS. As a result, the gate-source voltage of the NMOS transistor QN35 becomes negative, and the drain-source voltage of the NMOS transistor QN35 decreases. Therefore, the NMOS transistor QN
The off-leak current of 35 decreases. Other three NMOS
The same applies to the transistors QN31, QN41, and QN43, in which the gate-source voltage becomes negative due to the floating of the cell power supply line voltage VCN, and the off-leakage current decreases. The PMOS transistor QP34 is a transistor having a high threshold voltage to reduce off-leak current.

If the PMOS transistor QP36 and the NMOS transistor QN36 are kept off during standby, the logic level of the output signal OUT becomes unstable. Therefore, the first and second activation signals ACTP and ACTN are applied similarly to the case of FIG. 16 so as to turn on both the transistors QP36 and QN36 intermittently.

As described above, according to the example of FIG. 17, the off-leakage current of the transistor constituting the flip-flop of the latch circuit can be reduced by devising the circuit configuration, and a high-speed and low-power-consumption latch circuit can be realized.

The example of the SRAM memory cell and the example of the latch circuit have been described. These flip-flop type data holding circuits can employ a stack configuration of a plurality of stages. For example, if the off-leak current discharged from the upper data holding circuit is used as the power supply current by the lower data holding circuit, the effect of reducing the power consumption during standby is further increased.

[0057]

As described above, according to the present invention, at least one of the two power supply lines of the flip-flop constituting the data holding circuit is intermittently brought into a floating state during standby. Therefore, the off-leak current of the transistor can be reduced while preventing the retained data from disappearing. That is, in a data holding circuit such as a semiconductor memory device, power consumption during standby is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a memory cell array in FIG. 1 and an internal configuration of each of voltage control circuits.

3 is a diagram showing a change over time of a cell power supply line voltage when a transistor constituting a voltage control circuit in FIG. 2 is kept off;

FIG. 4 is a timing chart showing an operation example of the semiconductor memory device of FIG. 1 during standby;

FIG. 5 is a timing chart showing another operation example of the semiconductor memory device of FIG. 1 during standby;

FIG. 6 is a timing chart showing an operation example at the time of reading of the semiconductor memory device of FIG. 1;

FIG. 7 is a timing chart showing an operation example at the time of writing of the semiconductor memory device of FIG. 1;

FIG. 8 is a block diagram showing an example of an internal configuration of an activation circuit in FIG. 1;

FIG. 9 is a block diagram showing another example of the internal configuration of the activation circuit in FIG. 1;

FIG. 10 is a circuit diagram showing an internal configuration of a level detection circuit in FIG. 9;

FIG. 11 is a timing chart showing an operation of the level detection circuit of FIG. 10;

FIG. 12 is a block diagram showing still another example of the internal configuration of the activation circuit in FIG. 1;

FIG. 13 is a block diagram showing another example of the internal configuration of the activation circuit in FIG. 1;

FIG. 14 is a block diagram showing a configuration of a semiconductor memory device according to another embodiment of the present invention.

FIG. 15 is a block diagram showing an example of an internal configuration of an activation circuit in FIG. 14;

FIG. 16 is a circuit diagram showing a modification of the voltage control circuit in FIG. 2;

FIG. 17 is a circuit diagram showing a configuration of a latch circuit according to still another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 memory cell array 14 voltage control circuit 15 activation circuit (control means) 21 memory cell 22 precharge circuit 23 positive voltage power supply line 24 ground power supply line 31, 31a, 31b, 31c oscillation circuit 32a waveform shaping and switching circuit 33 NOR circuit 35 , 35a, 35b Level detection circuit 41 Reference voltage generation circuit 42 Comparison circuit 51 Latch cell 52 Voltage control circuit 53 Internal clock generation circuit 54 Positive voltage power supply line 55 Ground power supply line 115 Activation circuit (control means) 121 to 124 Block 131 Oscillation circuit 133a to 133d NOR circuit 141 Decoder 142a to 142d AND circuit ACT activation signal ACT0 to ACT3 activation signal ACTN, ACTP activation signal BA block address BL, XBL bit line CA column address CK external clock Lock signal CLK Clock signal CS Chip select signal C1, C2 Capacitor DET detection signal I1, I2, I3 Off-leak current of transistor IN Input signal LCK, XLCK Internal clock signal MOD Mode switching signal N1, N2 Storage node OUT Output signal PRE precharge signal QN1 to QN4 NMOS transistor QN5 NMOS transistor (switch means) QN21 to QN26 NMOS transistor QN31 to QN35 NMOS transistor QN36 NMOS transistor (switch means) QN41 to QN45 NMOS transistor QP1 to QP4 PMOS transistor QP5 PMOS transistor (switch means) QP21 to QP25 PMOS Transistors QP31 to QP35 PMOS transistors QP 36 PMOS transistor (switch means) QP41 to QP45 PMOS transistor RA Row address SBY, XSBY Standby signal VCN, VCP Cell power supply line voltage VDD, VSS power supply Vref1, Vref2 Reference voltage WL Word line

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-246089 (JP, A) JP-A-58-62889 (JP, A) JP-A-5-6667 (JP, A) JP-A-4- 192186 (JP, A) JP-A-63-49812 (JP, A) JP-A-60-170095 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/41-11 / 4197

Claims (4)

(57) [Claims] 1. A flip-flop comprising a plurality of transistors.
Flip-flop and the storage node and bit of the flip-flop.
Switching system according to the word line voltage
With memory cell having a transistor controlled
In the conductor storage device, at least one of the two power supply lines of the flip-flop
Switch means interposed between one power supply line and the power supply
The switching means is intermittent when the semiconductor memory device is on standby.
Control for controlling the switch means to be opened
Means, wherein the control means is configured to control the scan mode when the semiconductor memory device is on standby.
The one signal is used as a signal for intermittently opening the switch means.
Signal indicating that the voltage of the power supply line has reached the predetermined reference voltage.
Level detection circuit for supplying a signal to the switch means
The level detection circuit intermittently intermittently controls the voltage of the one power supply line and the predetermined reference voltage.
A comparison circuit for performing a comparison, and intermittently supplying the predetermined reference voltage to the comparison circuit
And a reference voltage generation circuit, which is interposed between a first power supply and a first node, and is controlled to close during a first period and open during a second period. A first switch interposed between the first node and the second node, and controlled to open during the first period and close during the second period; A third switch interposed between the second node and a second power supply and controlled to close during the first period and open during the second period; A first capacitor interposed between the second node and the second power supply; and a second capacitor interposed between the second node and the second power supply. The voltage of the first and second nodes when the second switch is closed during the period of 2 A semiconductor memory which supplies the reference voltage as a constant reference voltage to the comparison circuit, and wherein the comparison circuit compares the voltage of the one power supply line with the supplied reference voltage during the second period. apparatus. 2. A memory cell comprising: a flip-flop composed of a plurality of transistors; and a transistor interposed between a storage node of the flip-flop and a bit line and controlled to open and close according to a voltage of a word line. A switching device interposed between at least one of the two power lines of the flip-flop and a power supply, wherein the switch device is intermittent when the semiconductor storage device is on standby. Control means for controlling the switch means so as to open the data in the storage node of the flip-flop not only within a non-extinction range of the data but also within a predetermined time. To generate a first clock signal having a frequency determined on condition that the clock signal is in a readable range. And a second clock signal having a frequency determined on condition that the voltage representing the data at the storage node of the flip-flop cannot be read within the fixed time but is within the indelible range of the data. A second oscillation circuit for generating, and a signal for intermittently opening the switch means when the semiconductor memory device is in a standby state, wherein the signal is one of the first and second clock signals according to a mode switching signal. And a circuit for supplying the data to the switch means. 3. A memory cell comprising: a flip-flop including a plurality of transistors; and a transistor interposed between a storage node of the flip-flop and a bit line and controlled to open / close according to a word line voltage. A switching device interposed between at least one of the two power lines of the flip-flop and a power supply, wherein the switch device is intermittent when the semiconductor storage device is on standby. Control means for controlling the switch means so as to open the switch means. The control means operates in response to a mode switching signal, and intermittently opens the switch means when the semiconductor memory device is on standby. As a signal, the voltage representing the data at the storage node of the flip-flop is not only in A first level detection circuit for supplying to the switch means a signal indicating that the voltage of the one power supply line has reached a first reference voltage defined on condition that the voltage is within a readable range. A memory node of the flip-flop which operates when the first level detection circuit is inactive in response to the mode switching signal and intermittently opens the switch means when the semiconductor memory device is on standby. That the voltage of the one power supply line has reached a second reference voltage that is determined on condition that the voltage representing the data cannot be read within the fixed time but is within the non-destructive range of the data. And a second level detection circuit for supplying a signal to the switch means. 4. The semiconductor memory device according to claim 3 , wherein said control means switches said mode switching so that said first and second level detection circuits operate intermittently at different periods according to said mode switching signal. A semiconductor memory device further comprising an oscillation circuit for supplying a clock signal having a frequency changed in accordance with a signal to the first and second level detection circuits.