JP3308047B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3308047B2 JP3308047B2 JP15400193A JP15400193A JP3308047B2 JP 3308047 B2 JP3308047 B2 JP 3308047B2 JP 15400193 A JP15400193 A JP 15400193A JP 15400193 A JP15400193 A JP 15400193A JP 3308047 B2 JP3308047 B2 JP 3308047B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- main surface
- semiconductor
- chip
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はパッケージの小型化技
術、特に、高機能化及び高集積化を図るために用いて効
果のある技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for reducing the size of a package, and more particularly to a technology effective for achieving high functionality and high integration.
【０００２】[0002]
【従来の技術】近年、半導体装置の高機能化及び高集積
化に伴って急速に多ピン化が進み、これに比例して電源
ピン（またはリード）も増加の傾向にある。通常、１つ
のＬＳＩ（大規模集積回路）は、数本の電源ピンとグラ
ンド（ＧＮＤ）ピンを備えている。2. Description of the Related Art In recent years, the number of pins has rapidly increased with the advancement of functions and integration of semiconductor devices, and the number of power supply pins (or leads) tends to increase in proportion thereto. Usually, one LSI (large-scale integrated circuit) has several power supply pins and ground (GND) pins.
【０００３】[0003]
【発明が解決しようとする課題】本発明者の検討によれ
ば、高機能化及び高集積化に伴ってパッケージサイズの
拡大、アナログ／デジタル回路の混在等により複雑化し
た半導体装置は、多ピン化が避けられず、基板上に実装
したときのパターン引き回し設計に多大の時間と労力を
要するという問題がある。また、配線の引き回しによ
り、電位差を大きくするという問題もある。According to the study of the present inventor, a semiconductor device which has become complicated due to an increase in package size and a mixture of analog / digital circuits due to high functionality and high integration has a large number of pins. However, there is a problem that a great deal of time and labor is required for the pattern routing design when mounted on a substrate. In addition, there is also a problem that a potential difference is increased by wiring.
【０００４】そこで、本発明の目的は、ピン数またはリ
ード数の低減を図りパッケージサイズの小型化を可能に
する技術を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique for reducing the number of pins or leads and reducing the size of a package.
【０００５】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。[0005] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００６】[0006]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【０００７】すなわち、本発明の半導体装置は、複数の
パッドを主面に有する四角形の半導体チップと、前記半
導体チップを搭載する前記半導体チップよりも大きな金
属板と、前記半導体チップから離間して先端が前記半導
体チップを囲むように配置される複数のリードと、前記
半導体チップ主面の複数のパッドと前記複数のリードと
を接続するボンディングワイヤとを有する半導体装置で
あって、前記半導体チップは前記金属板の一主面に搭載
され、前記金属板の前記半導体チップ搭載面と同一主面
であって前記複数のリードと前記半導体チップとの間の
個所に前記半導体チップから離間して前記半導体チップ
を囲むように枠状のメタル層が設けられ、前記枠状のメ
タル層と前記金属板の一主面との間には絶縁層が設けら
れ、前記パッドと前記メタル層とはボンディングワイヤ
で接続されているものである。 また、本発明の他の半導
体装置は、複数のパッドを主面に有する四角形の半導体
チップと、前記半導体チップを搭載する前記半導体チッ
プよりも大きな金属板と、前記半導体チップから離間し
て先端が前記半導体チップを囲むように配置される複数
のリードと、前記半導体チップ主面の複数のパッドと前
記複数のリードとを接続するボンディングワイヤとを有
する半導体装置であって、前記半導体チップは前記金属
板の一主面に搭載され、前記金属板の前記半導体チップ
搭載面と同一主面であって前記複数のリードと前記半導
体チップとの間の個所に前記半導体チップから離間して
前記半導体チップの四つの辺それぞれに向かい合う長辺
を有する複数のメタル層が絶縁層を介して設けられ、前
記パッドと前記メタル層とはボンディングワイヤで接続
されているものである。 That is, the semiconductor device of the present invention comprises a plurality of
A quadrangular semiconductor chip having pads on its main surface;
Gold larger than the semiconductor chip on which the conductor chip is mounted
Metal plate and the semiconductor chip is separated from the semiconductor chip by the tip.
A plurality of leads arranged so as to surround the body chip;
A plurality of pads on the main surface of the semiconductor chip and the plurality of leads;
Semiconductor device having a bonding wire connecting
The semiconductor chip is mounted on one main surface of the metal plate
The same main surface as the semiconductor chip mounting surface of the metal plate
Between the plurality of leads and the semiconductor chip
The semiconductor chip separated from the semiconductor chip
A frame-shaped metal layer is provided so as to surround the frame-shaped metal layer.
An insulating layer is provided between the metal layer and one main surface of the metal plate.
And the pad and the metal layer are bonded to each other by a bonding wire.
Are connected by In addition, other semiconductor devices of the present invention
The body device is a square semiconductor with multiple pads on the main surface.
A chip and the semiconductor chip on which the semiconductor chip is mounted.
A metal plate larger than the
A plurality of tips arranged so as to surround the semiconductor chip
And a plurality of pads on the main surface of the semiconductor chip and
It has a bonding wire that connects to multiple leads.
Wherein the semiconductor chip comprises the metal
The semiconductor chip of the metal plate mounted on one main surface of the plate
The plurality of leads and the semi-conductor are the same main surface as the mounting surface.
At a point between the body chip and the semiconductor chip
Long side facing each of the four sides of the semiconductor chip
A plurality of metal layers having
The pad and the metal layer are connected by a bonding wire
Is what is being done.
【０００８】[0008]
【作用】上記した手段によれば、半導体チップの周辺に
共通電源パターンとなるメタル層を設け、このメタル層
に半導体チップ上の電源パッド（電圧が共通するもの）
の各々が接続される。これにより、半導体チップ上の電
源パッドの各々に対応してリードを設ける必要がなくな
るので、ピン（またはリード）数の低減が可能になり、
基板実装時の基板上配線（パターン）の設計も容易にな
るため、パッケージの小型化が可能になる。According to the above-described means, a metal layer serving as a common power supply pattern is provided around the semiconductor chip, and a power supply pad (a voltage having a common voltage) on the semiconductor chip is provided on the metal layer.
Are connected. This eliminates the need to provide leads corresponding to each of the power supply pads on the semiconductor chip, thereby reducing the number of pins (or leads).
Since the design of the wiring (pattern) on the substrate at the time of mounting the substrate is also facilitated, the size of the package can be reduced.
【０００９】[0009]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１０】（実施例１）図１は本発明による半導体装
置の一実施例を示す平面図である。また、図２は図１の
実施例の断面図である。(Embodiment 1) FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention. FIG. 2 is a sectional view of the embodiment of FIG.
【００１１】タブ１上の中央部には、上面の周囲にバン
プ２ａが設けられた半導体チップ２が実装（搭載）さ
れ、この半導体チップ２を取り囲むようにしてタブ１上
には枠形のメタル層３が絶縁層４を介して形成されてい
る。メタル層３に隣接させて、タブ１の周辺には放射状
に複数のリード５が水平に配設されている。このリード
５に対し、ボンディングワイヤ６によってメタル層３及
び半導体チップ２上のパッドとの接続が行われている。A semiconductor chip 2 provided with bumps 2a around its upper surface is mounted (mounted) at a central portion on the tab 1, and a frame-shaped metal is placed on the tab 1 so as to surround the semiconductor chip 2. The layer 3 is formed via the insulating layer 4. A plurality of leads 5 are horizontally arranged radially around the tab 1 adjacent to the metal layer 3. The leads 5 are connected to the metal layer 3 and the pads on the semiconductor chip 2 by bonding wires 6.
【００１２】また、タブ１は金属製であるため、これを
共通のＧＮＤ端子として用いることができる。すなわ
ち、半導体チップ２上のグランド用パッド２ｃ及びリー
ド５をメタル層３の両側より露出するタブ１の表面にワ
イヤボンディングで接続することにより、グランド用の
リードは１本で済むことになる。Further, since the tab 1 is made of metal, it can be used as a common GND terminal. That is, by connecting the ground pad 2c and the lead 5 on the semiconductor chip 2 to the surface of the tab 1 exposed from both sides of the metal layer 3 by wire bonding, only one ground lead is required.
【００１３】このように、半導体チップ２の周囲のスペ
ースを生かし、このスペースにメタル層３を設けること
で共通電源パターンを作成することができ、この共通電
源パターンに半導体チップ２上の電源用パッド２ｂの各
々を接続すれば、電源用のリード５は１本で済むことに
なり、リード数を低減できることによってパッケージの
小型化を図ることができる。そして、メタル層３は幅広
に形成できる結果、電位差を最小限に抑えることができ
る。As described above, by utilizing the space around the semiconductor chip 2 and providing the metal layer 3 in this space, a common power supply pattern can be created. If each of 2b is connected, only one power supply lead 5 is required, and the number of leads can be reduced, whereby the size of the package can be reduced. As a result, the metal layer 3 can be formed wide, so that the potential difference can be minimized.
【００１４】同様に、タブ１をグランド用パターンとし
て用いることでグランド用リードを１本で済ませられ、
これによってリード数を低減できる結果、パッケージの
小型化を図ることができる。Similarly, by using the tab 1 as a ground pattern, only one ground lead is required.
As a result, the number of leads can be reduced, and the size of the package can be reduced.
【００１５】（実施例２） 図３は本発明の第２実施例を示す断面図である。なお、
図３においては、図２と同一であるものには同一の符号
を付し、以下においては重複する説明を省略する。(Embodiment 2) FIG. 3 is a sectional view showing a second embodiment of the present invention. In addition,
In FIG. 3, the same components as those in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted below.
【００１６】本実施例は、前記実施例におけるタブ１と
ほぼ同サイズの絶縁板７上に、半導体チップ２よりやや
大きめのサイズのタブ８を接着等により搭載し、タブ８
の周囲の絶縁板７上に共通電源用のメタル層３を直接に
設けるようにしたところに特徴がある。なお、ボンディ
ングワイヤ６の配線などについては、前記実施例と同一
である。In this embodiment, a tab 8 slightly larger than the semiconductor chip 2 is mounted on an insulating plate 7 having substantially the same size as the tab 1 in the above embodiment by bonding or the like.
The feature is that the metal layer 3 for the common power supply is directly provided on the insulating plate 7 around the above. Note that the wiring of the bonding wires 6 and the like are the same as those in the above embodiment.
【００１７】本実施例は、タブが比較的小さく、半導体
チップ２の周囲に有効なスペースが得られない場合に有
効であり、タブサイズに制限されることなくパッケージ
サイズの小型化を図ることができる。This embodiment is effective when the tab is relatively small and an effective space around the semiconductor chip 2 cannot be obtained, and it is possible to reduce the package size without being limited by the tab size. it can.
【００１８】（実施例３）図４は本発明の第３実施例を
示す平面図である。なお、図４においては、リード、ボ
ンディングワイヤなどについては図示を省略している。(Embodiment 3) FIG. 4 is a plan view showing a third embodiment of the present invention. In FIG. 4, illustration of leads, bonding wires, and the like is omitted.
【００１９】前記各実施例がメタル層３を共通電源用に
用いていたため、メタル層３を枠形に形成し、電気的に
は４辺が接続された状態であったのに対し、本実施例は
複数（ここでは４つ）に分割し、各々を異なる目的に使
用するようにしたものである。例えば、異なる電圧や極
性の複数種の電源に用いる事などが可能になる。In each of the above embodiments, the metal layer 3 was used for a common power supply. Therefore, the metal layer 3 was formed in a frame shape, and the four sides were electrically connected. The example is divided into a plurality (here four), each of which is used for a different purpose. For example, it can be used for a plurality of types of power supplies having different voltages and polarities.
【００２０】なお、ここでは４辺にメタル層３を形成す
るものとしたが、少なくとも１辺に設ければよい。ま
た、図５に示すように各辺を更に分割し、用途を増やす
ことも可能である。Here, the metal layers 3 are formed on four sides, but may be provided on at least one side. Further, as shown in FIG. 5, each side can be further divided to increase the use.
【００２１】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。As mentioned above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.
【００２２】[0022]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described.
It is as follows.
【００２３】すなわち、本発明の半導体装置は、複数の
パッドを主面に有する四角形の半導体チップと、前記半
導体チップを搭載する前記半導体チップよりも大きな金
属板と、前記半導体チップから離間して先端が前記半導
体チップを囲むように配置される複数のリードと、前記
半導体チップ主面の複数のパッドと前記複数のリードと
を接続するボンディングワイヤとを有する半導体装置で
あって、前記半導体チップは前記金属板の一主面に搭載
され、前記金属板の前記半導体チップ搭載面と同一主面
であって前記複数のリードと前記半導体チップとの間の
個所に前記半導体チップから離間して前記半導体チップ
を囲むように枠状のメタル層が設けられ、前記枠状のメ
タル層と前記金属板の一主面との間には絶縁層が設けら
れ、前記パッドと前記メタル層とはボンディングワイヤ
で接続されているので、ピン（またはリード）数の低減
が可能になり、基板実装時の基板上配線(パターン)の設
計も容易になるため、パッケージの小型化が可能にな
る。That is, the semiconductor device of the present invention comprises a plurality of
A quadrangular semiconductor chip having pads on its main surface;
Gold larger than the semiconductor chip on which the conductor chip is mounted
Metal plate and the semiconductor chip is separated from the semiconductor chip by the tip.
A plurality of leads arranged so as to surround the body chip;
A plurality of pads on the main surface of the semiconductor chip and the plurality of leads;
Semiconductor device having a bonding wire connecting
The semiconductor chip is mounted on one main surface of the metal plate
The same main surface as the semiconductor chip mounting surface of the metal plate
Between the plurality of leads and the semiconductor chip
The semiconductor chip separated from the semiconductor chip
A frame-shaped metal layer is provided so as to surround the frame-shaped metal layer.
An insulating layer is provided between the metal layer and one main surface of the metal plate.
And the pad and the metal layer are bonded to each other by a bonding wire.
, The number of pins (or leads) can be reduced, and the wiring (pattern) on the board can be easily designed when mounted on the board, so that the package can be downsized.
【図１】本発明による半導体装置の一実施例を示す平面
図である。FIG. 1 is a plan view showing one embodiment of a semiconductor device according to the present invention.
【図２】図１の実施例の断面図である。FIG. 2 is a sectional view of the embodiment of FIG.
【図３】本発明の第２実施例を示す断面図である。FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】本発明の第３実施例を示す平面図である。FIG. 4 is a plan view showing a third embodiment of the present invention.
【図５】図４の実施例の変形例を示す平面図である。FIG. 5 is a plan view showing a modification of the embodiment of FIG.
１ タブ ２ 半導体チップ ２ａ パッド ２ｂ 電源用パッド ２ｃ グランド用パッド ３ メタル層 ４ 絶縁層 ５ リード ６ ボンディングワイヤ ７ 絶縁板 ８ タブ Reference Signs 1 tab 2 semiconductor chip 2a pad 2b power supply pad 2c ground pad 3 metal layer 4 insulating layer 5 lead 6 bonding wire 7 insulating plate 8 tab
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高崎 一 秋田県南秋田郡天王町天王字長沼64 ア キタ電子株式会社内 (56)参考文献 特開 平３−42846（ＪＰ，Ａ) 特開 昭63−52457（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/822 H01L 21/60 301 H01L 27/04 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazu Takasaki 64 Nagano Numa, Tenno-cho, Tenno-cho, Minami-Akita-gun Akita Electronics Co., Ltd. (56) References JP-A-3-42846 (JP, A) JP-A 63 -52457 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/822 H01L 21/60 301 H01L 27/04
Claims (6)
導体チップと、前記半導体チップを搭載する前記半導体
チップよりも大きな金属板と、前記半導体チップから離
間して先端が前記半導体チップを囲むように配置される
複数のリードと、前記半導体チップ主面の複数のパッド
と前記複数のリードとを接続するボンディングワイヤと
を有する半導体装置であって、前記半導体チップは前記
金属板の一主面に搭載され、前記金属板の前記半導体チ
ップ搭載面と同一主面であって前記複数のリードと前記
半導体チップとの間の個所に前記半導体チップから離間
して前記半導体チップを囲むように枠状のメタル層が設
けられ、前記枠状のメタル層と前記金属板の一主面との
間には絶縁層が設けられ、前記パッドと前記メタル層と
はボンディングワイヤで接続されていることを特徴とす
る半導体装置。1. A quadrangular half having a plurality of pads on its main surface.
A conductive chip and the semiconductor on which the semiconductor chip is mounted
A metal plate larger than the chip and separated from the semiconductor chip.
The tip is arranged so as to surround the semiconductor chip.
A plurality of leads and a plurality of pads on the main surface of the semiconductor chip
And a bonding wire connecting the plurality of leads.
Wherein the semiconductor chip is
The semiconductor chip of the metal plate is mounted on one main surface of the metal plate.
The plurality of leads and the same main surface
Separated from the semiconductor chip at a location between the semiconductor chip
Then, a frame-shaped metal layer is provided so as to surround the semiconductor chip.
Between the frame-shaped metal layer and one main surface of the metal plate.
An insulating layer is provided between the pad and the metal layer.
Is a semiconductor device characterized by being connected by a bonding wire .
導体チップと、前記半導体チップを搭載する前記半導体
チップよりも大きな金属板と、前記半導体チップから離
間して先端が前記半導体チップを囲むように配置される
複数のリードと、前記半導体チップ主面の複数のパッド
と前記複数のリードとを接続するボンディングワイヤと
を有する半導体装置であって、前記半導体チップは前記
金属板の一主面に搭載され、前記金属板の前記半導体チ
ップ搭載面と同一主面であって前記複数のリードと前記
半導体チップとの間の個所に前記半導体チップから離間
して前記半導体チップの四つの辺それぞれに向かい合う
長辺を有する複数のメタル層が絶縁層を介して設けら
れ、前記パッドと前記メタル層とはボンディングワイヤ
で接続されていることを特徴とする半導体装置。2. A square half having a plurality of pads on its main surface.
A conductive chip and the semiconductor on which the semiconductor chip is mounted
A metal plate larger than the chip and separated from the semiconductor chip.
The tip is arranged so as to surround the semiconductor chip.
A plurality of leads and a plurality of pads on the main surface of the semiconductor chip
And a bonding wire connecting the plurality of leads.
Wherein the semiconductor chip is
The semiconductor chip of the metal plate is mounted on one main surface of the metal plate.
The plurality of leads and the same main surface
Separated from the semiconductor chip at a location between the semiconductor chip
To face each of the four sides of the semiconductor chip
A plurality of metal layers having long sides are provided via an insulating layer.
And the pad and the metal layer are bonded to each other by a bonding wire.
A semiconductor device, characterized by being connected by:
位を供給するパッドとボンディングワイヤで接続されて
いることを特徴とする請求項１又は請求項２記載の半導
体装置。3. The semiconductor device according to claim 1, wherein said metal layer is provided to a semiconductor chip.
Connected to the pad that supplies the position with a bonding wire
The semiconductor device according to claim 1 , wherein:
られることを特徴とする請求項１又は請求項２記載の半
導体装置。 4. The metal layer is used for a common power supply.
The semiconductor device according to claim 1 , wherein the semiconductor device is provided.
用いられることを特徴とする請求項２記載の半導体装
置。5. A before Symbol metal layer, as for a plurality of types of power
3. The semiconductor device according to claim 2 , wherein the semiconductor device is used.
ることを特徴とする 請求項１乃至請求項５のいずれか一
つに記載の半導体装置。 6. The metal plate is used for grounding.
6. The method according to claim 1, wherein:
6. The semiconductor device according to any one of the preceding claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15400193A JP3308047B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15400193A JP3308047B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0730067A JPH0730067A (en) | 1995-01-31 |
| JP3308047B2 true JP3308047B2 (en) | 2002-07-29 |
Family
ID=15574750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15400193A Expired - Lifetime JP3308047B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3308047B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0177744B1 (en) * | 1995-08-14 | 1999-03-20 | 김광호 | Semiconductor device with improved electrical characteristics |
| JP4545537B2 (en) | 2004-09-17 | 2010-09-15 | 富士通セミコンダクター株式会社 | Semiconductor device and semiconductor device unit |
| CN110364477B (en) * | 2018-03-26 | 2021-11-23 | 中芯国际集成电路制造(上海)有限公司 | Chip structure and forming method thereof |
-
1993
- 1993-06-25 JP JP15400193A patent/JP3308047B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0730067A (en) | 1995-01-31 |
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