JP3306928B2 - Digital image signal receiving / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal receiving / reproducing apparatus applied to record / reproduce a digital image signal by, for example, a digital VTR, and more particularly to interpolation of pixel data having an error.

[0002]

2. Description of the Related Art When a digital video signal is transmitted using a recording medium such as a magnetic tape, an error occurs in a recording / reproducing process. Usually, an error correction code is used as a measure against errors. However, when an error occurs that exceeds the correction capability of the error correction code,
Interpolation processing is performed so that errors are not noticeable in the reproduced image.

The interpolation process utilizes a spatial correlation of image information, and calculates an average value of two correct pixels near an error pixel and replaces the error pixel value with the average value. It is. In order to generate an interpolation value that is as close as possible to the true value of the error pixel, adaptive interpolation using a selected one of the plurality of interpolation values as the interpolation value is preferable. That is, an average value of two pixel data located in different directions (horizontal direction, vertical direction, diagonal direction, etc.) is generated for the interpolation target pixel which is an error. Then, the absolute value of the difference value between the two pixel data for generating each interpolation value is calculated, and the absolute value of the absolute difference value that is smallest is detected.
The interpolation value corresponding to this is selected as the optimal one.

[0004]

In order to select an optimum value among a plurality of interpolated values, a conventional adaptive interpolator determines the magnitude of the absolute difference value between two pixel data, that is, the pixel to be interpolated. Using a one-dimensional level gradient centered on
The case where the inclination is minimum is determined to be optimal. However, there is a problem that sufficient accuracy cannot be expected even if the determination is made based on the one-dimensional level gradient in order to detect the optimum interpolation, and the accuracy of the selected interpolation value is reduced. Further, there is a problem that hardware such as a subtraction circuit and a comparison circuit is required to select an optimal interpolation value.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital image signal receiving / reproducing apparatus whose accuracy can be higher than that of a conventional apparatus and whose hardware is simple.

Another object of the present invention is to provide a digital image signal receiving / reproducing apparatus capable of finding the current optimum interpolation by learning past received / reproduced data.

[0007]

According to the first aspect of the present invention, there is provided a digital image signal which has been received or reproduced, and has a pixel having an error.
Reception of digital image signal with data interpolated
/ Interpolation target image received or reproduced by the reproduction device
Multiple received or reproduced pixel data
Data for compression encoding and generating a compression encoded output.
The encoding means and the received or reproduced pixel to be interpolated
Multiple adjacent received or reproduced pixel data
Using different interpolation formulas
The error between the multiple interpolated values obtained and the true value of the interpolation target pixel is minimized.
The interpolation formula to be small is determined, and the determined interpolation calculation formula and
Generates the corresponding optimal interpolation data and outputs the compression encoded output.
The frequency of appearance of the optimal interpolation data for each
Form a frequency distribution table integrated by
The optimal interpolation data for each of the compression encoded outputs
The optimal interpolation data with the maximum appearance frequency of
The output optimal interpolation data is
Map to create a mapping table stored for
Means for generating the encoding table and the delayed compression-encoded output
The interpolation target image supplied to the mapping table and delayed
Output from mapping table when element is error
Generated with the optimal interpolation data
The generated optimal interpolation value is substituted for the pixel to be interpolated in error.
Instead, the present invention is a digital image signal receiving / reproducing apparatus characterized by comprising means for selectively outputting .

According to a second aspect of the present invention , error pixel data is interpolated in a received or reproduced digital image signal.
Digital image signal receiving / reproducing apparatus
Close to the received or reproduced pixel to be interpolated.
Compression encoding of multiple received or reproduced pixel data
And an encoding circuit for generating a compression encoded output, DOO
Delayed compression code prepared by training
Output is supplied, and the compression encoded output and the optimal interpolation data are
The first mapping table storing the first mapping table
1 mapping table storage circuit and the received or reproduced
Compressed code created using delayed pixel data
The encoded output is supplied, and the compressed encoded output and the optimal interpolation data
A second mapping table indicating the relationship with is stored
Second mapping table storage circuit and delayed interpolation
If the target pixel is in error, the first and second maps
Optimal complement output from the selected one of the ping tables
Generated by the interpolating equation corresponding to the interim data
Select the interpolation value instead of the interpolation target pixel which is in error
Output circuit and received or reproduced interpolation
Multiple received or reproduced signals in proximity to the target pixel
Using pixel data and multiple different interpolation formulas
Multiple interpolated values found and the true value of the interpolated pixel
And the interpolation formula that minimizes the error with
Generates the optimal interpolation data corresponding to the interpolation formula and
Frequency of optimal interpolated data for each output
There is formed a frequency distribution table which is integrated a plurality of frames, most for the frequency distribution table, each of the compression encoded output
A second optimal interpolation data in which the frequency of appearance of the optimal interpolation data has a maximum value is detected, and the detected optimal interpolation data is stored.
Mapping table for each compressed encoded output
From the second mapping table creation circuit
Become the first mapping table for training
The first mapping table creation circuit created by
Close to the interpolation target pixel in the digital image signal
Compression encoding of multiple adjacent pixel data and compression encoding
Form an interpolated pair in the prepared digital image signal
A plurality of pixel data close to the Elephant pixel use, each other
The numbers calculated using different interpolation formulas
To minimize the error between the interpolation value of
And determine the interpolation formula that corresponds to the determined interpolation formula.
Generates the appropriate interpolation data, and
Of the optimal interpolation data to be integrated
Form a frequency distribution table, and in the frequency distribution table,
Frequency of optimal interpolated data for each output
The optimal interpolation data with the maximum value is detected, and the maximum
The first mapping table in which the appropriate interpolation data is stored
Created for each compression encoded output
And a digital image signal receiving / reproducing apparatus.

[0009]

When a pixel to be interpolated is interpolated by a plurality of pixels adjacent thereto, an arithmetic expression for performing optimal interpolation or a pixel to be used is specified by a mapping table stored in a memory device. This mapping table determines the optimal interpolation for the received / reproduced data of k frames from the present to the past and is variable. By using the variable mapping table, errors can be interpolated with high accuracy in accordance with image data actually received / reproduced.

[0010]

An embodiment of the present invention will be described below. FIG. 1 illustrates this embodiment, namely, the digital VT.
1 shows a schematic configuration of R signal processing. A video signal is supplied from an input terminal denoted by reference numeral 1 and the A / D converter 2 outputs a video signal.
The sample is digitized, for example, to 8 bits. The output data of the A / D converter 2 is supplied to the blocking circuit 3. In this embodiment, the blocking circuit 3 divides the effective area of one frame into blocks each having a size of (4 × 4) pixels, (8 × 8) pixels, or the like.

The digital video signal scan-converted in the order of blocks from the blocking circuit 3 is supplied to the shuffling circuit 4. In the shuffling circuit 4, shuffling is performed, for example, in units of blocks. Shuffling shuffles the spatial position of a block. The output of the shuffling circuit 4 is supplied to the block encoding circuit 5. The block encoding circuit 5 compression-encodes pixel data for each block. ADRC, cosine transform (DCT) and the like can be adopted as block coding. The shuffling circuit 4 may be provided after the block encoding circuit 5.

In this embodiment, ADRC is used as block coding. In the block coding circuit 5, the dynamic range DR of each block and the minimum value MI
N is detected, and the video data from which the minimum value has been removed is re-quantized in the quantization step. 4-bit fixed-length AD
In the case of RC, the quantization step Δ is obtained by setting the dynamic range DR to 1/16. In the quantization step Δ, the video data from which the minimum value has been removed is divided, and the value obtained by rounding down the quotient to an integer is used as the quantized data. The dynamic range DR, the minimum value MIN, and the quantized data are output data of the block encoding circuit 5. A dynamic range DR and a minimum value MIN are generated as important words in each block.

The output data of the block encoding circuit 5 is supplied to a framing circuit 6. The framing circuit 6
A parity of an error correction code is generated, and recording data having a structure in which sync blocks are continuous is generated. As the error correction code, for example, a product code for performing error correction coding in each of a horizontal direction and a vertical direction of a matrix arrangement of data can be adopted. A sync block synchronization signal and an ID signal are added to the encoded data and parity. The recording data in which the sync blocks continue are supplied to the channel encoding circuit 7,
It undergoes channel coding processing to reduce the DC component.

The output data of the channel encoding circuit 7 is converted into a bit stream, and is further supplied to a rotary head H via a recording amplifier 8 so that the recording data is transferred to a magnetic tape T.
Recorded as diagonal tracks on top. Usually, a plurality of rotating heads are used, but only one head is shown for simplicity.

The reproduction data taken out of the magnetic tape T by the rotary head H is supplied to a channel decoding circuit 12 via a reproduction amplifier 11 and is subjected to channel coding decoding. The output data of the channel decoding circuit 12 is supplied to a frame decomposing circuit 13, where various kinds of data are separated from recording data and error correction is performed. The output data generated from the frame decomposition circuit 13 includes an error flag indicating the presence or absence of an error after error correction in addition to the reproduction data.

The output data of the frame decomposition circuit 13 is supplied to an important word correction circuit 14. The important word correction circuit 14
An important word indicating an error by the error flag (that is, the dynamic range DR for each block)
And the minimum value MIN). Output data of the important word correction circuit 14 is supplied to a block decoding circuit 15. The decoding circuit 15 performs ADRC decoding using an important word that is not erroneous, and decodes the ADRC using the corrected important word in the important word correcting circuit 14 for a block in which the important word is erroneous. Do. It is preferable that the important word correction circuit 14 has a function of estimating an important word when an error cannot be corrected.

In the block decoding circuit 15, for example, ADR
In the case of C decoding, when the number of bits of the quantization code is 4 bits, a decoded value Li of each pixel is generated. This decrypted value L
i is represented by the following equation. Li = [(DR / 2 ⁴ ) × xi + MIN + 0.5] = [Δ × xi + MIN + 0.5]

Here, xi is the value of the code signal, Δ is the quantization step, and [] is the Gaussian symbol. The block decoding circuit 15 has a configuration in which the operation in [] of the above equation is realized by, for example, a ROM and the minimum value MIN is added.

The decoded data of the block decoding circuit 15, that is, restored data corresponding to each pixel is supplied to a deshuffling circuit 16. This circuit 16 is complementary to the shuffling circuit 4 on the recording side, and performs processing for returning the spatial position of the block to the original position. Output data of the deshuffling circuit 16 is supplied to the block decomposition circuit 17. The order of the data is returned from the order of the blocks to the order of the raster scanning by the block decomposition circuit 17. Output data of the block decomposition circuit 17 is supplied to an error interpolation circuit 18. The error interpolation circuit 18 interpolates data having an error in pixel units with peripheral pixel data. Output data of the error interpolation circuit 18 is supplied to a D / A converter 19, and restored data of the order of raster scanning corresponding to each pixel is obtained at an output terminal 20.

The present invention is applied to the error interpolation circuit 18. FIG. 2 shows an error interpolation circuit 18 according to the present invention.
This is an example. Reproduction data is supplied from an input terminal indicated by reference numeral 21 and stored in a data memory 23. An error flag accompanying the reproduction data is supplied from an input terminal indicated by reference numeral 22, and is stored in an error flag memory 24. These memories 22 and 24 have a capacity capable of storing data for one frame and an error flag.

The data memory 23 simultaneously generates pixel data of a block of (5 × 5) pixels centering on the pixel to be interpolated. In FIG. 3, BLK1 indicates one block. A (5 × 5) block centered on the interpolation target pixel X indicated by a black dot is configured. Of the 25 pixels, 16 pixels A to P are used for the interpolation calculation. The interpolation operation forms interpolation values IP1 to IP8 for various interpolation directions as described below.

IP1 = (A + B) / 2 IP2 = (C + D) / 2 IP3 = (E + F) / 2 IP4 = (G + H) / 2 IP5 = (I + J) / 2 IP6 = (K + L) / 2 IP7 = (M + N) / 2 IP8 = (O + P) / 2

The pixel data A to P of the block output from the data memory 23 and the pixel X to be interpolated are sequentially included in the block. As shown in FIG. 3, reading of the data memory 23 is performed such that when the block BLK1 is formed, the block BLK2 is formed next. That is, blocks shifted one pixel at a time in the horizontal direction are sequentially formed. A data memory 23 is provided for forming overlapping blocks. In addition, when the formation of a block is completed for one line period and a new block is formed therebelow, a block shifted by one line is formed. The error flag from the error flag memory 24 is also a 1-bit flag output in synchronization with each data.

The pixels A to P from the data memory 23 are AD
It is supplied to the RC encoding circuit 25 and the arithmetic circuit 26.
The interpolation target pixel X is supplied to the selector 28 via the delay circuit 27. The arithmetic circuit 26 outputs one of the interpolation values IP1 to IP8 according to the arithmetic expression designated as the optimal interpolation. In this example, information designating an arithmetic expression for optimal interpolation is supplied from the selector 29 to the arithmetic circuit 26, and the arithmetic circuit 26 generates an interpolated value using the specified arithmetic expression. The output of the arithmetic circuit 26 is used as one input of the selector 28.
Supplied to The output of the delay circuit 27 is supplied as the other input of the selector 28.

The error flag via the delay circuit 31 is supplied to the selector 28 as a control signal. What
Note that the delay circuit 31 is required to determine the optimal interpolation data.
Time, error flag from error flag memory 24
And the output data M of the ADRC encoder 25 are delayed.
It is for time adjustment. When the error flag indicates that the interpolation target pixel is in error, the selector 2
8 selects an interpolation value from the arithmetic circuit 26, and this interpolation value is generated at the output terminal 32. When the pixel to be interpolated is not an error, actual pixel data from the delay circuit 27 is selectively taken out to the output terminal 32.

The ADRC encoding circuit 25 has a maximum pixel value MAX, a minimum pixel value MIN, and a minimum pixel value MIN for each block of 25 pixels.
A dynamic range DR which is a difference between X and MIN is detected, and a pixel value is set to n according to the dynamic range DR.
Requantize to bits. However, when the pixel value is 8 bits, (7 ≧ n ≧ 1), and the data is compressed.

FIG. 4 shows an example of the ADRC encoding circuit 25. 4, the detection circuit 42 detects the maximum value MAX and the minimum value MIN for each block from the data from the input terminal 41. MAX and MIN are supplied to the subtraction circuit 43, and the dynamic range DR
Occurs. The input data and MIN that have passed through the delay circuit 44 are supplied to the subtraction circuit 45, and the minimum value is removed from the subtraction circuit 45, thereby generating normalized pixel data. The dynamic range DR is supplied to the quantization circuit 46, the normalized pixel data is divided by the dynamic range DR, and n-bit quantized data is extracted from the output terminal 47.

Returning to FIG. 2, among the output data of the n-bit ADRC encoding circuit 25, 16 pixels A to P of the block excluding the pixel X to be interpolated at the center position
, And output data (referred to as data M) of (16 × n bits) obtained by synchronizing the quantized data. This data M
Is fixed mapping table 33 via delay circuit 31
Is supplied as a read address signal. Therefore, the mapping table 33 has (2 ^{n * 16} ) addresses.

Further, the interpolation target pixel X and the pixels A to P from the data memory 22 are supplied to the optimum interpolation determination circuit 35. The decision circuit 35 generates the above-described eight types of interpolation values IP1 to IP8 using the peripheral pixels A to P, and calculates the absolute value of the difference between the interpolation target pixel X which is a true value and each of the interpolation values IP1 to IP8. Generated and the one with the smallest value is determined as the optimal interpolation. Since there are eight types of interpolation calculations, the decision circuit 54
Output data (referred to as data S) is 3 bits. Data M which is the output of the ADRC encoding circuit 25
(16 × n + 3) bits, which are both the data and the data S, are supplied to the switching circuit 36.

The switching circuit 36 is generated for each of the k accumulation memories M1 to Mk for each block of each one frame period in the k frame period (16 ×
Co when the data M n) bits long is supplied as address
Is supplied with data S having a length of 3 bits,
When the processing is completed, the data M and S of the next frame are
It is supplied to the next accumulation memory. The memories M1 to Mk form a frequency distribution table for each address. That is, in one frame, (16 × n bits) data M and 3
The frequency at which the bit data S appears is integrated. When a frequency distribution table for a certain frame is formed in the memory Mi, a frequency distribution table for the next frame is formed in the memory Mi + 1.
In this way, from the frame currently being processed, the past k
Frequency distribution tables for frames are stored in the memories M1 to Mk, respectively. In this case, the memory M1~Mk, d
An error flag is supplied from the error flag memory 24, and when the interpolation target pixel X has an error, counting as a frequency is prohibited. This is because when the interpolation target pixel X has an error, the reliability of the data S from the optimal interpolation determination circuit 35 is poor.

The frequency distribution tables stored in the memories M1 to Mk are added by an adder circuit 37. The addition circuit 37
Weight addition is performed by the weight coefficient wi from the terminal 38. Weight coefficient wi (i = 1, 2,...)
, K) is always 1 when the frequencies for k frames are simply added. This is the case when the image has no significant change in the time direction, as well as in the normal case. Further, when the change of the image in the time direction such as a scene change is large, the frequency distribution changes largely before and after the change. At this time, it is necessary to improve the accuracy without using the frequency distribution before the scene change. To meet this need, the weighting factor wi is set to 0 for the frame before the change, and the weighting factor wi + 1 is set to 1 for the subsequent frame.

The output of the adding circuit 37 is supplied to the detecting circuit 39. The detection circuit 39 detects the maximum value of each data M in the frequency distribution table to which the k frames have been added, and indicates information corresponding to the detected maximum value, that is, the data M and the optimal interpolation number for the k frame. The pair with the data S is sent to the variable mapping table 34. Specifically, the data M is sequentially changed, data S corresponding to the maximum frequency in each value of the data M is detected, and a pair of the data M and the data S is received by the variable mapping table 34.

The variable mapping table 34 receives a pair of data M and data S from the detection circuit 39, writes the value of the data S using the data M as an address. As a result, a mapping table is created in which data M is used as an address and data S is used as an output. Further, the data M that has passed through the delay circuit 31 is input to the variable mapping table 34. Therefore, data S indicating the optimal interpolation determined by the encoded outputs (data M) of the peripheral data A to P is generated from the variable mapping table 34.

The fixed mapping table 33 is also a table that receives data M passed through the delay circuit 31 and outputs data S. However, the table is formed in advance by training. The outputs of the two mapping tables 33 and 34 are supplied to a selector 29, one of which is selected according to a control signal from a terminal 30. This control signal specifies a mapping table to be used. The data S from the selector 29 is supplied to the arithmetic circuit 2
6 and the arithmetic circuit 26 performs an optimal interpolation operation indicated by the data S. The resulting interpolated value is the selector 2
8 is supplied.

Before explaining the creation of the variable mapping table 33, referring to FIG.
3 will be described. In FIG. 5, at 51,
A digital video signal is supplied, which is supplied to a data memory 52. The output of the sequential block from the data memory 52 is supplied to an ADRC encoding circuit 53 and an optimal interpolation determining circuit 54. The output of the ADRC encoding circuit 53 (corresponding to data M) and the output of the decision circuit 54 (corresponding to data S) are supplied to the memory 55 as addresses.

The data memory 52, the ADRC encoding circuit 53, and the decision circuit 54 are different circuits having the same functions as the data memory 23, the ADRC encoding circuit 25, and the decision circuit 35 of the interpolation circuit 18 in FIG. is there. However, the input data is preferably standard video data for training. For example, a signal composed of still images of various patterns can be adopted.

The decision circuit 54 generates the above-mentioned eight types of interpolation values IP1 to IP8 using the peripheral pixels A to P, and calculates the difference between the interpolation target pixel X which is a true value and each of the interpolation values IP1 to IP8. An absolute value is generated, and the one having the minimum value is determined as the optimal interpolation. Since there are eight types of interpolation calculations, the decision circuit 5
The output data from 4 is 3 bits. On the other hand, ADR
The output of the C encoding circuit 53 is 16 × n bits. The (16 × n + 3) bits combining these two data are used as the address of the memory 55.

FIG. 6A shows a memory area of the memory 55. By being the (2 n ^{* 16)} pieces of the address specified by the generated data ADRC encoding circuit 53 is prescribed longitudinal direction of the memory area, the lateral direction is defined by two corresponding ^three address types and optimum interpolation You. The memory 55 performs a read operation and a write operation for a specified address in one cycle period. The read output of the memory 55 is supplied to the adding circuit 56, and the value incremented by 1 by the adding circuit 56 is rewritten at the same address of the memory 55.

When the supply of the still image signals of various pictures ends, that is, when the training ends, the memory 5
5 stores a frequency distribution table. As shown by an arrow in FIG. 6A, when looking at a certain address in the vertical direction,
As shown in FIG. 6B, there are data of the respective frequencies of the eight addresses.

The read address of the memory 55 is formed by an address counter 57. When the training is completed, the data at each address of the memory 55 is read by the read address. The read address is 0-2
Increment to ^{n * 16} . The read data is supplied to the detection circuit 58. The detection circuit 58 detects the address of the maximum frequency (that is, the optimal interpolation number) in the frequency distribution table of each address (FIG. 6B).

The detection signal of the detection circuit 58 is supplied to the memory 59 as a data input, and the address counter 5
7 is written according to the address. As a result of training in this manner, 5 ×
ADRC of 16 pixels used for interpolation in area 5
The address (data M) defined by the encoded data and the optimal interpolation data (data S) at that address are stored. The table stored in the memory 59 is the fixed mapping table 33 used in the interpolation circuit 18 as described above.

The variable mapping table 34 is based on the same concept as the formation of the fixed mapping table 33 described above. However, the fixed mapping table 33 uses standard picture data, while the variable mapping table 34 uses the previous k frame reproduction data. Each of the integration memories M1 to Mk has the configuration shown in FIG.
Is formed. The frequency distribution table is added in the adder circuit 37 to obtain a frequency distribution table for k frames.

Then, in the detection circuit 39, the data M
, The data S having the maximum frequency is detected. A pair of the data M and the data S having the maximum frequency is supplied to the variable mapping table 34. Then, data S indicating the optimal interpolation is output by one of the variable mapping table 34 and the fixed mapping table 33 created in advance as described above. The arithmetic circuit 26 generates an interpolated value using an arithmetic expression according to the data S. The interpolation value is selected by the selector 28 in place of the interpolation target pixel X having an error.

An error flag is supplied to the arithmetic circuit 26 via the delay circuit 31. When an error exists in any of the pixels A to P, the above-described mapping table 3 is used.
It is detected that the optimal interpolation data from 3 or 34 cannot be used. In this case, the average value of the values of the two pixels without error is formed as an interpolation value, and this is used as the selector 28.
Output to

Unlike the above-described embodiment, in order to compress the data amount of a plurality of pixels used for interpolation, an average value of a plurality of pixels is calculated, and the difference between each pixel value and the average value is vector-quantized. You may do it. As an interpolation method, not only spatial interpolation but also interpolation in the time direction may be adopted as one of the candidates for the optimal interpolation. Further, the block encoding circuit 5 may be a DCT.

[0046]

According to the present invention, since the optimum interpolation according to the value of the peripheral pixel is obtained by analyzing the received / reproduced data of the past k frames or by training in advance, the difference between the two pixels is simply obtained. The accuracy can be made higher as compared with determining the optimal interpolation based on the magnitude of the absolute value. Further, the hardware can be simplified without the need for a subtraction circuit and a comparison circuit for determining the optimal interpolation.

[Brief description of the drawings]

FIG. 1 shows a digital V to which the present invention can be applied.
It is a block diagram of a recording / reproducing circuit of TR.

FIG. 2 is a block diagram illustrating a configuration of an example of an error interpolation circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an example of a block configuration according to an embodiment of the present invention.

FIG. 4 is a block diagram of an ADRC encoding circuit according to one embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration at the time of training for creating a mapping table in one embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating a case where a mapping table is created.

[Explanation of symbols]

 18 Error interpolation circuit 25 ADRC encoding circuit 26 Interpolation operation circuit 28 Selector 33 Fixed mapping table 34 Variable mapping table

Continuation of front page (56) References JP-A-4-139959 (JP, A) JP-A-1-200883 (JP, A) JP-A-2-214388 (JP, A) JP-A-2-217086 (JP) JP-A-2-238787 (JP, A) JP-A-3-30522 (JP, A) JP-A-63-111781 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04N 7/24-7/68

Claims (3)

(57) [Claims] 1. A digitizer for interpolating erroneous pixel data in a received or reproduced digital image signal.
In a total image signal receiving / reproducing apparatus, a plurality of pixels close to a received or reproduced pixel to be interpolated.
Compression encoding of a number of received or reproduced pixel data,
Encoding means for generating a compression encoded output, to the proximity to said received or reproduced interpolation target pixel
Using multiple received or reproduced pixel data
The numbers calculated using different interpolation formulas
And the true value of the pixel to be interpolated.
Is determined, and a pair is determined with the determined interpolation expression.
Generate the optimal interpolation data corresponding to
Multiple occurrences of the above optimal interpolation data for each
Form a frequency distribution table integrated for each frame, and
In the cloth table, for each of the compression-encoded outputs
The above optimum in which the frequency of appearance of the above optimum interpolation data becomes the maximum value
Interpolation data is detected, and the detected optimal interpolation data is
The stored map for each of the above compression encoded outputs.
Mapping table creation means for creating a ping table
And the delayed encoded output is mapped to the mapping table.
The interpolation target pixel supplied to the
If there is, output from the above mapping table
Generated by the optimal interpolation data and the corresponding interpolation
The optimal interpolation value obtained by the interpolation
A digital image signal receiving / reproducing apparatus, characterized by comprising means for selectively outputting the digital image signal in place of 2. A digitizer for interpolating erroneous pixel data in a received or reproduced digital image signal.
In a total image signal receiving / reproducing apparatus, a plurality of pixels close to a received or reproduced pixel to be interpolated.
Compression encoding of a number of received or reproduced pixel data,
Encoding means for generating a compression encoded output, is prepared in advance by training, it delayed the pressure
The compressed encoded output is supplied, and the compressed encoded output is
The first mapping table indicating the relationship with inter-data
Created using the stored first mapping table storage means and the received or reproduced pixel data,
The delayed compressed encoded output is provided and the compressed code
Second map showing the relationship between the encoded output and the optimal interpolation data
Of the second mapping table in which the mapping table is stored
When the delayed interpolation target pixel is in error,
Selected one of the first and second mapping tables
The optimal interpolation data output from the
The optimal interpolation value generated by
Means for selectively outputting in place of target pixel
When, to close with respect to the received or reproduced interpolation target pixel
Using multiple received or reproduced pixel data
The numbers calculated using different interpolation formulas
And the true value of the pixel to be interpolated.
Is determined, and a pair is determined with the determined interpolation expression.
Generate the optimal interpolation data corresponding to
Multiple occurrences of the above optimal interpolation data for each
To form a frequency distribution table which has been integrated frame, in the frequency distribution table, for each of the compression encoded output
The optimal interpolation data in which the appearance frequency of the optimal interpolation data is the maximum value is detected, and the detected optimal interpolation data is
The stored second mapping table is stored in the compressed code
A second mapping to be created for each of the encoded outputs
Means for creating a table, wherein the first mapping table is used for the training.
The first mapping table creation means created by using
For the pixel to be interpolated in the intended digital image signal
Compression encoding of multiple neighboring pixel data, and compression encoding
Forming an output, and
A plurality of pixel data adjacent to the interpolation target pixel is
Using different interpolation formulas
Between the calculated interpolation values and the true value of the interpolation target pixel
Is determined, and the determined interpolation formula is determined.
Generate the optimal interpolation data corresponding to the arithmetic expression and
Appearance of the above optimal interpolation data for each of the encoded outputs
Form a frequency distribution table in which frequencies are integrated for multiple frames,
In the frequency distribution table, each of the compression-encoded outputs
The frequency of occurrence of the optimal interpolation data for
The optimal interpolation data is detected, and the detected optimal interpolation data is detected.
The first mapping table in which the interim data is stored
What to create for each of the above compression encoded outputs
Characteristic digital image signal receiving / reproducing device. 3. When forming the frequency distribution table, an interpolation pair
If the target pixel has an error, process it so that it is not included in the frequency.
Claim 1 Symbol placement of the digital image signal, characterized in Rukoto
Receiving / reproducing device.