JP3297781B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device used for a resistance, a wiring, a diffusion layer and the like of the semiconductor device.

[0002]

2. Description of the Related Art A polycrystalline silicon film in a semiconductor device comprises a gate electrode, a diffusion source, a contact opening, a wiring, a resistor, a thin film transistor (TFT).
or)]. Then, after the polycrystalline silicon film is formed according to the application, the polycrystalline silicon film is doped with impurities by an ion implantation method, a diffusion method, or the like. Alternatively, a polycrystalline silicon film is formed in a state containing impurity ions. For example, it has been performed by a CVD method.

[0003]

However, when ion implantation is performed on the polycrystalline silicon film, the crystal grain size of the polycrystalline silicon film is not precisely controlled. Therefore, the resistance value of the polycrystalline silicon film does not become as designed. For example, even if a process using ion-implanted polycrystalline silicon is developed instead of using DOPOS (doped polycrystalline silicon) as a diffusion source, the diffusion of ion-implanted impurity ions and the polycrystalline silicon film are performed by a subsequent heat treatment. Crystallization occurs simultaneously. Therefore, polycrystalline silicon having characteristics (for example, resistance) different from those in the case where DOPOS is used is formed. When such a polycrystalline silicon film is used as an electrode material, characteristics as designed cannot be obtained. Further, the resistance of the polycrystalline silicon film varies depending on the grain size of the crystal formed by crystallization. Therefore, a polycrystalline silicon film having a desired resistance value cannot be formed.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a polycrystalline silicon film having a desired resistance is partially obtained by partially controlling the crystal grain size of the polycrystalline silicon film. And

[0005]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to achieve the above object. That is, in the first method, first, in a first step, a polycrystalline silicon layer is formed on a base, and then impurity ions are selectively implanted into the polycrystalline silicon layer by an ion implantation method. At this time, by controlling the ion implantation energy and setting the implantation depth of the impurity ions, an amorphous layer corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer. In the second step, a heat treatment is performed to crystallize the amorphous layer corresponding to the thickness of the polycrystalline silicon layer left below the amorphous layer, which is different from the initial polycrystalline silicon layer. A polycrystalline silicon layer having a crystal grain size is formed.

In a second method, a polycrystalline silicon layer is formed on a substrate in a first step, and then a covering layer is formed to selectively cover the polycrystalline silicon layer. Next, in a second step, impurity ions are implanted into the polycrystalline silicon layer through the coating layer by an ion implantation method. At the same time, impurity ions are implanted into a portion of the polycrystalline silicon layer which is not covered with the covering layer. Then, a first amorphous layer is formed on a portion of the polycrystalline silicon layer which is covered with the covering layer, and a first amorphous layer is formed on a portion of the polycrystalline silicon layer which is not covered with the covering layer. To form a thick second amorphous layer. Then in the third step,
Heat treatment is performed to crystallize the first amorphous layer and the second amorphous layer, thereby forming a first polycrystalline silicon layer on the first amorphous layer side. At the same time, a second polycrystalline silicon layer having a larger crystal grain size than the first polycrystalline silicon layer is formed on the second amorphous layer side.

In a third method, after a polycrystalline silicon layer is formed on a semiconductor substrate in a first step, ion implantation is performed when impurity ions are selectively implanted into the polycrystalline silicon layer by an ion implantation method. By setting the implantation depth of the impurity ions by controlling the implantation energy, an amorphous layer corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer. Next, in a second step, a heat treatment is performed to crystallize the amorphous layer according to the thickness of the polycrystalline silicon layer left below the amorphous layer, thereby forming the polycrystalline silicon layer formed first. To form a polycrystalline silicon layer having a different crystal grain size. At the same time, impurity ions implanted into the polycrystalline silicon layer are diffused into the surface layer of the semiconductor substrate to form an impurity diffusion layer.

In a fourth method, after a polycrystalline silicon layer is formed on a semiconductor substrate in a first step, impurity ions are selectively and entirely implanted in an entire region in the thickness direction of the polycrystalline silicon layer by an ion implantation method. Implantation is performed to modify the region into which the impurity ions have been implanted into an amorphous layer. Then, in a second step, a heat treatment is performed to modify the amorphous layer into a single-crystal silicon layer. At the same time, impurity ions in the amorphous layer are diffused into the surface layer of the semiconductor substrate to form an impurity diffusion layer.

The depth t of the amorphous layer at the time of the ion implantation is controlled based on the LSS (Lindhard, Scharff, Schiott) theory based on the projected range Rp of the ion and the projected range dispersion ΔR.
Using p, the ion implantation energy is set according to the equation of t = Rp + κ ・ ΔRp, 2 ≦ κ ≦ 5.

The ion implantation is performed by an oblique ion implantation method in which the incident angle of the impurity ions is set to a predetermined angle.

As the impurity ions, ions of at least one of silicon and elements heavier than silicon are used.

[0012]

In the first method, when the impurity ions are selectively implanted into the polycrystalline silicon layer by the ion implantation method, the ion implantation energy is controlled to set the implantation depth of the impurity ions. An amorphous layer corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer. Since the heat treatment is performed, the amorphous layer has a different crystal grain size from the polycrystalline silicon layer formed first, corresponding to the thickness of the polycrystalline silicon layer left thereunder. Layer.

In the second method, after forming a coating layer selectively covering the polycrystalline silicon layer, impurity ions are implanted into the polycrystalline silicon layer including the portion covered with the coating layer by an ion implantation method. Therefore, a shallow first amorphous layer is formed by implanting shallow impurity ions in the upper layer of the polycrystalline silicon layer covered with the covering layer. On the other hand, impurity ions are deeply implanted into the upper layer of the polycrystalline silicon layer which is not covered with the covering layer, and the second layer is thicker than the first amorphous layer.
An amorphous layer is formed. After that, heat treatment is performed,
The first and second amorphous layers are crystallized by taking over the crystal of the polycrystalline silicon layer remaining on each lower surface side. At this time, since the crystal grain size is determined according to the thickness of the remaining polycrystalline silicon layer, more polycrystalline silicon layers are formed on the remaining first amorphous layer side. The first polycrystalline silicon layer has a smaller crystal grain size than the second polycrystalline silicon layer formed on the second amorphous layer side.

In the third method, since the ion implantation energy for selectively implanting impurity ions into the polycrystalline silicon layer is controlled, the implantation depth of the impurity ions changes. Therefore, an amorphous layer corresponding to the ion implantation depth is formed in the polycrystalline silicon layer. Then, by performing the heat treatment, the amorphous layer is crystallized. At the same time, impurity ions implanted into the polycrystalline silicon layer diffuse into the semiconductor substrate, so that an impurity diffusion layer is formed on the surface of the semiconductor substrate.

In the fourth method, after a polycrystalline silicon layer is formed on a semiconductor substrate, impurity ions are selectively implanted by ion implantation into the entire region in the thickness direction of the polycrystalline silicon layer. The entire region in the thickness direction of the polycrystalline silicon layer into which the impurity ions have been implanted becomes an amorphous layer. Since the heat treatment is performed, the amorphous layer takes over the crystal of the semiconductor substrate. For example, if the semiconductor substrate is single crystal, the amorphous layer becomes a single crystal silicon layer. At the same time, the impurity ions in the amorphous layer diffuse into the surface layer of the semiconductor substrate to form an impurity diffusion layer.

The depth t of the amorphous layer formed by the above-described ion implantation is controlled based on the LSS theory by using the projected range Rp of ions and the projected range dispersion ΔRp. > Since it is performed by the injection energy, almost exactly,
The implantation depth of the impurity ions is set. Therefore, the film thickness which is not amorphized but remains in the state of the polycrystalline silicon layer is also set.

Since the ion implantation is performed by an oblique ion implantation method in which the incident angle of the impurity ions is set to a predetermined angle, the impurity ions are implanted even if the polycrystalline silicon layer is formed in the step portion. You.

Since at least one of silicon and an element heavier than silicon is used as the impurity ions, the portion of the polycrystalline silicon layer into which the impurity ions are implanted becomes an amorphous layer.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the manufacturing process diagram of FIG.

As shown in FIG. 1A, in the first step, first, a polycrystalline silicon film (not shown) was formed on the substrate 11 by a film forming technique such as a CVD method, a vapor deposition method, or a sputtering method. Thereafter, the polycrystalline silicon film is patterned by lithography and etching to form a polycrystalline silicon layer 12.

Subsequently, as shown in FIG.
Forming film (not shown) covering the polycrystalline silicon layer 12 by a film forming technique such as a deposition method, an evaporation method, and a sputtering method.
Is formed of, for example, silicon oxide. Thereafter, the mask forming film is patterned by lithography and etching to form a mask 51 that selectively covers the polycrystalline silicon layer 12. Next, impurity ions 61 are selectively implanted into the polycrystalline silicon layer 12 by an ion implantation method using the mask 51. At this time, by changing the implantation depth of the impurity ions 61 by controlling the ion implantation energy, the amorphous layer 13 corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer 12. In this figure, impurity ions 61 are formed over the entire region in the film thickness direction.
Is implanted to make the region amorphous.

As the impurity ions 61, one or more ions of silicon and at least one of the heavier elements are used in order to make the polycrystalline silicon layer 12 amorphous. For example, the ions include silicon ions (Si ⁺ ), arsenic ions (As ⁺ ), phosphorus ions (P ⁺ ), and antimony ions (Sb ⁺ ).

Incidentally, by the same ion implantation method as described above,
After selectively amorphizing the polycrystalline silicon film, the polycrystalline silicon film may be patterned to form the polycrystalline silicon layer 12 including the amorphized portion.

Thereafter, the mask 51 may be removed by etching. When the mask 51 is formed of a resist, the mask 51 is removed by performing at least one of an ashing process and a wet process, for example.

Subsequently, a second step shown in FIG. 1C is performed. This figure shows a state after the mask (51) has been removed. In this step, a heat treatment is performed to polycrystallize the amorphous layer (13). And the amorphous layer (13)
A polycrystalline silicon layer 14 having a crystal grain diameter different from that of the polycrystalline silicon layer 12 corresponding to the thickness of the polycrystalline silicon layer 12 left thereunder is obtained. The mask (5
The crystal grain size of the portion of the polycrystalline silicon layer 12 covered by 1) does not change.

In the embodiment described with reference to FIG. 1, since the ion implantation energy is controlled to set the implantation depth of the impurity ions 61, the ion implantation depth is determined by the ion implantation energy. Then, the depth of the amorphous layer 13 is determined according to the ion implantation depth. That is,
The thickness of the polycrystalline silicon layer 12 left under the amorphous layer 13 is also determined. Since the heat treatment is performed, the amorphous layer 13 is crystallized. At this time, the smaller the thickness of the remaining polycrystalline silicon layer 12, the larger the crystal grain size to be formed. Therefore, the polycrystalline silicon layer 14 formed by recrystallization of the amorphous layer 13 has impurity ions 61
Since the crystal grain size is larger than that of the polycrystalline silicon layer 12 not implanted, the resistance is low. Further, since the impurity ions 61 are ions of silicon and elements heavier than silicon, the region of the polycrystalline silicon layer 12 into which the impurity ions 61 are implanted becomes amorphous.

Next, an example of a specific method for simultaneously forming a wiring and a resistor using the first invention will be described. Note that FIG. 1 is used in the description.

First, the first step is performed. The film thickness of 110 is formed on the substrate 11 by the low pressure CVD method (the film forming temperature is 620 ° C.).
A polycrystalline silicon film having a thickness of nm is formed. Thereafter, the polycrystalline silicon film is patterned by lithography and etching to form a polycrystalline silicon layer 12. Subsequently, the polycrystalline silicon layer 12 is formed by CVD.
A mask forming film (not shown) covering
Then, a mask 51 for selectively covering the polycrystalline silicon layer 12 with the mask forming film is formed by lithography and etching.

Then, impurity ions (eg, silicon ions) 61 are selectively implanted into the polycrystalline silicon layer 12 by an ion implantation method using the mask 51. In this ion implantation, the ion implantation energy is 25
KeV, dose amount is 3P (peta) ions / cm ²
Set to. When the ion implantation is performed in this manner, the polycrystalline silicon layer 12 into which the silicon ions have been implanted becomes entirely amorphous in the film thickness direction to become the amorphous layer 13. The portion of the polycrystalline silicon layer 12 covered by the mask 51 maintains the initial crystal grain size (about 50 nm).

Subsequently, a second step is performed. That is, heat treatment for recrystallization (for example, heating at 600 ° C. for 80 hours)
Is performed to crystallize the amorphous layer 13. The polycrystalline silicon layer 14 formed by crystallization has a larger crystal grain size than the non-amorphized polycrystalline silicon layer 12. The resistance of the polycrystalline silicon layer 14 is about 200
Ω / □. On the other hand, the crystal grain size of the non-amorphized polycrystalline silicon layer 12 was about 50 nm, and the resistance value was about 900 Ω / □.

Next, an embodiment of the second invention will be described with reference to the manufacturing process diagram of FIG. The same components as those described in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2A, in the first step, first, a polycrystalline silicon film (not shown) is formed on the substrate 11 by a film forming technique such as a CVD method, a vapor deposition method, and a sputtering method. I do. Thereafter, the polycrystalline silicon film is patterned by lithography and etching to form a polycrystalline silicon layer 12. Next, a coating layer forming film 21 covering the polycrystalline silicon layer 12 is formed of, for example, silicon oxide by a film forming technique such as a CVD method, an evaporation method, and a sputtering method. Thereafter, the portion indicated by the two-dot chain line of the coating layer forming film 21 is removed by lithography and etching to form a coating layer 22 that selectively covers the polycrystalline silicon layer 12.

Next, a second step shown in FIG. 2B is performed. In this step, impurity ions 62 are added to the polycrystalline silicon layer 12 through the coating layer 22 by ion implantation.
Inject. At the same time, the impurity ions 62 are also implanted into the polycrystalline silicon layer 12 that is not covered with the covering layer 22. As a result, the polycrystalline silicon layer 12 into which the impurity ions 62 have been implanted is made amorphous, and a first amorphous layer 23 is formed on the polycrystalline silicon layer 12 covered with the covering layer 22. A second amorphous layer 24 is formed on the polycrystalline silicon layer 12 which is not covered with the covering layer 22. Here, a case is shown in which the first amorphous layer 23 is formed over the polycrystalline silicon layer 12 and the second amorphous layer 24 is formed over the entire region of the polycrystalline silicon layer in the thickness direction.

After the polycrystalline silicon film is selectively covered with the coating layer, the polycrystalline silicon film is made amorphous by the same ion implantation method as described above. Next, the polycrystalline silicon film may be patterned to form a polycrystalline silicon layer 12 having an amorphous portion. As the impurity ions 62, the same ions as described in the embodiment of the first invention are used.

Thereafter, the coating layer 22 may be removed, for example, by etching. Then, a third step shown in FIG. 2C is performed. This figure shows the state after the covering layer (22) has been removed. In this step, heat treatment is performed to crystallize the first and second amorphous layers (23) and (24). Then, a first polycrystalline silicon layer 25 is formed in a portion covered by the covering layer (22), and a crystal grain size in the portion not covered by the covering layer (22) is larger than that of the first polycrystalline silicon layer 25. A large second polycrystalline silicon layer 26 is formed.

In the second invention, the polycrystalline silicon layer 1
2 is selectively covered with the coating layer 22, and then the impurity ions 6
2 is implanted, the implantation depth of the impurity ions 62 is controlled by the thickness of the coating layer 22. Therefore, the impurity ions 62 are implanted deeper into the polycrystalline silicon layer 12 which is not covered by the portion covered by the covering layer 22. By controlling the depth of the impurity ions 62 as described above, the thickness of the formed amorphous layer is controlled. That is, the polycrystalline silicon layer 12 not covered with the covering layer 22 has a second non-crystalline layer that is thicker than the first amorphous layer 23 formed on the polycrystalline silicon layer 12 covered with the covering layer 22. A crystalline layer 24 is formed. Therefore, the polycrystalline silicon layer 12 is thicker below the first amorphous layer 23 than under the second amorphous layer 24. Then, since the heat treatment is performed, the first and second amorphous layers 23 and 24 are formed.
Is crystallized taking over the crystal of the polycrystalline silicon layer 12 remaining thereunder. Therefore, the first polycrystalline silicon layer 25 formed by crystallizing the first amorphous layer 23 side where a large amount of the polycrystalline silicon layer 12 remains remains, and the first polycrystalline silicon layer 25 formed by crystallizing the second amorphous layer 24 side is formed. The crystal grain size is smaller than that of the two polysilicon layers 26. Therefore, the first polycrystalline silicon layer 25 has a higher resistance than the second polycrystalline silicon layer 26.

Next, an example of a specific method for simultaneously forming a wiring and a resistor by using the second invention will be described. Note that FIG. 2 is used in the description.

First, the first step is performed. The film thickness of 110 is formed on the substrate 11 by the low pressure CVD method (the film forming temperature is 620 ° C.).
A polycrystalline silicon film having a thickness of nm is formed. Thereafter, the polycrystalline silicon film is patterned by lithography and etching to form a polycrystalline silicon layer 12. Subsequently, the polycrystalline silicon layer 12 is formed by CVD.
Is formed of, for example, a silicon oxide film having a thickness of 40 nm to cover the polycrystalline silicon layer 12 by the lithography technique and etching. I do.

Then, the implantation depth of impurity ions (for example, arsenic ions) 61 into the polycrystalline silicon layer 12 is selectively controlled by the ion implantation method using the coating layer 22. In this ion implantation, for example, the ion implantation energy is 70 keV and the dose is 3P (peta) i.
ons / cm ² . When ion implantation is performed in this manner, arsenic ions are implanted into the upper layer of the polycrystalline silicon layer 12 which is covered with the coating layer 22, and the region 70 nm deep from the surface becomes amorphous and becomes 1 amorphous layer 23
Is formed. Underneath it are four polycrystalline silicon layers 12.
It remains at a thickness of 0 nm. Arsenic ions are implanted into the entire portion of the polycrystalline silicon layer 12 not covered with the coating layer 22 in the film thickness direction, and the entire region in the film thickness direction is amorphized to form the second amorphous layer. Layer 24 is formed.

Subsequently, a second step is performed. That is, heat treatment for recrystallization (for example, heating at 700 ° C. for 2 hours and 9
(Heating at 00 ° C. for 20 minutes) to form the first and second amorphous layers 2.
Crystallize 3,24. The portion covered by the coating layer 22 becomes the first polycrystalline silicon layer 25 having a small grain size.
The portion of the second amorphous layer 24 not covered by the second amorphous layer 24 becomes the second polycrystalline silicon layer 26 having a large grain size. Then, the resistance value of first polycrystalline silicon layer 25 becomes approximately 650 Ω / □, and the resistance value of one second polycrystalline silicon layer 26 becomes approximately 450
Ω / □.

Next, an embodiment of the third invention will be described with reference to the manufacturing process diagram of FIG. The same components as those described in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, the semiconductor substrate 3
1, an insulating film 32 is formed.
2 has a first opening 33 formed therein. First, in a first step, a polycrystalline silicon film (not shown) is formed on the insulating film 32 including the inside of the first opening 33 by a film forming technique such as a CVD method, a vapor deposition method, and a sputtering method. Thereafter, the polycrystalline silicon film is patterned by lithography and etching to form a polycrystalline silicon layer 12.

Subsequently, as shown in FIG.
The mask 53 covering the polycrystalline silicon layer 12 is formed of, for example, silicon oxide by a film forming technique such as a deposition method, an evaporation method, and a sputtering method. Thereafter, the mask 53 is patterned by lithography and etching,
The second opening 54 is formed in the mask 53 on the first opening 33. Then, impurity ions 63 are selectively implanted into the polycrystalline silicon layer 12 by an ion implantation method using the mask 53. At this time, the implantation depth of the impurity ions 63 is set by controlling the ion implantation energy. Thus, the amorphous layer 13 corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer 12. As the impurity ions 63, the same ions as described in the embodiment of the first invention are used.

Thereafter, the mask 53 may be removed by etching. When the mask 53 is formed of a resist, the mask 53 is removed by performing at least one of an ashing process and a wet process, for example.

Subsequently, a second step shown in FIG. 3C is performed. This figure shows a state after the mask 53 is removed.
In this step, heat treatment is performed to polycrystallize the amorphous layer (13) to form a polycrystalline silicon layer. that time,
The impurity ions (63) implanted into the amorphous layer (13) are diffused into the surface layer of the semiconductor substrate 31 to form the impurity diffusion layers 16.

In the third aspect, since the implantation depth of the impurity ions 63 is set by controlling the ion implantation energy, the ion implantation depth is determined by the ion implantation energy. Then, the depth of the amorphous layer 13 is determined according to the ion implantation depth. That is, the thickness of the polycrystalline silicon layer 12 left below the amorphous layer 13 is also determined. Since the heat treatment is performed, the amorphous layer 13 is crystallized. At that time, the polycrystalline silicon layer 14 is formed by inheriting the crystallinity of the remaining polycrystalline silicon layer 12.
Further, the impurity ions 63 implanted into the polycrystalline silicon layer 12 diffuse into the semiconductor substrate 31. Therefore, the impurity diffusion layer 16 is formed on the surface layer of the semiconductor substrate 31.

The process described above can be applied when forming the emitter of an npn-type bipolar transistor. One example will be specifically described with reference to FIGS.

As shown in FIG. 4A, a normal npn
A p ⁺ -type base layer 36 is formed on the upper layer of the semiconductor substrate 31 having the n-type epitaxial layer 34 and the n ⁺ -type buried layer 35 thereunder, that is, a part of the upper layer of the n-type epitaxial layer 34 by the p-type bipolar transistor process. Have been. An insulating film 32 is formed on the semiconductor substrate 31.
Is formed, and a first opening 33 is formed on a part of the p ⁺ -type base layer 36.

First, in a first step, a polycrystalline silicon film (not shown) of, eg, a 110 nm film is formed on the insulating film 32 including the inside of the first opening 33 by a low pressure CVD method (film forming temperature: 620 ° C.). The film is formed thick. Thereafter, the polycrystalline silicon film is patterned by lithography and etching to form a polycrystalline silicon layer 12.

Subsequently, as shown in FIG.
Mask 5 covering polycrystalline silicon layer 12
3 is formed of, for example, silicon oxide having a thickness of 150 nm. Thereafter, the mask 53 is patterned by lithography and etching to form a second opening 54 in the mask 53 on the first opening 34. Then, impurity ions (for example, arsenic ions) 63 are selectively implanted into the polycrystalline silicon layer 12 by an ion implantation method using the mask 53. In this ion implantation, for example, the ion implantation energy is set to 40 keV, and the dose is set to 6P (peta) ions / cm ² . When the ion implantation is performed in this manner, the portion of the polycrystalline silicon layer 12 that is not covered with the mask 53 becomes amorphous in a thickness direction to a depth of 76 nm from the surface. Then, an amorphous layer 13 is formed, and the polycrystalline silicon layer 12 is left under the amorphous layer 13 to have a thickness of 34 nm. When the thickness of the polycrystalline silicon layer 12 is 100 nm and the ion implantation energy is 30 keV, the thickness of the amorphous layer 13 is 62 nm.
nm, and the thickness of the underlying polycrystalline silicon layer 12 becomes 38 nm. On the other hand, arsenic ions are not implanted into the portion of the polycrystalline silicon layer 12 covered by the mask 53. Thereafter, the mask 53 is removed by, for example, etching.

Then, as shown in FIG. 4C, a second step is performed. That is, a heat treatment for recrystallization (for example, heating at 700 ° C. for 2 hours and heating at 900 ° C. for 20 minutes) is performed to make the amorphous layer (13) substantially equal to the initial polycrystalline silicon layer 12. To a polycrystalline silicon layer 14 having a crystal grain size of At this time, the impurity ions (63) implanted into the polycrystalline silicon layer 12 are diffused into a part of the surface layer of the p ⁺ -type base layer 36 to form the n ⁺ -type emitter layer 3.
7 (corresponding to the impurity diffusion layer 16) is formed. Note that the polycrystalline silicon layer 14 can be used as an emitter electrode.

Next, an embodiment of the fourth invention will be described with reference to the manufacturing process diagram of FIG. The same components as those described in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 5A, an insulating film 32 is formed on a semiconductor substrate 31 in the same manner as described with reference to FIG. 3A, and a first opening is formed in the insulating film 32. 3
Form 3 Then, the polycrystalline silicon layer 12 is formed on the insulating film 32 including the inside of the first opening 33.

Subsequently, as shown in FIG. 5B, a mask 53 for covering the polycrystalline silicon layer 12 is formed of silicon oxide in the same manner as described with reference to FIG. The second opening 54 is formed in the mask 53 on the first opening 33. Thereafter, impurity ions 64 are selectively implanted into the polycrystalline silicon layer 12 from the second opening 54 over the entire region in the thickness direction of the polycrystalline silicon layer 12 by ion implantation. The region into which the impurity ions 64 are implanted as described above is made amorphous, and the amorphous layer 1 is formed.
It becomes 3. As the impurity ions 64, the same ions as those described in the first embodiment are used.

Thereafter, the mask 51 may be removed by etching. When the mask 51 is formed of a resist, the mask 53 is removed by performing at least one of an ashing process and a wet process, for example.

Then, the second step shown in FIG. 5C is performed. This figure shows the case where the mask 53 is removed. In this step, heat treatment is performed to form the amorphous layer (13).
To a single-crystal silicon layer 17. At this time, the impurity ions (6
4) The impurity diffusion layer 16 is formed by diffusing into a part of the surface layer of the semiconductor substrate 11.

In the fourth aspect of the present invention, the impurity ions 64 are selectively implanted by ion implantation into the entire region of the polycrystalline silicon layer 12 in the thickness direction. It is reformed to. And the amorphous layer 1
3 is formed so as to reach the semiconductor substrate 31, so that the amorphous layer 13 is crystallized by inheriting the single crystallinity of the semiconductor substrate 31 by performing a heat treatment. Therefore, the amorphous layer 13 is modified into a single-crystal silicon layer 17. At the same time, the impurity ions 64 in the amorphous layer 13
Is diffused into the surface layer of the semiconductor substrate 11, so that the semiconductor substrate 3
The impurity diffusion layer 16 is formed on one surface layer.

The process described with reference to FIG.
It can be applied when forming the emitter of a pn-type bipolar transistor. An example will be described.

This process is almost the same as the process described with reference to FIG. The difference from the process described with reference to FIG. 4 is the condition of the ion implantation method using the mask 53. That is, arsenic ions are used as the impurity ions 64, the ion implantation energy is set to 70 keV, and the dose is set to 6P (peta) ions / cm ² . When the ion implantation is performed in this manner, as shown in FIG. 6A, the portion of the polycrystalline silicon layer 12 that is not covered with the mask 53 has impurity ions 64 over the entire region in the thickness direction.
Is implanted and becomes amorphous, and the region becomes the amorphous layer 13. On the other hand, impurity ions are not implanted into the portion of the polycrystalline silicon layer 12 covered by the mask 53.

Then, as shown in FIG. 6B, heat treatment for recrystallization (for example, heating at 550 ° C. for 2 hours,
(Heating at 00 ° C. for 20 minutes).
3) is modified into a single-crystal silicon layer 17. As described above, the heat treatment causes the amorphous layer (13) to become
Since the epitaxial growth occurs between the silicon layer 17 and the silicon layer 17, the single crystal silicon layer 17 is formed. Therefore, the contact resistance with the semiconductor substrate 31 is reduced. In the heat treatment, the impurity ions 6 implanted into the polycrystalline silicon layer 12 are removed.
4 diffuses into a part of the surface layer of the diffusion layer 36 serving as the p ⁺ -type base, so that the n ⁺ -type emitter layer 37 (the impurity diffusion layer 16
Is formed.

The control of the depth t of the amorphous layer 13 described in each of the first to fourth embodiments of the present invention is based on the LSS theory (Lindhard, Schar).
ff, theory based on the calculation of range parameters of particles injected into the solid, established by Schiott). That is, the ion implantation energy is derived by using the projected range Rp of the ions and the projected range variance ΔRp according to the following equation.

[0062]

(Equation 1)

[0063]

(Equation 2)

The depth t of the amorphous layer at the time of the above ion implantation is controlled by using the projected range Rp of the ions based on the LSS theory and the projected range dispersion ΔRp using the equations (1) and (2). The implantation depth is set almost exactly, so that the implantation depth of the impurity ions can be set almost exactly. Therefore, the film thickness which is not amorphized but remains in the state of the polycrystalline silicon layer is also set. As described above, the thickness of the polycrystalline silicon film remaining after the ion implantation is arbitrarily controlled by setting the ion implantation energy. Thereby, the crystal grain size of the polycrystalline silicon layer after recrystallization is controlled, and finally, the resistance value of the polycrystalline silicon layer is controlled.

Next, an application example in the case where the polycrystalline silicon layer 12 is used as a wiring will be described. Usually, the polycrystalline silicon layer 12 is rarely formed in a flat region. For example, as shown in FIG. 7, it is often formed on the surface of the base 11 having the step portion 41. In such a case, the ion implantation is performed by a so-called oblique ion implantation method. That is, the incident angle θ of the impurity ions 61 (62 to 64) is set to a predetermined angle, and the ion implantation is performed while rotating the base 11 in, for example, the direction of arrow A. Above incident angle θ
Is set to a certain angle within a range of, for example, about 30 ° to 60 °.

An example in which amorphization is performed by the above oblique ion implantation method will be described below. Silicon ions are obliquely implanted at an incident angle of 60 ° into the polycrystalline silicon layer 12 formed on the surface of the step portion 41 having a height of 200 nm by a low-pressure CVD method and then formed by lithography and etching. . In this case, the relative film thickness becomes 120 nm to 200 nm. Therefore, by performing ion implantation while setting the implantation energy of silicon ions to 45 keV, the entire layer of the polycrystalline silicon layer 12 can be made amorphous to form the amorphous layer 14. The film which has been completely amorphized in this manner is subjected to a recrystallization heat treatment (for example, 60
By performing the heating at 0 ° C. for 80 hours, a film having a low resistance (for example, 200 Ω / □) is obtained.

As described above, the impurity ions 61 (62 to 62)
64) using the oblique ion implantation method in which the incident angle θ is set to a predetermined angle, even if the polycrystalline silicon layer 12 is formed in the step portion 41, the impurity ions 61 ( 62-64) are injected.

[0068]

As described above, according to the first aspect of the present invention, the ion implantation energy for selective ion implantation is controlled, the implantation depth of impurity ions is determined, and the amorphous layer is formed. Determine the thickness. Therefore, a polycrystalline silicon layer having a desired thickness can be left below the amorphous layer. Also, since the amorphous layer is recrystallized to a crystal grain size corresponding to the remaining polysilicon layer, and the resistance value of the polysilicon layer corresponds to the crystal grain size, by controlling the ion implantation energy, It becomes possible to control the resistance value of the polycrystalline silicon layer after recrystallization. Therefore, a polycrystalline silicon layer having portions having different resistance values selectively can be formed.

According to the second aspect of the present invention, impurity ions are implanted shallowly into the polycrystalline silicon layer covered with the coating layer, and deeply implanted into the polycrystalline silicon layer not covered with the coating layer. Is done. Therefore, the thickness of the amorphous layer can be changed depending on the presence or absence of the covering layer, so that a polycrystalline silicon layer having a desired thickness can be left below the amorphous layer. Also, since the amorphous layer is recrystallized to a crystal grain size corresponding to the remaining polycrystalline silicon layer, and the resistance value of the polycrystalline silicon layer corresponds to the crystal grain size, it is necessary to control the thickness of the coating layer. This makes it possible to control the resistance value of the polycrystalline silicon layer after recrystallization. Therefore, a polycrystalline silicon layer having portions having different resistance values selectively can be formed.

According to the third aspect of the invention, the same effect as the first aspect of the invention can be obtained. At the same time, impurity ions implanted into the polycrystalline silicon layer can be diffused into the semiconductor substrate, so that a diffusion layer can be formed on the surface of the semiconductor substrate.

According to the fourth aspect of the present invention, after the impurity ions are selectively implanted into the entire region of the polycrystalline silicon layer in the thickness direction to modify the region into an amorphous layer, recrystallization is performed. As a result, the amorphous layer is crystallized while inheriting the crystallinity of the semiconductor substrate. For this reason, if the semiconductor substrate is a single crystal, it can be modified into a single crystal silicon layer, so that the resistance value of this portion can be reduced. In addition, since the impurity ions in the amorphous layer can be diffused into the surface layer of the semiconductor substrate by the heat treatment, a diffusion layer can be formed on the surface layer of the semiconductor substrate.

According to the fifth aspect of the present invention, the depth t of the amorphous layer at the time of the ion implantation is determined by the relational expression between the projected range Rp of the ions based on the LSS theory and the projected range dispersion ΔRp,
It can be set by t = Rp + κ · ΔRp, 2 ≦ κ ≦ 5. Therefore, the implantation depth of the impurity ions can be set almost accurately by the ion implantation energy, so that the thickness of the amorphous layer and the thickness of the polycrystalline silicon layer left under the amorphous layer are reduced. Can be set almost exactly. Therefore, the polycrystalline silicon layer obtained by recrystallization can be easily designed.

According to the sixth aspect of the present invention, since the above-described ion implantation is performed by the oblique ion implantation method, even if the polycrystalline silicon layer is formed in the step, impurity ions are implanted from the entire surface of the polycrystalline silicon layer. It becomes possible to do.

According to the seventh aspect of the present invention, since at least one of silicon and an element heavier than silicon is used as the impurity ions, a portion of the polycrystalline silicon layer into which the impurity ions are implanted is used. Can be made amorphous.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram showing an embodiment of the first invention.

FIG. 2 is a manufacturing process diagram showing an embodiment of the second invention.

FIG. 3 is a manufacturing process diagram showing an embodiment of the third invention.

FIG. 4 is an illustration of a method for forming an emitter according to a third invention.

FIG. 5 is a manufacturing process diagram showing an example of the fourth invention.

FIG. 6 is an explanatory diagram of a method of forming an emitter according to a fourth invention.

FIG. 7 is an explanatory diagram of amorphization by oblique ion implantation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Base 12 Polycrystalline silicon layer 13 Amorphous layer 14 Polycrystalline silicon layer 22 Coating layer 23 1st amorphous layer 24 2nd amorphous layer 25 1st polycrystalline silicon layer 26 2nd polycrystalline silicon layer 31 Semiconductor Base 16 Impurity diffusion layer 17 Monocrystalline silicon layer 61 Impurity ion 62 Impurity ion 63 Impurity ion 64 Impurity ion θ Incident angle

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyoshi Inoda 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-4-139718 (JP, A) JP-A Heisei JP-A-4-337625 (JP, A) JP-A-3-104210 (JP, A) JP-A-62-239520 (JP, A) JP-A-2-76235 (JP, A) JP-A-5-13416 (JP, A A) JP-A-4-340222 (JP, A) JP-A-7-78760 (JP, A) JP-A-7-22618 (JP, A) JP-A-6-97074 (JP, A) JP-A-4 JP-A-92413 (JP, A) JP-A-2-51280 (JP, A) JP-A-63-185015 (JP, A) JP-A-62-122227 (JP, A) JP-A-61-131413 (JP, A) JP-A-60-55614 (JP, A) JP-A-58-37913 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB (Name) H01L 21/265 601 H01L 21/265

Claims (6)

(57) [Claims] 1. After forming a polycrystalline silicon layer on a substrate, when selectively implanting impurity ions into the polycrystalline silicon layer by ion implantation, the ion implantation energy is controlled to control the impurity ions. By setting the implantation depth, a first step of forming an amorphous layer corresponding to the ion implantation depth at least above the polycrystalline silicon layer, and performing a heat treatment to form an amorphous layer below the amorphous layer A second step of crystallizing the amorphous layer corresponding to the thickness of the remaining polycrystalline silicon layer to form a polycrystalline silicon layer having a different crystal grain size from the polycrystalline silicon layer. A method for manufacturing a semiconductor device. 2. A first step of forming a polycrystalline silicon layer on a substrate, and then forming a coating layer selectively covering the polycrystalline silicon layer, and a polycrystalline silicon layer passing through the coating layer by ion implantation. By implanting impurity ions into the polysilicon layer and implanting impurity ions into portions of the polysilicon layer not covered with the coating layer, the first non-crystal layer is formed above the portion of the polysilicon layer covered with the coating layer. Performing a second step of forming a crystalline layer and forming a second amorphous layer thicker than the first amorphous layer on a portion of the polycrystalline silicon layer which is not covered by the coating layer; The first amorphous layer and the second amorphous layer are crystallized to form a first polycrystalline silicon layer on the first amorphous layer side;
Forming a second polycrystalline silicon layer having a larger crystal grain size than the first polycrystalline silicon layer on the side of the amorphous layer. 3. After forming a polycrystalline silicon layer on a semiconductor substrate, when selectively implanting impurity ions into the polycrystalline silicon layer by ion implantation, the ion implantation energy is controlled to control the impurity ions. A first step of forming an amorphous layer corresponding to the ion implantation depth at least above the polycrystalline silicon layer by setting the implantation depth of
Performing a heat treatment, crystallizing the amorphous layer corresponding to the thickness of the polycrystalline silicon layer left below the amorphous layer,
Forming a polycrystalline silicon layer having a different crystal grain size from the polycrystalline silicon layer, and diffusing impurity ions implanted into the polycrystalline silicon layer into a surface layer of the semiconductor substrate to form an impurity diffusion layer A method for manufacturing a semiconductor device, comprising: a second step. 4. The method of manufacturing a semiconductor device as recited in one of claims 1 to 3, the control of the depth t of the amorphous layer formed by the ion implantation, based on the LSS theory Using the projected range Rp of the ion and the projected range dispersion ΔRp, with the ion implantation energy set by the equation t = Rp + κ · ΔRp, 2 ≦ κ ≦ 5. . 5. The method of manufacturing a semiconductor device as recited in one of claims 1 to 4, wherein the ion implantation,
A method for manufacturing a semiconductor device, wherein the method is performed by an oblique ion implantation method in which an incident angle of impurity ions is set to a predetermined angle. 6. The method of manufacturing a semiconductor device as recited in one of claims 1 to 5, in the impurity ions, using at least one or more ions of elements heavier than silicon and silicon A method for manufacturing a semiconductor device, comprising: