JP3297104B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switching system for exchanging information in an asynchronous transmission mode, and more particularly to an ATM switch for guiding a cell to a desired output path.

[0002]

2. Description of the Related Art In recent years, A is being actively developed.
In a TM switching system, a hardware cell switch, that is, an ATM switch, plays an important role as the heart of the system.

Conventionally, various researches and developments have been made on ATM switches. Among such research and development, the banyan ATM switch noted by the present inventor in Japanese Patent Application Laid-Open No. 1-2241242 and the like has only one path from any input port to any output port.
There is an advantage that the amount of calculation required when setting a certain connection is small for the entity that controls the TM switching system (implemented exclusively by a microprocessor).

[0004] However, while maintaining the flexibility of the scale, it is possible to realize the desired scale, and the banyan ATM is used.
Considering the realization of a switch, in order to analyze the routing tag by hardware and transfer the cell to a desired output port, a different identifier for routing is output to each output port of each stage of the banyan ATM switch. I will attach it. As a result, the number of package types inevitably increases, resulting in increased costs.
There was a disadvantage.

[0005] Further, since the ATM switch is a store-and-forward system, a double system is considered and the ATM switch is used at the time of failure or maintenance work.
If the switching operation between the act system and the standby system of the switch is not devised, a large amount of cells will be dropped, which greatly affects the cell transmission quality of the connection set on the ATM switch.

As a solution to this problem, Japanese Patent Publication No.
As disclosed in Japanese Patent No. 16628 and Japanese Patent Application Laid-Open No. 2-246640, information indicating that a cell has been lost in a buffer of an ATM switch has passed for a predetermined period of time, or information indicating that the buffer is empty. It has been conventionally considered that the switching between the act system and the standby system is used to reduce the influence on the set connection. Such a conventional method has no problem at the time of maintenance work in which both the act system and the standby system are operating normally, but some failure occurs, a normal cell is not output, and / or an empty signal is normally output. If the output is not output, the system switching of the ATM switch is not performed as designed, which greatly affects the cell transmission quality of the connection set on the ATM switch.

[0007]

As described above, when the conventional ATM switch is realized while maintaining the flexibility of the scale, the number of package types increases, resulting in an increase in cost. In the case of redundancy, system switching is not performed normally as designed when a failure occurs.
There is a disadvantage that the cell transmission quality of the connection set on the TM switch is greatly affected.

[0008] The present invention has been made to solve such conventional problems, purpose of that, the package type is not increased when realizing while maintaining the flexibility of scale A
To provide a TM switch .

[0009]

To achieve the above Symbol purpose Means for Solving the Problems] The present onset Ming, the cells inputted from a plurality of input ports, ATM switching to a desired output port according to the routing tag with the said cell In the switch,
An input port number that the cell is input, and an output port number for outputting the cell is at least an argument, input port
The specified bit of the output port number is the specified bit of the number.
The exclusive OR of
The feature is to make a bit .

[0010]

[0011]

[Action] In ATM switch according to the present onset bright banyan system, a routing tag and an input port number which the cell is entered, and an argument and an output port number to output the cell, predetermined functions When implementing with multiple boards, the topology tag required in the same stage should be the same by inverting the bit of the routing tag required in each stage by the input port number. Can be. This makes it possible to realize a banyan switch with half the number of board types required conventionally.

[0012]

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an ATM switch according to this embodiment. The figure shows A of each size of 16 × 16, 32 × 32, 64 × 64 with the same architecture.
4 shows a method for implementing a TM switch. In the figure, reference numerals 101, 102,..., 176 (note that the reference numerals of the switches in the figure are 101 at the upper left and 10
106, and 111, 121,... 171 downward from the reference numeral 101, and 176 is at the lower right. All symbols are not shown in the figure. ) Is 8
An ATM switch with eight inputs and eight outputs, for example, having the configuration disclosed by the present inventors in Japanese Patent Application No. 2-144370,
It may be realized by an I1 chip. Thereafter, the 8-input 8-output ATM switch integrated into one chip is replaced with SWL8.
It is described. In the figure, cells are transferred from left to right.
The left side of SWL8 is an input port, and the right side is an output port.

In FIG. 1, a portion (including two substrates) surrounded by a broken-line rectangle corresponds to one substrate. Also, in the figure, four channels (Stage # 0 and Stage # 0)
(during e # 0 ′, between Stage # 3 and Stage # 4)
Or, for 8 channels (Stage # 0 'and Stage # 1)
(Between Stage # 2 and Stage # 3) are described together. Note that Stage # 1 and St # 1
The connection between age # 2 will be described later.

As shown in FIG. 1, the ATM switch of this embodiment is constructed using a 16 × 16 scale ATM switch composed of two sets of substrates.

Stage # 0, Stage # 0 ', and S
Each substrate for the 16 × 16 ATM switch at the position of the age # 3 and the stage # 4 has the SWL8 in the cell transfer direction.
Are arranged in a two-stage configuration, and four of the output ports of the SWL8 of the input-side stage are connected to the input ports of the SWL8 of the output-side stage of the substrate, while the remaining output ports of the input-side stage are connected. 4ch,
The output is performed toward the substrate to be a set, and the remaining input port 4ch of the output side stage is connected to the output from the substrate to be a set. This can be considered as a well-known architecture that takes measures to increase the throughput by increasing the number of internal links (to four) in a delta network.

To obtain a switch of a size larger than 16 × 16, as shown in FIG. 1, the input / output ports of the 16 × 16 ATM switch created as described above are grouped into 2 × 2 switches by 8 channels. It is assumed that they are connected by a banyan network topology. this is,
As is well known, an ATM switch of a banyan network system can be regarded as an architecture in which the number of internal links is increased (to eight) to improve the throughput.

As described above, by combining the two types of architectures, a switch having a scale of 16 × 16 to 64 × 64 can be serialized, and the routing tag can be calculated by a unified algorithm. One of the advantages of this architecture is that the interconnection between the boards is simpler than other architectures such as a cross network, and as a result, the signals transmitted between the boards, and the signal output from one connector is always one. In this case, the workability can be improved.

In FIG. 1, the subdivision by broken lines in the vertical direction corresponds to subrack division. As shown in the figure, at 16 × 16, 2 subrack configuration, 32 ×
At 32, a 4-subrack configuration is used, and at 64 × 64, an 8-subrack configuration is used. Further, the division by the broken line in the left-right direction corresponds to the division of the substrate in the subrack. For convenience of the following description, the slot in which the board of the ATM switch is inserted is called a speech path slot, and a speech path slot number is given to each board as shown in FIG.

In one embodiment of the present invention, a package accommodating an interface point, the interface package is inserted into one subrack, and the substrate inserted into the same subrack among the substrates constituting the ATM switch. It shall be connected to the input port and the output port.

Each SWL8 in the substrate of the ATM switch is given a stage number as shown in FIG.
The stage number designates a predetermined location of the routing tag, which causes the SWL 8 to switch cells.

Here, Stage0 and Stage0 'are routed with reference to the same position of the routing tag. Therefore, the switch at the position of Stage0 'is not actually switched. Therefore, although SWL8 is not theoretically necessary at this position, from the viewpoint of architecture uniformity, here, Stage #
The description proceeds assuming that SWL8 is at the position of 0 '.

The AID shown in FIG.
This is an identifier for identifying the output port of SWL8 located on the output side of 0. Switch size from 16 × 16 to 64
When considering up to x64, AID requires 6 bits. In one embodiment of the present invention, the upper 3 bits are the SWL.
Subrack number of subrack to which 8 belongs, lower 3 bits
Is the output port number of SWL8. Note that A
The input port of the TM switch is the AID attached to the output port used for communication with the same interface board.
It will be identified by the same value as.

The ATM switch of this embodiment has a cell transfer rate in the ATM switch and 1 (which is an extension unit).
By setting the number of inter-stage transfer channels in the 6 × 16 switch as described later, non-blocking can be achieved in the sense of multirate up to 64 × 64 scale. This non-blocking property will be described later.

Further, as will be described in detail later, the routing tag at this time is determined by the AI of the source interface board.
D and the AID of the destination interface board. The ATM switch according to the embodiment of the present invention can reduce the load of the call setting process executed by the control entity of the ATM switch due to these properties.

Next, a method for connecting the substrates in the ATM switch according to the present embodiment will be described in more detail.

When realizing switches of various sizes, the types of boards to be inserted into the communication path slots are different. The switch of 16 × 16 scale is one type of substrate called ASW0, 32 ×
There are 32 types of switches, ASW1 and ASW2, and 6 types.
4 × 64 scale switches are ASW in addition to ASW1 and 2
And three types of substrates. Table 1 shows the types inserted into each communication path slot at each scale.

[0029]

[Table 1] Hereinafter, the inter-substrate connection mode in each size of the ATM switch will be described in more detail.

First, a 16 × 16 ATM switch will be described. FIG. 2 shows a connection form between substrates of a 16 × 16 ATM switch. In this figure, as in FIG. 1, cells flow from left to right. The left side of SWL8 is an input port, and the right side is an output port.

As shown in FIG. 2, the 16 × 16 switch is configured by combining two ASW0 substrates. Two SWLs 8 are used inside the substrate. As described above, the SWL 8 has a function of guiding an input cell to a desired output. The determination of the “desired output” is made by assuming that a part of the routing tag is designated by a stage number given from the outside in a DC manner, and that the output port number is written at the designated position. In order to unify routing tags with switches of other sizes, these L
The SI has a stage # as shown in FIG.

In order to construct a 16 × 16 ATM switch from SWL8, SWL8 belonging to Stage # 3
Of the outputs are SWL8 of Stage # 4 in the board.
S of the board where the output of another 4ch faces the input 4ch of
It is connected to the input 4ch of the switch of the stage # 4. If the connection is made in this way, and the cell transfer rate in the ATM switch is set to twice the transfer rate on the UNI / NNI, and the routing tagging method described later is used, the switch having this topology can perform multi-rate switching. In the sense of non-blocking, that is, the sum of the capacity of the connections set on each input port and each output port is U
When the capacity on the NI / NNI is not exceeded, a connection is not always established in the link inside the ATM switch beyond the transmission capacity of the link. This will be described in detail later.

In this embodiment, the cell transfer rate conversion is performed by an input buffer (not shown) arranged for each input port of Stage # 3 and an output buffer (not shown) arranged for each output port of Stage # 4. ) Are assumed to be the respective functions. Since these input buffers / output buffers do not affect the effectiveness of the present invention at all, it is assumed that the ATM transfer switch of another scale has a cell transfer rate conversion function at the connection point with the interface board. The following description will proceed.

It should be noted that SWL8 is disclosed in Japanese Patent Application No.
In the case of the configuration disclosed in Japanese Patent No. 144370, in the cell transfer between the input buffer, the SWL8 and the output buffer, if the transfer destination buffer is full, the output of the cell is stopped at the transfer source. May be applied. As a result, the buffers distributed and arranged inside the switch network operate cooperatively when collision of cells is avoided, and the cell loss rate under a relatively low load can be greatly improved. Flow control may be introduced in switches of other sizes as well.

Next, a 32 × 32 ATM switch will be described. FIG. 3 shows an inter-substrate connection mode of the 32 × 32 switch. In this figure, as in FIG. 1, the cells flow from left to right. The left side of SWL8 is an input port, and the right side is an output port.

As shown in the figure, the 32 × 32 switch is
16 × 1 composed by combining two ASW1 substrates
6 switches and a 16 × 16 switch configured by combining two ASW2 boards. As for these 16 × 16 switches, 8 channels are collected together in the same subrack and between other subracks in FIG.
Are connected as shown in FIG. S inside each board
Two WL8s are used. In order to ensure the consistency of routing tags with ATM switches of other sizes, these L
The SI has a stage # as shown in FIG.

As described above, a 16 × 16 ATM switch which is non-blocking in the sense of multi-rate is connected by giving all the outputs of the 8 channels of Stage # 0 ′ to the inputs of Stage # 3 as shown in FIG. If the cell transfer rate is set to double and the routing tagging method described later is used, as described in detail later, 32 × 3
Two-scale ATM switches are also non-blocking in the sense of multi-rate.

Next, a 64 × 64 ATM switch will be described. FIG. 4 shows a board-to-board connection mode of the 64 × 64 switch. In this figure, as in FIG. 1, cells flow from left to right. The left side of SWL8 is an input port, and the right side is an output port.

As shown in the figure, a 64 × 64 switch is a 16 × 1 switch formed by combining two ASW1 substrates.
It is configured by combining six switches and a 16 × 16 switch configured by combining two ASW2 substrates by a 16 × 16 switch configured by combining two ASW3 substrates. These 16 × 16 switches are connected to form a Banyan ATM switch as shown in FIG. ASW1 / ASW
The two boards are similar to a 32 × 32 switch. Eight 8 × 8 switch LSIs are used inside the ASW3 substrate, and the cell transfer capacity between adjacent substrates is A using two substrates.
16 × 16 set to 4 times that of using SW1 / ASW2
Configure the switch. In order to unify the switch and the routing tag of other scales, these LSIs are provided with stage numbers as shown in FIG.

As described above, Stage # 1-Stag
The cell transfer capacity between e # 2 is Stage # 0-Stag.
It is set to be four times between e # 0 '/ Stage # 3-Stage # 4. Set the cell transfer capacity in this way,
And, if the cell transfer rate is set to double and the routing tagging method described later is used, as described in detail later,
Non-blocking in the sense of multirate.

Next, a description will be given of a physical connection method between the boards constituting the ATM switch in the embodiment.

The ATM switch is a so-called space division type switch. A large-scale ATM switch is generally obtained by connecting a plurality of unit switches with complicated wiring.
Here, the wiring method between the unit switch and the board becomes complicated,
When the cable is congested, there is a problem that the workability is deteriorated. On the other hand, the number of channels that can be wired on the back panel is limited by the performance of the connector.
In the M switch board, a connector must be placed on the free edge side.

In one embodiment of the present invention, connection between boards may be performed in the following manner so as not to deteriorate workability.

1) The connector on the free edge side is a connection between ATM switch boards inserted into the same slot of the adjacent subrack, that is, Stage # 0-Stage #.
0 ', Stage # 1-Stage # 2, Stage
Used between e # 3 and Stage # 4. This prevents congestion of the cable on the free edge side and enables maintenance from the free edge side.

2) The remaining connections, that is, between the interface board and Stage # 0, Stage # 0'-Stag
e # 1, Stage # 2-Stage # 3, Stage
Ge # 4−Interface boards are wired on the back panel side. Here, Stage # 0'-Stage # 1
And that the connection between Stage # 2 and Stage # 3 is only connection from one substrate to one package (that is, cell flow output from one substrate does not go to multiple substrates). The connection is made using a coaxial connector that provides high throughput.

FIG. 5 is a schematic diagram showing a case where a 32 × 32 scale switch is mounted in accordance with the above-described concept. In the figure, 511 to 514 are ASW1 inserted in the communication channel slot # 1, and 521 to 524 are the communication channel slot # 1.
ASW2 inserted in 0, 531 to 534 are interface boards inserted in each subrack, 541 to 544 are back panels mounted in each subrack, 561 to 56
4 is a wiring on the free edge side of ASW1 / ASW2, 57
1 to 574 are wirings on the back panel connecting the ASW1 and ASW2, and 581 to 588 are wirings on the back panel connecting the ATM switch board and the interface board. As shown in the figure, if implemented according to the above idea, maintenance on the free edge side becomes possible.

Next, a method of assigning a routing tag in the ATM switch according to one embodiment of the present invention will be described.

As described above, in the ATM switch, the communication path to which the cell is guided is specified by the value of the routing tag of an arbitrary cell. In one embodiment of the invention, the cells routed inside the ATM switch are:
Based on the VPI / VCI of the cell, a routing tag according to the connection to which the cell belongs is added to the cell input from the interface point in the interface package. The length of the routing tag does not affect the effectiveness of the present invention in any way, and the description will be made here assuming that the routing tag is 15 bits.

In the ATM switch of this embodiment, the routing tag is calculated from the source and destination AIDs as follows.

As described above, the architecture of the ATM switch is basically a banyan system, but an architecture in which each link inside the banyan has a plurality of links.

Therefore, AID = [｛IR2, IR1, I
R0}, {IS2, IS1, IS0}] (where [{subrack #, ie, upper 3 bits of AID}, {output port number in subrack, ie, lower 3bi of AID]
t｝]) and AID = [｛OR
2, OR1, OR0}, {OS2, OS1, OS0}]
Can be calculated as shown in Tables 2 and 3 from the switch architecture. Table 2 is a table in which a 15-bit routing tag is divided into three bits in order from the head of the cell. Table 3 is a table for explaining specific values of symbols used in Table 2.

[0052]

[Table 2]

[Table 3] The SWL 8 belonging to each stage determines whether Stage # 0 to Stage # according to externally provided stage number information.
4 is selected, and the cell is output to an output port having an output port number corresponding to the number indicated at the position. When this operation is performed by each SWL 8 and each ATM switch board is connected as described above, cells can be guided from any input port to any output port. It is assumed that the SWL 8 belonging to Stage # 0 ′ in the ASW 1 refers to the routing tag at the position of Stage # 0 to determine the output port that outputs the cell.

Next, the fact that the cell can be normally switched by the above-described routing tag will be described in more detail.

In the ATM switch of this embodiment, St
Between stage # 0 and stage # 0 ', stage # 1-S
The connection between Stage # 2 and the connection between Stage # 3 and Stage # 4 is Stage # 0 / Stage # 1 / Stage #.
Among the output ports of SWL8 belonging to ch3, ch0-ch3
And ch4-ch7 are connected together to the SWL8 in the same subrack or in the adjacent subrack, so that "A", "B", and "C" are 16 * 16 switches to 2 * 2 switches. , And corresponds to the routing tag of the 2 × 2/4 × 4/8 × 8 Banyan switch created using the 2 × 2 switch.

The reason why the Ex-OR operation with one bit having the input side subrack number is introduced into the calculation of "A", "B", and "C" is based on the following principle (ch0-ch).
(ch3: output in own board; ch4-ch7: output to adjacent board) only, and in case of a board inserted in an odd slot, the routing tag is appropriately inverted and the routing tag is normally performed, so that This is to reduce the types.

First, a stage for directly receiving cells from the interface board, that is, a Stage # at 16 × 16
3, Stage # 0 at 32 × 32, S at 64 × 64
The stage # 0 will be described.

In these positions, if IR 0 = 1, cells from the interface board are input to the switch board on the odd subrack number side.
In these cases, OR0, OR1, for each OR @ 2, if the bit inversion in the case of an odd number and those taking IR 0 and Ex-OR, well-known Banyan based ATM
The self-routing principle in switches can be used.

Next, Stage # 1 at 64 × 64 will be described with reference to FIG. Note that the reference numerals given to the SWL8 in FIG. 6 match the reference numerals given in FIG.

In this stage, the SWL of the stage # 1 of the switch substrate inserted in the odd subrack number
8 (113, 133, 153, 173) is an interface board inserted in a subrack where IR2 = 1 (that is, subrack # 4 to subrack # 7). Therefore, 64 ×
The "B" bit at 64 o'clock is used for OR1 and IR2 and Ex-
By taking the OR and inverting the bits when IR2 = 1, the well-known principle of self-routing in a banyan ATM switch can be used.

Finally, St at 32 × 32/64 × 64
The age # 3 will be described with reference to FIG. Note that, also in this figure, like FIG. 6, the reference numerals assigned to the SWL8 coincide with the reference numerals assigned in FIG.

In this stage, the SW of Stage # 3 of the switch substrate inserted in the odd subrack number is used.
The interface board that gives traffic to L8 (115, 135, 155, 175) has I as shown in FIG.
This is an interface board inserted in a subrack where R1 = 1. Therefore, the "C" bit at 32.times.32 and 64.times.64 is obtained by taking IR1 and Ex-OR with respect to OR0, and inverting the bit when IR1 = 1, a well-known banyan ATM switch. The self-routing principle can be used.

If this operation is not introduced, ASW0 /
For each substrate of ASW1 / ASW2 / ASW3, (c
It is necessary to define two types: h0-3 jumps to the adjacent subrack and ch4-7 closes in the substrate; and h4-3 jumps to the adjacent subrack and ch0-3 closes in the substrate. It should be noted that there is. Also, IR0 / I
The operation of R1 / IR2 and OR0 / OR1 / OR2 is EX
If the calculation is EX-NOR instead of -OR, (ch0
Note that the present invention can be applied to an ATM switch that defines only a board that is -ch3: output to an adjacent board; ch4-ch7: output to its own board).

Next, the non-blocking property of the ATM switch according to one embodiment of the present invention will be described in detail. As described above, the non-blocking property here means that an ATM switch is always used when the total capacity of connections set on each input port and each output port does not exceed the capacity on the UNI / NNI. In the internal link, no connection is set beyond the transmission capacity of the link, which means non-blocking in the sense of multi-rate here.

First, the non-blocking property of a 16 × 16 ATM switch will be described.

When the routing tag is attached as described above,
( However, E by the bits of the source AID of A, B, C)
x-OR operation is ignored), [｛I
R 0 }, a connection input from {IS2, IS1, IS0} and a connection output from [{OR 0 }, {OS2, OS1, OS0}] pass through a link in the ATM switch as follows. Will be. Here, the link between each stage in the ATM switch has the same
It is assumed that numbers are added by the subrack number and the input port / output port number of the SWL8 belonging to the subrack. The path of the connection shown in Table 4 has a format expressed by each bit constituting the AID of the input port to which the connection is input and the output port AID to be output.

[0066]

[Table 4] Here, the capacity per link is a capacity that is likely to be maximally concentrated when viewed from each of the incoming port and the outgoing port. Since internal speed doubling is assumed, non-blocking is obtained in the sense of multirate if the smaller of the incoming side / outgoing side is 2 or less. When viewed from the input side terminal, if there is one bit different in the binary representation between the input port and the output port of the SWL8 in the path expression,
The value of the capacity per link at the output port 2 at the input port
Double. The capacity per link from the output terminal can be calculated similarly.

The 16 × 16 ATM switch according to the present embodiment is non-blocking because the capacity per link is twice or less.

Next, the non-blocking property of a 32 × 32 ATM switch will be described. As in the case of the 16 × 16 ATM switch described above, the connection route is described in bit expression and the capacity per link is calculated as follows.

That is, when the routing tag is attached as described above (however, the Ex-OR operation by the bits of the source AID of A, B, and C is ignored), the 32 × 32 A
The TM switch [{IR1, IR 0}, {IS2, I
S1, IS0}] and [{OR1, OR0
0}, {OS2, OS1, OS0}].
The link through which the connection passes can be expressed as shown in Table 5,
The capacity per link can be calculated.

[0070]

[Table 5] Like a 16 × 16 ATM switch, the capacity per link is twice or less and non-blocking.

[0071] In addition, in the 64 × 64 scale of the ATM switch, [{IR2, IR1, IR 0}, {IS2, IS
1, IS0}] and [{OR2, OR1,.
OR 0}, is output from the {OS2, OS1, OS0}] . The link through which the connection passes can be expressed as shown in Table 6, and the capacity per link can be calculated.

[0072]

[Table 6] In the above-described capacity per link, the numerical value in parentheses is the capacity that becomes this value when only the number of bit change points is considered. This value is shown in parentheses because it exceeds the traffic amount actually given to the ATM switch.

The ATM switch of 64 × 64 scale also has a capacity per link of twice or less and is non-blocking like ATM switches of other scales.

It should be noted that the above-mentioned property regarding the non-blocking property is satisfied even when the above-mentioned Ex-OR operation is added. This can be explained as follows.

The above discussion of non-blocking properties is based on the AS
In Stages # 0, # 1, and # 3 of W0 / 1/2/3, the substrate (D0-3: output to the adjacent substrate; D4-7: output to the own substrate) and the substrate (D4-7: adjacent Output to board;
D0-3: Define a board which is output in the board itself and
This is a discussion when an M switch is configured.

Here, a comparison between the above discussion on the Ex-OR operation and the discussion on the non-blocking property is as follows.
The bit for performing the Ex-OR operation and the bit for distributing the load among the plurality of inter-stage transmission paths are independent. Therefore, since the Ex-OR operation and the non-blocking property are independent, the property regarding the non-blocking property is satisfied even when the above-described Ex-OR operation is added.

Next, the operation when the ATM switch according to the second embodiment of the present invention is duplicated will be described in detail with reference to the drawings.

FIG. 8 is a diagram showing the relationship between the ATM switch and the interface board when the ATM switch is duplicated. In the figure, reference numeral 811 denotes an ATM switch on the 0-system side, 812 denotes an ATM switch on the 1-system side, 821 denotes an interface board connected to the ATM switch and accommodates an interface point, and 831 denotes an interface point in the interface board. A transmitting side cell processing function for transmitting a cell to the receiving side; 841 is a receiving side cell processing function for receiving a cell from an interface point in the interface board; 851 is a cell flow given to the transmitting side cell processing function; The selector 1 861 for selecting whether the signal from the system 1 or the system 1 is used. The selectors 2 and 871 for selecting whether to use the one from the side are used to assert a flow control signal when the interface board is actually mounted. It is an anti.

In the figure, the cell flow exchanged between the ATM switch and the interface board is indicated by a solid line, and the flow control ready signal exchanged between them is indicated by a dotted line.

The interface board and A in FIG.
It is assumed that a transfer clock and a signal indicating the head of the cell are running in parallel in cell transfer to and from the TM switch. Therefore, the transmitting side cell processing function on the interface board side,
And the input ports of the ATM switch each include a type of cell synchronization mechanism that adjusts the cell phase to its own convenience.

Next, how the system switching is performed in the ATM switching system shown in FIG.

The control entity (not shown) of the ATM switch is:
Whether ATM switch 0 system 811 is act system or 1 system 81
Information indicating whether or not 2 is an act system and an act system instruction are always notified to each interface board.

In each interface board, according to an act-related instruction from the control subject, selectors 1 and 2 are provided as shown in Table 7.
Control the selector 2.

[0084]

[Table 7] The cell flow passed from the receiving-side cell processing function to the ATM switch side is given to both the ATM switch 0 system and the 1 system at the same time. Further, a ready signal relating to cell transfer output from the transmitting side cell processing function is also given to the ATM switch 0 system / 1 system at the same time.

The ATM switch 0 system / 1 system inputs, switches and outputs cells according to a given cell flow and ready signal. To completely synchronize the operation of the ATM switch 0 system / 1 system and give the same cell to the 0 system / 1 system from the corresponding buffer in each system at exactly the same timing, consider the physical size of the ATM switch. And difficult. However, if the selectors 1 and 2 are controlled in accordance with Table 7 and the cell flows from the respective interface boards are simultaneously supplied to the ATM switches of both systems, after a sufficient time has passed, the corresponding ATM switches in the ATM switch 0 system / 1 system are provided. The cells stored in the buffer can be made the same with an error of about one cell.

[0086] The control subject determines that some sort of failure
If found by the M switch, the control subject reverses the act-related instruction. Then, the states of the selectors 1 and 2 on the interface board are inverted according to Table 7. At that time, the cell being transferred from the interface board to the ATM switch or vice versa is A
It is discarded by the input port of the TM switch or the cell synchronization mechanism of the transmission side cell processing function. However, these cell synchronization mechanisms can normally input from the next cell.

Thus, at the time of system switching, one cell may be discarded and / or the same cell may be input, but no more cells are discarded.
Such cell contamination is within the AAL's ability to be considered at present and has no major problems.

When the interface board is not connected to the input / output port of the ATM switch, a resistor 871 is mounted in order to reliably discard the cells transferred to the port. The line may be asserted so that cells are always output from the output port of the ATM switch.

Here, the fault detected by the control entity is, for example, information for managing a cell buffer for temporarily storing cells inside the ATM switch, for example, pointer information for creating a linked list. Rewriting due to a factor may be detected by parity, for example, or may be as follows.

That is, for example, as in the first invention of the present application, the AID of the source interface board and the AID of the destination board
When performing ATM switching by creating a routing tag from the above and adding it to the cell input from the interface point, ATM switching is performed by further adding the destination AID in addition to the routing tag, and the destination A
The ID is monitored on the interface board that has received the cell from the ATM switch. If A assigned to me
When a cell having an AID different from the ID is given from the ATM switch, the control subject is notified that some kind of failure has occurred in the ATM switch.

Further, the fault detected by the control subject may be as follows.

That is, for example, as in the first invention of the present application, the AID of the source interface board and the AID of the destination board
When performing ATM switching by creating a routing tag from the above and adding the cell to the cell input from the interface point, in addition to the routing tag, the source AID
And performs ATM switching by adding a sequence number for each destination AID managed by each interface board,
The source AID and sequence number are monitored on the interface board that has received the cell from the ATM switch. If the sequence number of the cell previously received from the transmission source and the sequence number of the newly received cell are inconsistent, the control unit is notified that some kind of failure has occurred in the ATM switch. However, in this case, it is necessary to ignore the contradiction of the sequence numbers caused by the switching of the switches.

[0093]

As described above, according to the first invention of the present invention, in the banyan ATM switch, the bits of the routing tag required in each stage are
By inverting according to the input port number, it is possible to realize a banyan switch with half the number of board types required conventionally.

[0094]

[Brief description of the drawings]

FIG. 1 is a diagram showing an ATM switch architecture according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a detailed connection of a 16 × 16 ATM switch;

FIG. 3 is a diagram showing a detailed connection of a 32 × 32 ATM switch;

FIG. 4 is a diagram showing a detailed connection of a 64 × 64 ATM switch;

FIG. 5 is a diagram illustrating a method of mounting a 32 × 32 ATM switch;

FIG. 6 is a diagram illustrating a routing tag attaching method.

FIG. 7 is a diagram illustrating a routing tag attaching method.

FIG. 8 is a diagram illustrating an ATM switch switching method according to a second embodiment of the present invention.

[Explanation of symbols]

101, 102, ..., 1768 8-input, 8-output ATM switch 511-514 AS inserted in speech path slot # 1
W1 521 to 524 AS inserted in channel slot # 0
W2 531 to 534 Interface boards 541 to 544 inserted in each subrack Back panels 561 to 564 mounted on each subrack Free-edge side wiring of ASW1 / ASW2 571 to 574 Back panel side connecting ASW1 and ASW2 Wirings 581 to 588 Wiring on the back panel connecting the ATM switch board and the interface board 811 ATM switch on the 10-system side 812 ATM switch on the 1-system side 821 Interface board 831 Cell processing function on the transmitting side 841 Cell processing function on the receiving side 851 Selector 1 861 for selecting cell flow Selector 2 for selecting ready signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/56

Claims (1)

(57) [Claims] 1. An ATM switch for switching a cell input from a plurality of input ports to a desired output port in accordance with a routing tag of the cell, and outputting an input port number to which the cell is input and a cell. Output port number and input port at least
The specified bit of the output port number is the specified bit of the number.
The exclusive OR of
An ATM switch characterized in that it is a bit .