JP3294284B2 - Test method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit tester.
Test method, especially using a conventional tester.
Jig signal propagation delay, signal delay inside LSI under test
Test semiconductor integrated circuits with due consideration for
Preparative about the possible and the method of testing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, a test of a semiconductor integrated circuit includes a test for directly probing a circuit formed on a wafer and a test for packaging a chip cut out from a wafer.

Such a test is divided into a DC characteristic test for determining whether or not the electrical characteristics of the circuit is within an allowable value and a DC function test for determining whether the circuit is functionally normal. Can be divided. The present invention relates to a method of generating a test pattern used for the latter function test.

As a method of creating a function test pattern, there is a method of utilizing a result of a logic simulation performed at the time of logic design of a semiconductor integrated circuit. This method is based on the results of logic simulation,
As a set of the input value and the output value of the signal of the semiconductor integrated circuit,
Each is used as a set of an input value and an expected output value of the function test pattern.

[0005] As this kind of prior art, for example,
The technology described in “LSI technology Corona Co., Ltd., page 192” and the like are known.

[0006]

The prior art described above requires a current tester to respond to recent demands for faster operation cycles of semiconductor integrated circuits for computers (hereinafter referred to as LSIs) and corresponding high-speed tests. To cope with the problem, no consideration is given to the signal propagation delay of the test jig connecting the tester and the LSI under test and the signal delay inside the LSI under test.

For this reason, in the above-mentioned prior art, while a signal is propagated from the tester to the LSI under test and from the LSI under test to the tester, the test cycle of the tester is reduced by the delay of the test jig and the LSI under test. Has progressed several cycles, it is necessary for the tester to hold the expected output value several cycles before the current test cycle and to compare and determine this expected value with the output value of the LSI under test. However, there is a problem that the number of memories for holding the pattern increases. This phenomenon becomes more problematic as the test cycle becomes shorter than the delay time, that is, as the operation cycle of the LSI becomes faster.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of testing a semiconductor integrated circuit capable of solving the problems of the prior art and realizing a high-speed function test using a current tester.
Is to provide a law .

[0009]

According to the present invention, the object is to provide a semiconductor integrated circuit to be tested with each test site.
It consists of the input value of the vehicle and the expected output value for the input value.
A test pattern is generated, and the half of the input value is generated.
The output value of the conductor integrated circuit is generated so that the output value matches the output value.
The semiconductor integrated circuit is compared with the output expected value to be generated.
Test method for semiconductor integrated circuits to test circuits
Therefore, switching from output to input is performed inside the semiconductor integrated circuit.
For the pattern part to be performed, a predetermined
By generating a dummy cycle during the timing
Achieved. In addition, the object is to provide a test jig between the tester and the LSI under test and a test
By comparing the total value of each delay time of I with the test cycle,
A test for a function test in which an expected output value for an input value is shifted backward by an appropriate number of cycles corresponding to the total value of the delay times, and an uncertain value is inserted in a space after the shifted expected output value. This is achieved by converting the pattern in advance.

[0010]

[Function] Switching from output to input inside a semiconductor integrated circuit
For the pattern part to be performed, a predetermined
By generating a dummy cycle during the timing
The signal delay due to the jig is guaranteed and the LSI under test
Function test can be easily performed. Further, the tester, the test fixture and the test LS between the tested LSI
By calculating how many test cycles the total delay time of I corresponds to, and shifting the expected output value backward with respect to the input value by the cycle calculated as described above,
On the tester side, there is no need to hold the test pattern several cycles before, and a memory for that purpose can be eliminated. Further, by inserting an uncertain value into the blank space after the output expected value shift, the comparison determination in the cycle can be stopped.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a method for testing a semiconductor integrated circuit according to the present invention.

FIG. 1 is a diagram showing the relationship between a tester and an LSI under test according to a first embodiment of the present invention, FIG. 2 is a time chart showing the state of input / output signals of the LSI at point A, and FIG. It is a figure explaining pattern conversion. In FIG. 1, reference numeral 1 denotes a tester, and 2 denotes an LSI under test.

In the first embodiment of the present invention shown in FIG. 1, a test signal from a tester 1 is output from a driver DRVT in the tester 1, and is input to an LSI under test 2 via a cable and a test jig. . This test signal is logically converted by a logic circuit in the LSI under test 2 and then output from the driver DRVL. This output signal is returned to the tester 1 via the jig and the cable, and is input to the comparator COMP in the tester 1. Comparator COMP
Compares the input signal with the expected value of the logic result of the logic circuit in the LSI under test 2 with respect to the test signal previously prepared in the tester 1 to check the normality of the function of the LSI 2 to be tested. Output.

In the test of the LSI 2 to be tested as described above, the input signal to the LSI 2 to be tested is a, the output signal is b, and the signals a, b at the connection point A between the cable from the tester 1 and the test jig. 2 is shown in FIG. Normally, among the signal delays from the tester 1 to the LSI under test 2, the cable delay is compensated by the tester, so that the delay visible to the user is the delay due to the jig and the delay inside the LSI.

An input signal a as a test signal and an output signal b as a logic result of a logic circuit in the LSI under test 2 should originally appear in the same test cycle, for example, Ts1, but from FIG. As can be seen, the output signal b
Has been delayed by the jig and the LSI under test 2, and in this example, has reached point A in the next test cycle Ts2. Therefore, when the signal b arrives at the tester 1, the output expected value corresponding to the output signal b does not exist in the tester 1, and the tester 1 cannot compare these signals. This phenomenon is caused by the aforementioned jig delay, L
This is not a problem if the test cycle is sufficiently large compared to the SI delay, but a problem if the test cycle is short.

In the first embodiment of the present invention, in order to solve the above-mentioned problem, as shown in FIG. 3, an output value which is an expected value with respect to an input test pattern signal is previously determined by a predetermined number of test cycles. It is decided to shift backward and insert an uncertain value (X) in the blank after the shift. That is, in the example shown in FIG. 2, the test cycles Ts1 to Ts9
Input signals i1 to i9 of the test pattern in...
Are shifted backward by two test cycles, and the test cycle Ts1,
The uncertain value (X) is inserted in Ts2.

In the above-described example, the output expected value is shifted backward by two test cycles. However, the shift amount may be determined according to the amount of jig delay and LSI delay.

According to the first embodiment of the present invention, by shifting the expected output value within the tester 1 by a predetermined number of test cycles, the signal delay due to the jig is guaranteed. The function test of the LSI under test can be easily performed.

FIG. 4 is a diagram showing a relationship between a tester and an LSI under test according to a second embodiment of the present invention, FIG. 5 is a diagram for explaining signal collision at the time of input / output switching, and FIG. Second
FIG. 6 is a diagram for explaining signal conversion according to the example of FIG. 4 are the same as those in FIG. The second embodiment is an example in which input / output switching is performed inside the LSI under test.

In FIG. 4, 2td is a cable delay,
It shall be equivalent to the sum of jig delay and LSI delay, and
This delay is assumed to be one test cycle time.

[0021] FIG. 5, using a conventional test pattern,
When the output → input switching in the tested LSI is performed, shows a signal time chart in the tester 1 side and the test LSI2 side, the tester 1 via an input line of a dedicated
From the control signals c2 to c input to the LSI under test 2 from
3 is switched to point C in FIG.
In, it is assumed that switching from output to input is performed,
4 is a time chart in which switching from input to output is performed at point B of the tester 1 .

In the time chart shown in FIG .
According to the method according to the first embodiment of the present invention, the output expected value
Are shifted one test cycle backward. Soshi
5, the point shown in FIG.
Before the fixed value signal X, not shown from the driver DRV
The test signals i1 and i2 are output, and the
In the test cycle, the comparator CMP sets the LS under test
A state in which signals output from point C of I can be compared
Is in a state. Output from point C of LSI under test
A signal which is a response of a processing result to the input signals i1 and i2.
o1 and o2 are at the timing shown in the lower part of FIG.
Output from point. On the other hand, the control signal from the dedicated input line
c1, c2,..., c6 are the upper rows of FIG.
Is transmitted to the LSI under test at the timing shown in
You. When the control signal is switched from c2 to c3
In the tester, the point B of the tester is tested by the comparator CMP.
It is possible to compare signals output from point C of LSI.
Driver DRV outputs signal i3
Is switched. As a result, the indeterminate value X
When o1 arrives at the subsequent test cycle, the comparator C
The MP can compare this o1 with the expected value.
However, during the next test cycle,
By switching the control signal from c2 to c3, the driver DR
Since V is switched to output the signal i3,
In the test cycle, the tester
The collision between o2 reaching the point B and the aforementioned i3 occurs, and o2
Can not be compared with the expected value
You. Note that the LSI under test is based on the control signals c2 to c3.
The point C is switched from output to input by switching to
The point C receives i3 to i6 after output of o2.
Can be used.

In the second embodiment of the present invention, in order to solve the above-mentioned problem, as shown in FIG.
Regarding a pattern in which switching from output to input is performed inside I, an uncertain value X ' is inserted so that the input continues the pattern before switching. In the example shown in FIG. 6, Te
The control signal input to the LSI under test 2 from the point A of the star 1
The signal c2 continues for two test cycles, after which c3
Output from the point A of the tester 1 and explained with reference to FIG.
The point that the same switching is performed as in FIG.
It is different from the case. As a result, the point B of the tester 1
During three test cycles in which signal c2 continues,
Is in an operable state and the tester 1
Meanwhile, from the point C of the LSI under test
Signals o1, o2 arriving at a point and their corresponding expectations
A comparison with the value can be made. And in this example,
Uncertain value X 'reaches point B of tester 1 following signal o2
Then, the driver DRV operates at the point B of the tester 1.
As a result, a signal i3 is output.
The point C of SI is the point where the control signal c2 continues for two test cycles.
After switching to c3 later, from tester point B
. Can be accepted.

In the second embodiment described, the delay is
Since the extension is one cycle, the uncertain value X 'is also one cycle.
It only needs to be inserted for the circle, in which case it smells at point B
Therefore, X ′ between the signals o2 and i3 is lost.
You.

According to the second embodiment of the present invention described above,
Even when the input / output switching is performed inside the LSI under test, similarly to the first embodiment, it is possible to guarantee the signal delay by the jig and easily perform the functional test of the LSI under test. it can.

[0026]

As described above, according to the present invention, a high-speed function test close to actual operation can be realized in an existing test environment in a test for selecting good or defective semiconductor integrated circuits.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between a tester and an LSI under test according to a first embodiment of the present invention.

FIG. 2 is a time chart showing states of input / output signals of an LSI at a point A in FIG. 1;

FIG. 3 is a diagram illustrating signal conversion according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between a tester and an LSI under test according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating signal collision at the time of input / output switching.

FIG. 6 is a diagram illustrating signal conversion according to a second embodiment of the present invention.

[Explanation of symbols]

 1 Tester 2 LSI under test

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 21/66

Claims (2)

(57) [Claims] 1. A test pattern including an input value of each test cycle and an expected output value corresponding to the input value is generated for a semiconductor integrated circuit to be tested, and an output value of the semiconductor integrated circuit corresponding to the input value is generated. In a semiconductor integrated circuit test method for testing the semiconductor integrated circuit by comparing the output value with the output expected value generated so that the output value is in phase, switching from output to input inside the semiconductor integrated circuit is performed. A test method for a semiconductor integrated circuit, wherein a dummy cycle is generated for a pattern portion to be performed during a predetermined timing following the input value. 2. A test pattern comprising an input value of each test cycle and an expected output value corresponding to the input value is generated for a test target semiconductor integrated circuit, and an output value of the semiconductor integrated circuit corresponding to the input value and the output value of the test pattern are calculated. In a semiconductor integrated circuit test method for testing the semiconductor integrated circuit using a tester that compares an output expected value, the test pattern is shifted backward by a predetermined timing from an input value corresponding to an output timing of the output expected value. you can, whether in advance conversion in such a way that the test pattern
One, switching to the input from the output within the semiconductor integrated circuit is performed
Dummy cycle for a predetermined period following the input value of the pattern part
A test method for a semiconductor integrated circuit, wherein the test is performed as a test pattern into which a test pattern is inserted .