JP3287038B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to the structure of a driving substrate on which pixel electrodes, thin film transistors, auxiliary capacitors, etc. are formed.

[0002]

2. Description of the Related Art FIG. 10 shows an equivalent circuit of a general active matrix type liquid crystal display device. MOS-FETs are provided at the intersections of m gate lines (G1, G2,... Gm) and n source lines (S1, S2.
Type thin film transistor 101, charge storage capacitor 102 as an auxiliary capacitor, and liquid crystal cell 1 forming a pixel
03 is formed. The active matrix type liquid crystal display having such a structure is driven as follows.
That is, scanning signals whose pulse width is set to one horizontal scanning period are sequentially applied to the gate lines G1, G2,... Gm. During the period in which one gate line is selected, the sampled display signals are sequentially held on the source lines S1, S2,... Sn, and immediately thereafter, the display signals are written to the respective pixels. The display signal written to the pixel is the liquid crystal cell 1
03 and the capacitor 102 hold for one field period, and are rewritten to a signal of the opposite polarity in the next field. Thus, the liquid crystal is AC driven.

The larger the pixel capacitance of each liquid crystal cell 103, the more reliably the pixel potential can be maintained, so that a uniform display quality can be ensured without causing contrast unevenness. Therefore, when the pixel electrode area is large (for example, 200
It is not necessary to provide an auxiliary capacitor in the case of (μm square or more). However, when a pixel is made finer or finer in a small display device, the pixel electrode area is significantly reduced (for example, 100 μm square or less), and an auxiliary capacitance for complementing the pixel capacitance is indispensable.

In general, in order to perform stable sampling and holding of a display signal, the auxiliary capacitance is required to be about five times as large as the pixel capacitance. This auxiliary capacitance generally has a MOS structure and is formed on a substrate plane. In order to secure the required capacity, it is necessary to increase the electrode area,
When the pixel is miniaturized, the ratio of the capacitance electrode increases, and the aperture ratio (the ratio of the pixel area to the display surface) decreases. In particular, when the pixel area is 50 μm square or less, there is a disadvantage that the aperture ratio becomes extremely poor due to the auxiliary capacitance.

As a countermeasure against this, for example, Japanese Patent Laid-Open No.
No. 1262 discloses an improved example using a so-called trench type storage capacitor. This example is first briefly described with reference to FIG. Grooves or trenches 105 are formed on the surface of the quartz substrate 104. On the inner wall of the trench 105, one electrode film 106, a dielectric film 107, and the other electrode film 108 are sequentially laminated to form a so-called trench capacitance element 109. As is clear from the figure, the trench 10
5, a pair of electrode films 106,
The effective area of 108 is increased, and only the capacitance value can be increased without increasing the element size. Therefore, when such a trench-type capacitance element 109 is used, the ratio occupied on the display surface can be reduced, so that a predetermined aperture ratio can be achieved even when the pixel is miniaturized. On the other hand, the thin film transistor 110 is of a planar type and is formed on a silicon polycrystalline thin film 111 constituting a semiconductor region. Two layers of gate insulating films 112 and 1 are formed on the semiconductor region.
13, a gate electrode 114 is formed, and a pixel electrode 116 is electrically connected to a drain region of the thin film transistor 110 via an interlayer insulating film 115.
In the source region of the thin film transistor 110, an electrode 117 connected to each source line is provided. A passivation film 118 is formed on the top of these stacked structures.
Is coated.

[0006]

In the conventional example shown in FIG. 11, the planar size is reduced by making the storage capacitor a trench type, but the thin film transistor is a planar type. If the element area of the transistor can be reduced, the aperture ratio of the pixel can be further improved. In view of this point, the applicant has previously proposed a structure in which a thin film transistor is formed in a trench type in addition to an auxiliary capacitor, and FIG. 12 shows a schematic cross-sectional shape thereof. The structure shown in FIG. 12 does not belong to the prior art, and is shown for reference for understanding the present invention. As illustrated, the thin film transistor 120 is formed using a trench 121.
On the inner wall surface of the trench 121, a first polysilicon layer 122 constituting a semiconductor region, a gate insulating film 123, and a second polysilicon layer 124 constituting a gate electrode are sequentially stacked, and the trench 121 is filled exactly. Has become. A lead electrode 126 is connected to a source region of the thin film transistor 120 via a first interlayer insulating film 125. The extraction electrode 126 is connected to a source line. On the other hand, the pixel electrode 127 is electrically connected to the drain region of the transistor 120 via the first interlayer insulating film 125. The surface of the transistor 120 is covered with a second interlayer insulating film 128.

The storage capacitor 130 also has a trench structure, and a first polysilicon layer 122, a dielectric film or an insulator film 123, and a second polysilicon layer 124 are sequentially deposited on the inner surface of the trench 131. ing. On top of that,
Further, a first interlayer insulating film 125 and a second interlayer insulating film 128
Are superimposed.

As described above, by forming the thin film transistor 120 into a trench structure, the dimensions of the transistor as viewed in plan, particularly the gate length can be reduced. Accordingly, miniaturization of a thin film transistor can be promoted, so that not only a transistor for pixel switching but also a transistor used for a peripheral circuit can be reduced in size, and high integration of a shift register portion and the like can be realized. On the other hand, the effective three-dimensional gate length along the inner wall of the trench can be set to a normal size, so that a normal power supply voltage level can be used. Further, even if the apparent two-dimensional gate length is reduced, the actual three-dimensional gate length can be set to a normal size, so that it is not necessary to take measures for the so-called short channel effect or the like. In addition, since the surface of the trench element is excellent in flatness, a rubbing process for controlling the alignment of liquid crystal molecules can be performed uniformly. Therefore, it is not necessary to particularly shield the region where the trench element is formed with a black mask or the like, and the region can be used as an opening as it is.

FIG. 13 shows an enlarged shape of a trench 121 in which a thin film transistor is formed. Generally, the trench 121 requires a vertical sidewall. The first polysilicon layer 122 is formed so as to continuously cover the surface portion, the side wall portion, and the bottom portion.
Has been deposited. Since the first polysilicon layer 122 is used as a semiconductor region of a transistor, a solid phase growth process for increasing the polysilicon crystal grain size is required. If this solid phase growth process is not performed, the desired current driving characteristics required for the transistor cannot be obtained. For example, Ion / Iof
Variations occur in f characteristics and Vth characteristics. In order to perform solid phase growth, the first polysilicon layer 1 must be
It is necessary to implant Si ⁺ ions into the surface of the substrate 22. However, since this implantation is performed by ion implantation having anisotropy, there is a problem that the polysilicon film adhered to the vertical side wall becomes a shadow portion 141 and uniform solid phase growth cannot be performed. In addition, since the vertical step portion 142 has poor step coverage, there is a problem that the first polysilicon layer is frequently disconnected.

Although the problems to be solved for the thin film transistor having the trench structure have been described above, the problems to be solved for the auxiliary capacitance having the trench structure still remain. The operating characteristics of the pixel switching thin film transistor formed on the insulating substrate are closely related to the corresponding pixel capacitance and auxiliary capacitance. In particular, the frequency dependence of the auxiliary capacitance has a great effect on the writing characteristics of the display signal to the pixel and the signal potential holding ability thereafter. This will be briefly described with reference to FIG. The graph of FIG. 14 shows the pixel potential waveform, and the vertical axis represents the pixel potential V.
And the horizontal axis represents time. In a normal pixel potential waveform, the potential immediately rises with the writing of the display signal, and is held until the next selection time. On the other hand, the pixel potential waveform in the case of using the conventional trench capacitor has insufficient writing, and cannot reach a desired pixel potential. This is mainly due to a decrease in the frequency followability of the trench capacitance. When forming the auxiliary capacitance on the plane of the insulating substrate,
The polycrystalline silicon constituting the lower electrode can be easily recrystallized, and its crystal grain size can be easily increased. Also, the thickness of the polycrystalline silicon can be reduced without considering the step cover. However,
In the case of the trench structure, under the influence of the crystal state and the step cover on the trench wall surface, the carrier mobility of the relevant portion decreases and the resistance value increases. Therefore, in the conventional trench capacitance, the ability of the capacitance to follow the frequency is deteriorated.
Therefore, there is a problem that insufficient writing of the pixel potential occurs, for example, when pixel writing is performed at high speed as shown in FIG.

FIG. 15 is a graph showing the relationship between the trench capacitance value and the carrier mobility of the polycrystalline silicon constituting the lower electrode. The trench capacitance value was measured at a frequency of 10 kHz.
The carrier mobility is the field-effect mobility of electrons and is a value estimated from the corresponding transistor characteristics.
As is clear from this graph, when the electron mobility of polycrystalline silicon is reduced to 20 cm ² / V · sec or less, the film resistance increases and the frequency tracking performance deteriorates. Value cannot be secured.

In order to increase the carrier mobility, it is conceivable that the polycrystalline silicon in the trench is once made amorphous by ion implantation of silicon, and then the grain size is increased by solid phase growth. As the crystal grain size increases, the carrier mobility can be improved accordingly. However, it is difficult and complicated to perform ion implantation on the polycrystalline silicon film deposited on the trench side wall because of oblique incidence. In order to sufficiently perform amorphization, the implantation must be performed while changing the energy of silicon ion implantation a plurality of times. Therefore, a long time is required for the ion implantation process. In addition, crystallization, particularly the reproducibility of the particle size, tends to vary.

[0013]

SUMMARY OF THE INVENTION In view of the above problems,
SUMMARY OF THE INVENTION It is an object of the present invention to provide a trench-structured thin film transistor and an auxiliary capacitor which enable uniform solid phase growth of a polycrystalline silicon thin film and have electrically favorable characteristics. The part mainly related to the thin film transistor among the means taken to achieve the object will be described with reference to FIG. The liquid crystal display device according to the present invention includes a pair of insulating substrates and a liquid crystal layer sandwiched between the insulating substrates. On one insulating substrate 1, pixel electrodes 2 arranged in a matrix, a thin film transistor 3 connected to the pixel electrodes 2, and an auxiliary capacitor 4 for holding charges of the pixel electrodes 2 are formed. I have. Thin film transistor 3
A semiconductor layer 6 formed in contact with the inner wall of the groove 5 having a tapered side surface formed in the insulating substrate 1 and the surface of the insulating substrate 1 ; and a gate insulating film 7 formed on the semiconductor layer.
And a gate electrode 8 formed on the gate insulating film. As is clear from the figure, the semiconductor layer 6,
It has a shape in which the gate insulating film 7 and the gate electrode 8 are buried in the trench 5 until it is substantially flat. The source electrode of the thin film transistor 3 thus formed is connected to a lead electrode 9 connected to a source line or a signal line via a first interlayer insulating film 10. The pixel electrode 2 is obtained by patterning a transparent conductive thin film such as ITO, and is electrically connected to a drain region of the thin film transistor 3. On the extraction electrode 9, a second
The interlayer insulating film 11 is covered.

The shape of the groove 5 or the trench is 0 <
It is set so as to satisfy tan θ ≦ a / 2b. Here, a indicates the groove width of the groove 5, b indicates the depth of the groove 5, and θ indicates the taper angle. In device design, the trench width a and the trench depth b of the trench are designed to desired values in advance. When the taper angle θ of the trench side wall is formed so as to satisfy the above relational expression, the inclined surface can reach the bottom of the groove 5 and does not become a vertical wall. If the above relational expression is not satisfied, the inclined side wall cannot reach the bottom and a groove portion shallower than the designed value is formed, so that the desired gate length cannot be obtained and the expected electrical characteristics of the transistor can be obtained. I can't.

On the other hand, the auxiliary capacitor 4 is made of the same material as the first electrode 13 formed along the inner wall of another groove 12 formed on the insulating substrate 1 at the same time as the groove 5 and the gate insulating film 7 of the thin film transistor. It is formed by the second electrode 15 provided via the formed dielectric film 14. Preferably, the first electrode 13 is formed of a first polysilicon 16 of the same material as the semiconductor layer 6 of the thin film transistor 3, and the second electrode 15 is formed of a second polysilicon 17 of the same material as the gate electrode 8 of the thin film transistor 3. It is formed with. In the example shown in FIG. 1, both the thin film transistor 3 and the auxiliary capacitance 4 have a trench structure. However, the present invention is not limited to this, and only the storage capacitor 4 may be formed in a trench having a tapered shape. Conversely, the thin film transistor 3 may be formed in the groove 5 having a tapered shape.

Next, a part mainly related to the auxiliary capacity of the means taken to achieve the object of the present invention will be described with reference to FIG. Insulating substrate 6 made of quartz or the like
A trench or groove 62 is formed in the surface of the substrate 1. The storage capacitor 63 is provided in the groove 62 and has a trench structure. The storage capacitor 63 includes a first electrode layer 64, a dielectric film 65, and a second electrode layer 66.
The first electrode layer 64 is formed between the inner wall of the groove 62 and the insulating substrate 61.
It is made of a polycrystalline semiconductor such as polysilicon formed in contact with the surface . The dielectric film 65 has the same structure as a gate insulating film used for a thin film transistor (not shown) formed on the same substrate, and is made of SiO2 / Si3N4 / Si.
It has a three-layer structure of O2. The second electrode layer 66 is also made of polysilicon or the like and is buried in the groove 62. In addition,
On the second electrode layer 66, a first interlayer insulating film 67 and a second
An interlayer insulating film 68 is formed to overlap. As a feature of the present invention, the minimum grain size of the polycrystalline semiconductor constituting the first electrode layer is set to be larger than its film thickness.
Preferably, the polycrystalline semiconductor is obtained by increasing the diameter of an amorphous semiconductor formed by chemical vapor deposition by solid phase growth.

FIG. 17 is a schematic sectional view showing a state in which a planar type pixel switching thin film transistor 71 is formed on the same substrate in addition to the trench type auxiliary capacitance 63 shown in FIG. The thin film transistor 71 is an insulating substrate 6
1, a polycrystalline semiconductor layer 72 to be an active region, a gate insulating film 73 formed on the polycrystalline semiconductor layer 72, and a gate electrode 74 formed on the gate insulating film 73. It is composed of The polycrystalline semiconductor layer 72 serving as an active region is the first region forming the storage capacitor described above.
Of the same material and thickness as the electrode layer 64 of FIG. The gate insulating film 73 is formed of the same material as the above-described dielectric film 65 and has a three-layer structure. Further, the gate electrode 74
Are formed of the same material as the second electrode layer 66 constituting the storage capacitor. Preferably, the polycrystalline semiconductor layer 72 serving as an active region of the thin film transistor 71 is once made amorphous by ion implantation, and is grown by solid phase. A pixel electrode 75 made of a transparent conductive film such as ITO is electrically connected to a drain region of the thin film transistor 71 through a contact hole opened through the first interlayer insulating film 67 and the second interlayer insulating film 68. Thin film transistor 71
A wiring pattern 76 made of metal aluminum or the like is electrically connected to the source region through a contact hole opened through the first interlayer insulating film 67. Further, a passivation film 77 made of P-SiN is formed on the second interlayer insulating film 68 by patterning.

[0018]

Next, with reference to FIG. 2, a part of the operation of the present invention mainly relating to the trench type thin film transistor shown in FIG. 1 will be described in detail. As described above, the groove 5 having a tapered shape or a substantially V shape is formed on the surface of the insulating substrate 1.
Is formed, and a first polysilicon 16 is deposited on the surface thereof. Since the first polysilicon 16 becomes a semiconductor layer of the thin film transistor, a solid phase growth process is required. In the solid phase growth process, first, Si ⁺ ion particles are ion-implanted to reduce the crystal grain size of the first polysilicon 16 once, and then heat treatment or annealing is performed to recrystallize the crystal to increase the crystal grain size. It is. As the crystal grain size increases, the charge mobility and the like of the semiconductor layer are improved, and characteristics closer to a single crystal thin film can be obtained. Since the angle of incidence of the ion implantation is perpendicular to the substrate surface, uniform implantation cannot be achieved if a shadow is formed. In particular, ion implantation used in the manufacturing process of a thin film transistor has a short injection distance. Therefore, when performing Si ⁺ ion implantation, the first polysilicon 16 needs to be exposed on the entire surface. That is, it is necessary to set the trench shape so that the shadow of the first polysilicon 16 does not occur when observed from the upper surface of the substrate. For this reason, in the present invention, the groove 5 is tapered.
This taper is formed along the longitudinal direction of the gate wiring. In the case of an auxiliary capacitor, it is formed along the longitudinal direction of the wiring connected to the auxiliary capacitor. By adopting such a tapered structure, the shadow of the trench portion at the time of Si ⁺ ion implantation can be reduced, and the semiconductor layer 6 or the first electrode 13 made of the first polysilicon having a uniform crystal structure along the inner wall of the trench (FIG. 1) can be formed.

Next, the operation of the present invention will be described mainly with reference to FIG.
The portion related to the trench type auxiliary capacitance shown in FIG. 17 will be described in detail. As described above, in the present invention, the polysilicon used below the trench capacitance is recrystallized to form a film such that the crystal grain size in the polysilicon becomes larger than the thickness of the polysilicon itself. The carrier mobility is increased by the recrystallization, so that the resistance at the side wall of the trench is prevented from increasing, and the frequency tracking property is improved. With such a structure, the trench-type storage capacitor can sufficiently follow the selection operation speed of the pixel switching thin film transistor, and can prevent insufficient writing unlike the conventional case.

According to the present invention, by making the crystal grain size of polysilicon larger than its thickness, the resistance is reduced and the frequency followability of the trench type auxiliary capacitance is improved.
Therefore, it is not necessary to increase the film thickness of the polysilicon in order to reduce the resistance. As shown in FIG. 17, the polysilicon used as the lower electrode 64 of the trench-type auxiliary capacitance is formed at the same time as the active region of the planar thin-film transistor 71. It can also be used for the polycrystalline semiconductor layer 72 to be formed. Therefore, the manufacturing process of the driving substrate for the active matrix type liquid crystal display device can be simplified. If the thickness of the polysilicon film is increased, the number of moving carriers increases and the resistance can be reduced. In this case, however, the lower electrode 64 of the trench type auxiliary capacitor and the activation of the pixel switching planar thin film transistor 71 are activated. The polycrystalline semiconductor layer 72 constituting the region cannot be shared. In this case, the number of steps for forming the driving substrate increases. A structure that separates the active region of the thin film transistor from the trench-type auxiliary capacitor is also conceivable. However, a contact hole for connecting the auxiliary capacitor portion and the transistor portion is required. Therefore, a layout for an additional contact hole is required in the pixel. Becomes In this structure, the aperture ratio of the active matrix type liquid crystal display device is ultimately sacrificed.

The operation of the present invention described above will be further described below with specific data. FIG. 18 is a graph showing the relationship between the auxiliary capacitance value and the frequency, in which the characteristic curve according to the present invention is compared with the characteristic curve according to the conventional method. This characteristic curve is a measured value when the bias voltage is set to 10V. Regarding the auxiliary capacitance of the trench structure formed according to the present invention, the thickness of the polysilicon forming the lower electrode is set to 95 nm, and the grain size is about 500 nm. On the other hand, the lower electrode film thickness of the trench type auxiliary capacitor formed according to the conventional method is also 95 nm.
And the polysilicon particle size is 50 nm. Polysilicon having a particle size of about 50 nm is in a substantially as-deposited state, and the mobility of the polysilicon on the side wall of the trench is 1 cm ² / V · sec or less. For this reason, in the range of 10 kHz or more, the frequency tracking ability is extremely deteriorated due to the increase in the resistance component. On the other hand, according to the present invention, solid-phase growth is performed on the polysilicon constituting the lower electrode.
When grown to a crystal grain size of about 00 nm, 100
Electron mobility of about cm ² / V · sec is obtained. The actual charge transfer is approximately proportional to the electron mobility.
It is possible to respond to high frequency twice or more.

FIG. 19 is a graph showing the relationship between the storage capacitance value and the thickness of the polysilicon forming the lower electrode of the trench storage capacitor. 500nm grain size of polysilicon
And the case of 40 nm. When the particle size is 500 nm, the thickness of the polysilicon film is 100 nm.
Even below, the resistance value does not decrease and the frequency tracking performance does not deteriorate, so that the desired auxiliary capacitance value can be maintained. Therefore, FIG.
As shown in FIG. 7, the polysilicon film can be used for both the lower electrode of the trench type auxiliary capacitance and the active region of the planar type thin film transistor. On the other hand, when the grain size is 40 nm, when the thickness of the polysilicon film is set to 100 nm or less, the frequency followability is deteriorated with the increase in the resistance value, and the auxiliary capacitance value is extremely reduced.

FIG. 20 schematically shows a difference in electron mobility depending on a crystal grain size in polysilicon. (A) shows the case where the crystal grain size is smaller than the polysilicon film thickness, and (B) shows the case where the crystal grain size is larger than the polysilicon film thickness. Each of them shows a crystal state in a trench sidewall portion where an auxiliary capacitance is formed. For easy understanding, the portions corresponding to the trench-type auxiliary capacitors shown in FIG. 16 are denoted by the corresponding reference numerals. As shown in (A), when the crystal grain size of the polysilicon forming the lower electrode 64 is smaller than the film thickness, the moving direction of the electrons traveling through the polysilicon film is scattered due to the random arrangement of the crystal grain boundaries 78. receive. The conduction state of a semiconductor is determined mainly by the number of carriers present in the conduction band and the valence band and their mobilities.
Therefore, an electron scattering factor typified by the crystal grain boundary 78 that hinders this lowers the conductivity. On the other hand, as shown in FIG. 3B, in the present invention, the direction of the crystal grain boundary 78 is perpendicular to the insulating substrate 61 in order to reduce the crystal grain boundary disorder existing in the polysilicon and to suppress electron scattering as much as possible. By forming, the scattering direction of the crystal grain boundary 78 can be made uniform. In order to achieve this, it is necessary to increase the crystal grain size with respect to the thickness of the polysilicon to be the lower electrode 64.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the substrate for driving a liquid crystal display device according to the present invention will be described below in detail with reference to the process charts of FIGS. First, FIG. 3 is a process chart showing the formation of the groove and the formation of the first polysilicon. In this example, a quartz substrate 31 is prepared as an insulating substrate. After applying a photoresist film on the surface of the quartz substrate 31 and performing exposure and development processing and patterning, wet etching is performed using a 1: 6 solution of HF and NH ₄ F to form a groove 32 having shallow but substantially vertical walls. Form. Next, plasma dry etching is performed using a 95: 5 mixed gas of CF ₄ and O ₂ as a reaction gas to form a groove 33 having a substantially tapered shape. Unlike isotropic wet etching, plasma dry etching has anisotropy. Therefore, by appropriately setting various parameters such as acceleration energy of plasma particles and vapor pressure of a reaction gas, a groove having a desired tapered shape is obtained. 33 are obtained. In this example, the trench is formed by combining wet etching and dry etching. However, in some cases, in the case of a quartz substrate, a tapered shape can be formed only by dry etching. Next, a first polysilicon layer 34 is deposited on the entire surface of the quartz substrate 31. Deposition is performed to a film thickness of 80 nm using low-pressure chemical vapor deposition (LPCVD). By this processing, the first polysilicon layer 34 can be formed with a substantially uniform film thickness not only on the substrate surface but also on the inner wall of the groove 33. Subsequently, Si ⁺ ions are implanted by ion implantation to perform a solid phase growth process of the first polysilicon layer 34.
For example, at an acceleration energy of 30 keV, the dose is 1 × 1
Set to 0 ¹⁵ pieces / cm ² . Alternatively, the acceleration energy of Si ⁺ ions may be set to 50 keV. By this implantation process, the first polysilicon having an average crystal grain size of 10 nm to 50 nm is miniaturized and once approaches an amorphous state. Next, recrystallization is caused by performing heat treatment or annealing at about 620 ° C. for a certain period of time.
A film having an average crystal grain size of about 0 nm is obtained. Since this film has a crystal structure close to that of a single crystal, a thin film transistor having excellent electric characteristics can be manufactured. what if,
Unless the solid phase growth process is performed, the deterioration of the transistor frequency characteristics cannot be avoided. Finally, the first polysilicon layer 34
Is patterned into a predetermined shape, and the semiconductor layer 35 of the thin film transistor and the first electrode 36 of the storage capacitor are simultaneously formed in the corresponding groove 33.

Next, a step of forming a gate insulating film will be described with reference to FIG. First, the surface of the first polysilicon layer 34 is thermally oxidized to form a SiO 2 film having a thickness of about 50 nm.
_{2 A} thermal oxide film 37 is formed. Next, after a region where a transistor is to be formed is partially covered with a photoresist 38, arsenic cation particles are ion-implanted into the exposed region. The condition at this time is, for example, acceleration energy 30 ke
In V, the dose is 5 × 10 ¹⁴ / cm ² . This ion implantation lowers the resistance of the first electrode 36 that forms the auxiliary capacitance. This ion implantation is performed via the thermal oxide film 37. Next, after removing the resist 38, the thermal oxide film 37 is removed.
A silicon nitride film having a thickness of about 30 nm is deposited on the surface of the substrate by LPCVD. This silicon nitride film is further thermally oxidized to form a thermal oxide film of about 2 nm on its surface. Thus, a gate insulating film 39 having a three-layer structure is formed. With a three-layer structure, pressure resistance is improved.

Next, the formation of the gate electrode of the transistor and the second electrode of the auxiliary capacitor will be described with reference to FIG. L
A second polysilicon layer having a thickness of about 350 nm is deposited on the gate insulating film 39 by using the PCVD method. On this, phosphorus-doped glass (not shown) (PS
Deposit the film of G). Subsequently, heat treatment is performed to diffuse phosphorus in the PSG into the second polysilicon layer 40 to reduce the resistance. After the PSG is removed, the second polysilicon layer 40 is patterned using a photoresist film to form a gate electrode 41 and a second electrode 42 having a predetermined shape.
These electrodes are embedded in the grooves 33, respectively. Therefore, the surface of the groove can be processed substantially flat. This patterning is performed by plasma etching using a 95: 5 mixed gas of CF ₄ and O ₂ as a reaction gas. The gate electrode 41 is connected to a gate line or a scanning line through the groove 33. On the other hand, the second electrode 42 is also connected to a predetermined common line through the groove 33.
By the above processing, the first electrode 36 is provided in the groove 33 on the right side.
A trench type auxiliary capacitor 56 including the dielectric film or the insulating film 34 and the second electrode 42 can be formed. Since it is a trench type, it has an electrode area larger than an apparent plane area and has an increased capacitance. Further, since the trench has a tapered shape, it has a structure in which a disconnection failure or the like at a stepped portion is unlikely to occur. On the other hand, the semiconductor layer 35,
A basic structure of a transistor including the gate insulating film 34 and the gate electrode 41 is formed. Similarly, because of the trench structure, the apparent two-dimensional channel length can be made shorter than the actual three-dimensional channel length, miniaturization of the transistor can be achieved, and the semiconductor layer 35 is formed along the tapered surface. There is little fear of step breakage. In addition, since the semiconductor layer 35 was almost completely exposed at first in plan view, the implantation of Si ⁺ ions in the solid phase growth process could be performed substantially uniformly as described above.

Next, a process for forming a source and a drain region of a thin film transistor will be described with reference to FIG. First, after covering the upper portion of the left groove 33 with a resist 43, arsenic cation particles are ion-implanted to form a lightly doped drain region (LDD). The implantation conditions at this time were set to an acceleration energy of 160 keV and a dose of 1 × 1.
Set to 0 ¹³ / cm ² . The so-called LDD structure aims at preventing the short channel effect. In this example, since the transistor has a trench structure, a sufficient channel length can be secured, and it is not always necessary to adopt the LDD structure.
Subsequently, after masking the groove 33 with a resist film 44 having a larger dimension than the above-described resist film 43,
Arsenic cations are implanted to form N-channel source and drain regions. The ion implantation conditions at this time are set to an acceleration energy of 140 keV and a dose of 2 × 10 ¹⁵
Set to / cm ^2. The N-channel type MOS-FET transistor thus created is used for driving a pixel. On the other hand, since a CMOS structure is often used in peripheral circuits such as a scanning circuit and a driving circuit, it is necessary to create a P-channel MOS-FET. In this case, boron cation particles are ion-implanted into the flat portion of the semiconductor layer 34 through the resist 45 to form a source region S and a drain region D doped with a P-type impurity at a high concentration. The ion implantation conditions at this time were such that the acceleration energy was set to 30 keV and the dose was set to 2 × 10 ¹⁵ / cm ² .

Next, the wiring process will be described with reference to FIG.
First, a first interlayer insulating film 46 made of PSG is deposited on the flattened insulating film 39 by using the LPCVD method. The first interlayer insulating film 46 is selectively etched to form a first contact hole 47. This process is based on HF and NH
_This is performed by wet etching using a mixed solution of 4F. Next, an aluminum thin film or an amorphous silicon thin film 48 serving as a wiring is deposited to a thickness of about 600 nm by sputtering. At this time, the deposited film fills the contact hole 47 and conducts to the source region S of the thin film transistor 49. Finally, a two-to-one ratio of H ₃ PO ₄ and H ₂ O
The wiring 50 is formed by selectively etching the aluminum thin film or the amorphous silicon thin film 48 by using the mixed solution 0 and performing electrode patterning. The wiring 50 is connected to a source line or a signal line.

Next, the hydrogen diffusion process for the first polysilicon layer 34 will be described with reference to FIG. First, a second interlayer insulating film 51 is formed on the first interlayer insulating film 46. This film is formed by depositing PSG by an LPCVD method.
Subsequently, a silicon nitride film 52 serving as a hydrogen diffusion source is formed on the second interlayer insulating film 51. This nitride film 52 is formed to a thickness of 400 nm by physical vapor deposition (PCVD) and contains about 20% of hydrogen atoms. 4 in this state
When annealing or heat treatment at 00 ° C. is performed, hydrogen atoms pass through the second interlayer insulating film 51, the first interlayer insulating film 46, and the gate insulating film 39 and are combined with traps included in the first polysilicon film 34. As a result, the charge mobility of the first polysilicon film 34 is further improved. At the stage when the hydrogen diffusion process is completed, the silicon nitride film
2 is completely removed.

Finally, a process for forming a pixel electrode will be described with reference to FIG. The second interlayer insulating film 51 and the first interlayer insulating film 4 using dry etching and / or wet etching.
6 and the gate insulating film 39 are partially removed to form a second contact hole 53. The hole 53 communicates with the drain region D of the thin film transistor 49. Dry etching is, for example, 95: 5 of CF ₄ / O ₂
It can be performed by plasma etching using a mixed gas. In the case of wet etching, HF and NH ₄ F
Is used. On the second interlayer insulating film 51, the IT
An O film 54 is formed. For example, at a film forming temperature of 400 ° C., 14
The thickness is about 0 nm. At this time, the second contact hole 53 is filled with the ITO film 54 to establish electrical conduction. Finally, the pixel electrode 55 which is patterned on the ITO film 54 and is electrically connected to the drain region D of the thin film transistor 49
Is formed. This patterning is performed, for example, with HCl / H ₂
This is performed by wet etching using a 300: 300: 50 mixed solution of O / NO ₃ .

Next, a second embodiment of the substrate for driving a liquid crystal display device according to the present invention will be described in detail with reference to FIGS. First, in step A of FIG. 21, a quartz substrate 201 is prepared. In step B, the quartz substrate 201
A trench 202 is formed on the surface of the substrate. This trench 20
2 has a predetermined taper and can be processed in the same manner as in the first embodiment described above. In step C, the quartz substrate 20
The first polysilicon 203 is formed on the entire surface of the first polysilicon layer 203. L
The thickness is about 200 nm using the PCVD method. However, in this embodiment, the film is formed at a temperature of 600 ° C. or less, and is substantially amorphous silicon. In step D, solid phase growth is performed by a predetermined annealing process to convert amorphous silicon to polycrystalline silicon. As a result, even within trench 202, the crystal of polysilicon 203 has a large grain size, and its size is sufficiently larger than the film thickness. Also, polysilicon 2
The plane portion 03 is made amorphous by implantation of Si ⁺ ions, and the polysilicon 203 having extremely excellent characteristics can be obtained by solid-phase growth of the amorphous portion. In step E, the first polysilicon 203 is patterned into a predetermined shape. As a result, the first electrode 204 of the storage capacitor is formed in the trench 202, and the polycrystalline semiconductor layer or the active region 205 of the thin film transistor is formed in the flat portion.

In step F of FIG. 22, the surface of the polysilicon is oxidized to form a gate insulating film 206 made of SiO ₂ . In step G, As ⁺ ions are implanted to form the first electrode 2
04 low resistance. S by CVD in step H
A gate insulating film 207 made of i ₃ N ₄ is deposited. Further, the gate insulating film 207 is oxidized by a thermal oxidation method to form a gate insulating film 208 made of SiO _{2 having} a thin surface. Thus, the gate insulating films 206, 207, 2
08 resulting in a three-layer structure 209. In step I, a second polysilicon 210 is entirely deposited by LPCVD. Further, the resistance is reduced by phosphorus diffusion. In step J, the second polysilicon is patterned by dry etching, and the second electrode 21 is
1 and a gate electrode 212 is formed on the active region 205. By this step, the trench 202
Inside, an auxiliary capacitance 213 composed of a first electrode 204, a dielectric film having a three-layer structure 209, and a second electrode 211 is obtained.

In step K of FIG. 23, the three-layer structure 209 of the gate insulating film is partially removed by dry etching. In step L, an N-type impurity is selectively ion-implanted to form an LDD region and an N ⁺ region in the active region 205, so that a thin film transistor 214 is obtained. This impurity ion implantation step is the same as in the first embodiment. In step M, a first interlayer insulating film 215 made of PSG is deposited. In step N, a contact hole 216 is opened in the first interlayer insulating film 215 by wet etching to expose the source region S of the thin film transistor 214. Process O
, Metal aluminum 217 is entirely deposited to fill contact holes 216.

In step P of FIG. 24, metal aluminum 217 is patterned into a predetermined shape to obtain wiring 218.
In step Q, a second interlayer insulating film 219 made of PSG is deposited by LPCVD. In step R, the second interlayer insulating film 219 and the first interlayer insulating film 215 are etched to form a contact hole 220,
The fourteen drain regions D are exposed. IT in process S
After a transparent conductive film made of O is formed by sputtering, patterning is performed by wet etching to obtain a pixel electrode 221 having a predetermined shape. The pixel electrode 221 is electrically connected to the drain region D of the thin film transistor 214 via the above-described contact hole.

In step T of FIG. 25, a P-SiN film 222 is deposited by a plasma CVD method. In step U, the P-SiN film 222 is patterned into a predetermined shape. A hydrogenation process is performed using the patterned P-SiN film 222. Finally, in step V, the opposing substrate 224 is attached so as to face the quartz substrate 201. A common electrode 225 is previously formed on the inner surface side of the counter substrate 224. The liquid crystal 2 is placed between the substrates 201 and 224
26 are filled and filled to complete an active matrix type liquid crystal display device.

[0036]

As described above, according to the first aspect of the present invention, a thin film transistor and / or an auxiliary capacitor are formed in a trench having a tapered shape. As the first step,
A first polysilicon film forming a semiconductor layer of the transistor and an electrode film of the storage capacitor is deposited along the tapered surface.
Since the first polysilicon film is almost completely exposed along the tapered surface when performing the solid phase diffusion processing of this film, Si ⁺
Ions can be implanted uniformly. Therefore, the solid-phase diffusion process can be performed uniformly, and a semiconductor layer having a composition similar to that of the silicon single crystal can be obtained even at the side wall of the trench, so that the electrical characteristics of the transistor and / or the auxiliary capacitor can be improved.
In addition, since the first polysilicon film is formed along the tapered surface, there is an effect that the step coverage is improved and a failure such as a step break can be effectively prevented.

According to the second aspect of the present invention, the polycrystalline semiconductor forming the first electrode of the trench-type storage capacitor includes a crystal grain having a size larger than its thickness. For this reason, the carrier mobility of the polycrystalline semiconductor increases, and the trench-type auxiliary capacitance can follow up to a high-frequency band, and sufficiently functions for high-frequency driving accompanying the high definition of the active matrix liquid crystal display device. There is an effect that can be exhibited. In addition, the thickness of the polycrystalline semiconductor can be reduced by an amount corresponding to the improved carrier mobility and can be shared with an active region of a thin film transistor formed on the same substrate, which leads to an effect of reducing the number of steps. Further, there is an effect that the step in the trench can be reduced by reducing the thickness of the polycrystalline semiconductor. In addition, particularly by increasing the crystal grain size of the polycrystalline semiconductor by solid phase growth of the amorphous semiconductor Si ⁺
Since there is no need to rely on ion implantation, the number of implantations can be reduced and the process can be shortened.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a basic configuration of a driving substrate used in a liquid crystal display device according to the present invention.

FIG. 2 is a schematic diagram for explaining the operation of the present invention.

FIG. 3 is a process diagram showing a process of forming a tapered trench and a first polysilicon film of a driving substrate.

FIG. 4 is also a process view showing a step of forming a gate insulating film.

FIG. 5 is a process chart showing a film formation and patterning step of a second polysilicon film.

FIG. 6 is a process chart showing a step of forming a source region and a drain region of the thin film transistor.

FIG. 7 is also a process view showing a step of forming wiring electrodes.

FIG. 8 is a process chart showing a hydrogen diffusion process for the first polysilicon film.

FIG. 9 is a process view showing a step of forming a pixel electrode.

FIG. 10 is a circuit diagram showing a general equivalent circuit of an active matrix type liquid crystal display device.

FIG. 11 is a schematic view showing a cross-sectional structure of a conventional driving substrate.

FIG. 12 is a reference diagram illustrating a cross-sectional shape of a driving substrate having a trench thin film transistor and a trench storage capacitor.

FIG. 13 is a schematic diagram for explaining a problem of the reference example shown in FIG. 12;

FIG. 14 is a graph showing a pixel potential waveform of an active matrix liquid crystal display device.

FIG. 15 is a graph showing a relationship between a trench capacitance value and a carrier mobility of polysilicon forming a lower electrode of an auxiliary capacitance.

FIG. 16 is a partially enlarged cross-sectional view showing a basic configuration of a trench storage capacitor according to the present invention.

FIG. 17 is a cross-sectional view showing another basic configuration of a driving substrate used in the liquid crystal display device according to the present invention.

FIG. 18 is a graph showing a relationship between a capacitance value of a trench-type auxiliary capacitance and a frequency.

FIG. 19 is a graph showing a relationship between a capacitance value of a trench type auxiliary capacitance and a film thickness of polysilicon forming a lower electrode of the trench type auxiliary capacitance.

FIG. 20 is a schematic diagram showing a crystal state of a lower electrode on a trench side wall.

21 is a process chart showing a manufacturing process of the drive substrate for the active matrix liquid crystal display device shown in FIG.

FIG. 22 is a manufacturing process drawing.

FIG. 23 is a manufacturing process drawing.

FIG. 24 is a manufacturing process drawing.

FIG. 25 is a manufacturing process view.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Pixel electrode 3 Thin film transistor 4 Auxiliary capacitance 5 Groove 6 Semiconductor layer 7 Gate insulating film 8 Gate electrode 12 Groove 13 First electrode 14 Dielectric film 15 Second electrode 16 First polysilicon 17 Second polysilicon 61 Insulating substrate 62 Trench 63 Auxiliary capacitance 64 First electrode 65 Dielectric film 66 Second electrode 71 Thin film transistor 72 Active region 73 Gate insulating film 74 Gate electrode 75 Pixel electrode

Claims (9)

(57) [Claims] 1. A pair of insulating substrates, a liquid crystal layer sandwiched between the insulating substrates, a pixel electrode arranged in a matrix on one of the insulating substrates, and a thin film transistor connected to the pixel electrode And a storage capacitor for holding an electric charge of the pixel electrode,
The thin film transistor is in contact with the inner wall of the groove having a tapered side surface formed on the insulating substrate and the surface of the insulating substrate.
A semiconductor layer formed Te, a liquid crystal display device comprising a gate insulating film formed on the semiconductor layer, that consists of a gate electrode formed on the gate insulating film. 2. A storage device comprising: a first electrode formed along an inner wall of another groove formed on an insulating substrate simultaneously with the groove; and a dielectric formed of the same material as a gate insulating film of the thin film transistor. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed by a second electrode provided via a film. Wherein the first electrode is formed in the semiconductor layer of the same material of the thin film transistor, according to claim 2, wherein the liquid crystal of said second electrode, characterized in that it is formed of the same material as the gate electrode of the thin film transistor Display device. 4. A pair of insulating substrates and a space between these insulating substrates.
The sandwiched liquid crystal layer and a mask are formed on one of the insulating substrates.
The pixel electrodes arranged in a trix shape and the
Connected to the thin film transistor and the charge of the pixel electrode.
In a liquid crystal display device having an auxiliary capacitor for holding
The thin film transistor has a side surface formed on an insulating substrate.
Semiconductor layer formed along inner wall of tapered groove
And a gate insulating film formed on the semiconductor layer,
A liquid comprising a gate electrode formed on a gate insulating film, wherein the shape of the groove satisfies the following equation:
Crystal display device. 0 <tan θ ≦ a / 2b (however,
The groove width is a, the depth is b, and the taper angle is θ. ) 5. A pair of insulating substrates, a liquid crystal layer sandwiched between the insulating substrates, a pixel electrode arranged in a matrix on one of the insulating substrates, and a thin film transistor connected to the pixel electrode And a storage capacitor for holding an electric charge of the pixel electrode,
The auxiliary capacitance includes an inner wall of a groove having a tapered side surface formed on the insulating substrate, a first electrode layer formed in contact with a surface of the insulating substrate, and a dielectric layer formed on the first electrode layer. film and, the dielectric Ri Do and a second electrode layer formed on the film, the liquid crystal display device wherein the first electrode layer, characterized in that ing polycrystalline semiconductor. 6. A pair of insulating substrates, a liquid crystal layer sandwiched between the insulating substrates, pixel electrodes arranged in a matrix on one of the insulating substrates, and a thin film transistor connected to the pixel electrodes And a storage capacitor for holding an electric charge of the pixel electrode,
A first electrode layer made of a polycrystalline semiconductor formed along an inner wall of a groove provided in the insulating substrate;
A dielectric film formed on the first electrode layer, and a second electrode layer formed on the dielectric film;
A liquid crystal display device characterized in that the minimum grain size of the polycrystalline semiconductor is larger than its film thickness. 7. The liquid crystal display device according to claim 6, wherein the polycrystalline semiconductor is obtained by increasing the grain size of an amorphous semiconductor formed by chemical vapor deposition by solid phase growth. . 8. The thin film transistor includes a polycrystalline semiconductor layer formed on a plane of an insulating substrate, a gate insulating film formed on the polycrystalline semiconductor layer, and a gate electrode formed on the gate insulating film. Wherein the polycrystalline semiconductor layer is formed of the same material and thickness as the first electrode layer, the gate insulating film is formed of the same material as the dielectric film, and the gate electrode is formed of the second electrode. 7. The liquid crystal display device according to claim 6, wherein the liquid crystal display device is formed of the same material as the layer. 9. The liquid crystal display device according to claim 8, wherein the polycrystalline semiconductor layer of the thin film transistor is made amorphous once by ion implantation, and is grown in a solid phase.