JP3276282B2 - Absolute phase detector and digital modulation wave demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute phase detector and a digital modulation wave demodulator capable of stably detecting the absolute phase of a multilevel phase modulation wave or a multilevel phase amplitude modulation wave.

[Summary of the Invention] The present invention relates to the improvement of stability when the absolute phase of a multilevel phase modulation wave or a multilevel phase amplitude modulation wave is detected by a fixed synchronization pattern with a small number of signal points. By averaging the signal point positions of the obtained synchronization pattern at symbol timing intervals or performing low-pass filtering on the signal point positions, the absolute phase detection can be stably performed even at low C / N where the demodulated signal point positions are spread. It is something that can be done.

[0003] Here, the absolute phase detection means detecting a correct received signal point by detecting a phase error of a signal point to be demodulated. That is, when synchronously detecting a phase-modulated signal, it is necessary to know the frequency and phase of the unmodulated carrier before modulation. However, when reproducing the unmodulated carrier on the demodulation side, it is generally difficult to reproduce the carrier having the same phase, and the signal point to be demodulated is, for example, Q
In the case of PSK, a phase error occurs that is an integral multiple of π / 2.
Absolute phase detection is performed to detect this phase error and obtain a correct received signal point.

[0004]

2. Description of the Related Art As is well known, in digital phase amplitude modulation, data transmission is performed by changing the phase and amplitude of a carrier at equal intervals, that is, at symbol timing intervals.

For example, in BPSK (two-phase shift keying), the phase is changed to 45 degrees or 225 degrees without changing the amplitude, and one symbol is assigned to the phase. In this case, since the phase takes only two values, 1
One bit data can be transmitted by a symbol.

In QPSK (four-phase shift keying), data transmission is performed using four phases of 45 degrees, 135 degrees, 225 degrees, and 315 degrees. This QPSK
In this case, since the phase can take four values, 2-bit data transmission is possible with one symbol.

FIG. 9 shows an example of a QPSK modulated wave.
FIG. 10 shows the signal point arrangement of K and QPSK. Note that the signal point is a value that the phase and amplitude of the modulated wave can take on an orthogonal plane.

[0008] In addition to the above, 8PSK (8-phase shift keying), 16PSK (16-level phase shift keying) and the like are known as the multi-level phase modulation that changes only the phase without changing the amplitude.

Further, there is also multi-level phase amplitude modulation in which the number of bits that can be transmitted in one symbol is further increased by changing not only the phase but also the amplitude. For example, there is 16 QAM (16-level quadrature amplitude modulation). ), 64QAM
(64-level quadrature amplitude modulation). FIG. 11 shows these signal point arrangements. FIG. 12 shows the phase relationship between the modulated wave and the demodulated wave.
Shown in

FIG. 13 shows an example of a conventional absolute phase detection circuit. A conventional method for detecting the absolute phase of QPSK from a time-divided BPSK synchronization pattern will be described with reference to FIG.

Here, it is assumed that the carrier reproduction system of the demodulator 101 performs QPSK, and as shown in FIG. 14, data is QPSK and a synchronization signal is time-division multiplexed by BPSK and transmitted.

The demodulated I and Q signals output a positive value (+) when "1" and a negative value (-) when "0" at the eye opening point. I do.

Now, as the synchronization pattern, {00010011010
11110} by BPSK, the phase uncertainty of π / 2 × n occurs in the I signal and the Q signal.
Any of the four patterns (1) to (2) is output as an I signal and a Q signal of the demodulator 101. Where + is a positive value,-
Indicates a negative value.

Pattern (1) I: {--- +-++-+-++++-} Q: {--- +-++-+-++++-} Pattern (2 ) I: {+++-++-+-+ ---- +} Q: {--- +-++-+-++++-} Pattern (3) I: {++ +-++-+-+ ---- +} Q: {+++-++-+-+ ---- +} Pattern (4) I: {--- +-++ -+-++++-} Q: {+++-++-+-+ ---- +} Therefore, as an I signal or a Q signal, {+++-++-+-+
---- +}, or {--- +-++-+-++++-},
Since it is known that synchronization has been acquired, for example, if the first symbol at this time is {I, Q} = {−, −}, the phase error is 0 {I, Q} = {+, −}. For example, if the phase error is π / 2 {I, Q} = {+, +}, the phase error is 3π / 2 if π {I, Q} = {−, +}. I understand.

Using this information, it is possible to make a symbol decision with phase uncertainty removed.

[0016]

However, in a poor reception environment in which the C / N is degraded due to non-linearity or rain on the satellite transmission line, the reception signal points are spread as shown in FIG. When a modulation scheme with a large number of signal point arrangements is used, the probability of being erroneously determined to be an adjacent symbol area increases, making it difficult to detect a synchronization pattern.

Therefore, by using only the modulation scheme of the synchronization pattern portion as a modulation wave having a smaller number of signal points than that of the data transmission portion, a region for one symbol is widened and the probability of occurrence of an error between adjacent symbols is reduced. Can be considered.
For example, when 8PSK modulation is used for data transmission and BPSK is used for a synchronization part, synchronization detection at the time of demodulation becomes easy even in a poor transmission state.

However, when trying to correct the phase uncertainty of n × π / 4 (n: integer) of 8PSK from the demodulation phase information of the BPSK synchronization signal, the demodulation signal point of the synchronization signal portion is shown in FIG. When the signal is spread by π / 8 or more as described above, the phase is corrected to the phase adjacent to the original phase, and a correct received symbol may not be obtained.

The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to stably detect correct phase information from a synchronization pattern extracted from a demodulated signal in which the above-described deterioration has occurred. To provide an absolute phase detector and a digitally modulated wave demodulator.

[0020]

[0021]

In order to achieve the above object, a first aspect of the present invention provides a multi-valued data signal comprising a multiplexed synchronizing signal portion having a smaller number of signal points than that of a data signal portion. When demodulating a phase-modulated wave or a multi-level phase-amplitude-modulated wave, a detector for detecting the absolute phase of the demodulated signal inputs the I signal and the Q signal demodulated by the demodulator and executes a tentative determination process of a received symbol. A tentative determination unit for
A synchronization pattern capturing unit that performs a capturing process of a synchronization pattern provisionally determined by the temporary determination unit to generate a frame synchronization signal, and inputs an I signal, a Q signal demodulated by the demodulator, and the frame synchronization signal. A received signal averaging unit that performs a process of averaging received signal points at symbol timing intervals only for the time of the synchronization pattern, and which synchronization pattern is determined based on the averaged signal output from the received signal averaging unit. A synchronization determination unit that determines whether the phase is locked;
And a received symbol hard decision section for determining a received symbol from which phase uncertainty has been removed using the phase information of the synchronization decision section.

According to a second aspect of the present invention, a multi-level phase modulation wave or a multi-level phase amplitude modulation wave obtained by multiplexing a synchronization signal portion having a smaller number of signal points than the data signal portion into the data signal portion is demodulated. At this time, a detector that detects the absolute phase extracts a signal point position of only a “0” symbol or only a “1” symbol from a synchronization signal portion in the demodulated baseband signal and performs a filtering operation. A low-pass filter, and an absolute phase detecting means for detecting an absolute phase of the synchronization signal based on the signal filtered by the low-pass filter.

According to a third aspect of the present invention, there is provided a digitally modulated wave demodulator including the absolute phase detector according to the first or second aspect.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

<Principle of the Present Invention> FIG. 1 shows a basic configuration of a multilevel phase amplitude modulated wave demodulator as a digital modulated wave demodulator according to the present invention.

According to the present invention, by averaging the received signal points for the synchronization signal portion, the S / N is equivalently improved for the synchronization signal portion, and it is possible to stably determine which phase is locked. It can be detected in any way. For example, when a signal transmitted using 8PSK modulation for data transmission and a signal transmitted using BPSK for a synchronization signal portion is demodulated, the synchronization signal portion is averaged as shown in FIG. 2 to obtain a correct received symbol. Can be.

For this purpose, as shown in FIG. 1, the demodulator according to the present invention comprises a demodulator 1, a received symbol tentative decision unit 3, a synchronization pattern capturing unit 5, and a reception signal averaging unit for a synchronization signal portion. It has a basic configuration including a conversion unit 7, a synchronization pattern synchronization detection unit, and a received symbol hard decision unit 11.

The tentative decision unit 3 receives the I signal and the Q signal demodulated by the demodulator 1 and performs a tentative decision process on the received symbol. A capture process is performed to generate a frame synchronization signal. On the other hand, the reception signal averaging unit 7 receives the I signal and the Q signal demodulated by the demodulator 1 and the frame synchronization signal, and averages the reception signal points at symbol timing intervals only for the time of the synchronization pattern. Execute The synchronization detector 9 determines at which phase the synchronization pattern is locked based on the averaged signal. The received symbol hard decision unit 11 uses the phase information to determine a received symbol from which phase uncertainty has been removed.

The demodulation device shown in FIG.
As shown in (1), the signal transmitted by time division multiplex hierarchy is demodulated. In this time division multiplex layer transmission, data 1 is 8P
An SK signal, a QPSK signal as data 2, a BPSK signal as data 3, and a BPSK signal as a synchronization signal are time-division multiplexed. The multiplexed signal is orthogonally modulated via an orthogonal modulator and transmitted as a hierarchical modulation wave. in this case,
Each signal of data 1 to data 3 is compressed on the time axis. In particular, since the synchronization signal is most important, it is a BPSK modulated wave that is resistant to deterioration of the transmission environment.

When demodulating the modulated wave generated as described above, first, the modulated wave is treated as 8PSK and carrier reproduction and symbol timing reproduction are performed to obtain a received signal point. Further, it is necessary to detect the synchronization signal at the head of the signal and correct the phase uncertainty of the reproduced carrier before extracting the received symbol.

First, in the absolute phase detection using the synchronizing signal, the synchronizing signal that has been demodulated by 8PSK is BPSK-modulated, and may be demodulated in eight phases as shown in FIG. In FIG. 4, the arrow in the figure indicates the locus of movement of the received signal point when the transmitted synchronization signal changes from 0 to 1. It is good if demodulation can be performed at "0" in the figure, but otherwise, it is necessary to correct the phase.

For example, FIG. 6 shows the relationship between the modulation phase and the demodulation phase at each signal point of BPSK, QPSK, and 8PSK. As shown in FIG. Thus, it can be understood that the phase on the demodulation side is shifted by +90 degrees.

In the present invention, this phase correction is stably performed, and a specific example of the device configuration shown in FIG. 5 will be described below.

<Example of Specific Apparatus Configuration> The circuit shown in FIG. 5 captures a BPSK synchronization pattern from a demodulated received signal point arrangement and determines a received symbol at a correct phase. And the demapping ROM 23
, Eight 16-bit shift registers 25, an OR gate circuit 27, two latch circuits 29, 29 ', an averaging circuit 31, a synchronous phase detection circuit 33, an 8PSK symbol determination circuit 35, and a QPSK. Symbol judgment circuit 37
And a BPSK symbol determination circuit 39 and two parallel / serial conversion circuits 41 and 43.

The demapping ROM 23 stores eight phase angles (0 deg, 45 deg, 90 deg, 1 deg) as shown in FIG.
A phase pattern corresponding to 35 °, 180 °, 225 °, 270 °, and 315 °) is stored. A synchronous signal portion demodulated by the quadrature demodulator 21 is input, and one of the patterns corresponding to the input synchronous signal is 8 Corresponding to one selected from two phase patterns
The data is output to the 6-bit shift register 25.

The 16-bit shift register group 25 is composed of eight 16-bit shift registers corresponding to the eight phase patterns supplied from the demapping ROM 23. It is generated and supplied to the OR gate circuit.

The OR gate circuit 27 is an 8-input OR circuit, and generates a frame synchronization signal when a signal indicating that synchronization has been captured by any of the eight shift registers 25 is output. The synchronization signal is supplied to each latch circuit 2.
9, 29 ', each D flip-flop 43, and each 16 counter 47.

The two latch circuits 29 and 29 'are circuits for latching the I and Q coordinates of the last symbol of the synchronization signal portion among the demodulated signal points by the frame synchronization signal.

The averaging circuit 31 is a circuit for executing processing for averaging the received signal points at symbol timing intervals only for the time of the synchronization pattern, and for each of the I and Q signals, a D flip-flop (D- FF) 45
, A full adder 47 and a 16 counter 49.

The D flip-flop 45 includes a full adder 47
And a cumulative adder circuit, which inputs and holds the 10-bit signal supplied from the full adder 47, and resets the processing of outputting the previously input 10-bit signal to the full adder 47 from the 16 counter 49. The cumulative addition is repeatedly performed until the signal is supplied.

The full adder 47 is a two-input full adder of 10 bits and 6 bits, and converts a 6-bit signal supplied from the latch circuit 29 and a 10-bit signal supplied from the D flip-flop 45. In addition to the addition, a process of supplying the upper 10 bits of the added 16-bit signal to the D flip-flop 45 is executed. When the cumulative addition for 16 symbol sections is completed, the lower 4 bits of the cumulative result are discarded, and 6-bit cumulative data is output to the synchronous phase detection circuit 33.

The 16 counter 49 is composed of a 4-bit counter and counts the frame synchronization signal output from the OR gate circuit 25. When the frame synchronization signal has been counted 16 times, a reset signal is generated. Output to the D flip-flop 45.

The synchronization phase detection circuit 33 is a circuit for determining at which phase the synchronization pattern is locked based on the averaged signal. The synchronization signal (3 bits of phase information) is used as an 8PSK symbol determination circuit 35 and QPSK. Output to the symbol determination circuit 37 and the BPSK symbol determination circuit 39.

The 8PSK symbol determination circuit 35 receives the I signal and the Q signal demodulated by the quadrature demodulator 21 and the determination signal from the synchronous phase detection circuit 33, and receives an 8PSK portion (corresponding to data 1 in FIG. 3). Of the received symbol is determined. The QPSK symbol determination circuit 37 receives the I signal and the Q signal demodulated by the quadrature demodulator 21 and the determination signal from the synchronous phase detection circuit 33, and outputs a QPSK portion (corresponding to data 2 in FIG. 3). The received symbol is determined. Further, the BPSK symbol determination circuit 39 receives the I signal and Q demodulated by the quadrature demodulator 21 and the determination signal from the synchronous phase detection circuit 33, and receives the BPSK portion (FIG. 3).
(Corresponding to the data 3 in FIG. 3).

The parallel / serial conversion circuit 41 converts the 8PSK symbol supplied from the 8PSK symbol determination circuit 35 into a serial signal and outputs it. Further, the parallel / serial conversion circuit 43 converts the QPSK symbol supplied from the QPSK symbol determination circuit 37 into a serial signal and outputs the serial signal.

Here, the demapping ROMs 23 and 16
A bit shift register 25, an OR gate circuit 27,
The latch circuit 29, the averaging circuit 31, and the synchronous phase detection circuit 33 constitute an absolute phase detection circuit according to the present invention. The demodulator 21, the absolute phase detection circuit, the 8PSK symbol determination circuit 35, and the QPSK symbol determination A digital modulation wave demodulator according to the present invention is composed of a symbol determination circuit including a circuit 37 and a BPSK symbol determination circuit 39, and two parallel / serial conversion circuits 41 and 43. Note that the quadrature demodulator 21 corresponds to the demodulator 1 in FIG.
The demapping ROM 23 corresponds to the received symbol provisional determination section 3 in FIG. 1, the 16-bit shift register 25 and the OR gate circuit 27 correspond to the synchronous pattern capturing section 5 in FIG. 1, and the averaging circuit 31 corresponds to FIG. Corresponding to the received signal point averaging unit 7, the synchronization phase detection circuit 33 corresponds to the synchronization detection unit 9,
The 8PSK symbol determination circuit 35, the QPSK symbol determination circuit 37, and the BPSK symbol determination circuit 39
Of the received symbol hard decision section 11.

In the configuration shown in FIG. 5, when the I signal and the Q signal are output from the quadrature demodulator 21, synchronization detection is first performed using the demapping ROM 23 for all eight phase angles. Here, {0001001101011110} is taken as an example of the synchronization pattern to be detected.

When synchronization is achieved with any of the patterns for the eight phase angles stored in the demapping ROM 23, a frame synchronization signal is generated from the OR gate circuit 27.

At this time, when the C / N is good, three of the eight gate outputs output signals that are stably acquired synchronously, but when the C / N is deteriorated, the signals are output. Two become particularly unstable. Therefore, when synchronization signals at equal intervals are detected from at least one of the eight gate outputs, it is regarded that synchronization has been acquired, and a frame synchronization signal is generated. The generated frame synchronization signal is supplied to the latch circuit 29, the D flip-flop 45, and the 16 counter 49, respectively.

When the synchronizing signal is detected, the OR gate circuit 27
When the frame synchronization signal is supplied from, for the 16 symbols of the synchronization symbol section, the 10-symbol D flip-flop 43 and the 10-bit and 6-bit 2-input full adders 47 are used for the 16 symbol sections. Perform cumulative addition. An operation of dividing the lower 4 bits by 16 is performed on the accumulated result.

The 16 counter 49 counts the number of times the frame synchronization signal is output. When the frame synchronization signal is output 16 times, a reset signal is generated and supplied to the reset terminal of the D flip-flop 45, whereby the cumulative addition is performed. Is reset.

When the averaging signal in the 16 symbol section is generated after the accumulation is completed, the averaging signal is output to the synchronous phase detection circuit 33.

The synchronization phase detection circuit 33 determines at which phase the synchronization pattern is locked based on the averaged signal, and outputs the determination signal to the 8PSK symbol determination circuit 35, Q
The signal is output to the PSK symbol determination circuit 37 and the BPSK symbol determination circuit 39 so that symbol determination can be performed stably.

FIG. 8 shows another embodiment of the present invention. In this embodiment, a filter circuit 51 is used in place of the averaging circuit 31 shown in FIG. 5
Is the same as that shown in FIG.

This filter circuit 51 has two digital low-pass filters (LPF) 53, 53 '. The LPF 53 receives the 6-bit signal from the latch circuit 29 and the frame synchronization signal from the OR gate circuit 27. Similarly, the LPF 53 ′ receives the 6-bit signal from the latch circuit 29 ′ and the frame signal from the OR gate circuit 27. A synchronization signal is input, and the signal after low-pass filtering is output to the synchronization phase detection circuit 33.

In the above-described embodiment, the S / N of the synchronization signal portion is equivalently improved by averaging a plurality of symbols of the synchronization signal portion. However, in this embodiment, the S / N of the synchronization signal portion is improved. Take out only the symbol and B
The signal point positions of only the "0" symbol or only the "1" symbol of the PSK are taken out and subjected to low-pass filtering by the LPFs 53 and 53 '. Thus, the same effect as that of the embodiment shown in FIG. 5 can be obtained with a simple circuit configuration.

The filter circuit 51 has a digital L
Although it can be easily configured by using the PFs 53 and 53 ', if a D / A converter and an A / D converter are provided before and after the filter, an analog filter can also be configured. In short, if only the DC component of the signal point can be extracted, the effect of improving the S / N of the synchronization signal portion can be expected.

[0057]

As described above, according to the present invention, when the absolute phase of a multilevel phase modulation wave or a multilevel phase amplitude modulation wave is detected by a fixed synchronization pattern with a small number of signal points, demodulation is performed. It is possible to stably detect the absolute phase even at the time of low C / N where the signal point positions are spread.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a multilevel phase amplitude modulation wave demodulation device as a digital modulation wave demodulation device according to the present invention.

FIG. 2 is an explanatory diagram of the principle of the present invention showing a state in which a synchronization signal portion is averaged.

FIG. 3 is an explanatory diagram showing the principle of time division multiplex hierarchical transmission to be demodulated by a multilevel phase amplitude modulated wave demodulation device.

FIG. 4 is an explanatory diagram showing a synchronization phase of a BPSK modulation wave demodulated by 8PSK.

FIG. 5 is a block diagram showing a specific configuration of a multilevel phase amplitude modulation wave demodulation device as a digital modulation wave demodulation device according to the present invention.

FIG. 6 is an explanatory diagram showing a relationship between a modulation phase and a demodulation phase.

FIG. 7: BPSK demapping R corresponding to eight phases
FIG. 4 is an explanatory diagram showing the contents of an OM.

FIG. 8 is a block diagram showing another specific configuration of a multilevel phase amplitude modulation wave demodulation device as a digital modulation wave demodulation device according to the present invention.

FIG. 9 is an explanatory diagram showing an example of a QPSK modulated wave.

FIG. 10 is an explanatory diagram showing a signal point arrangement of BPSK and QPSK.

FIG. 11 is an explanatory diagram showing a signal point arrangement of 16QAM and 64QAM.

FIG. 12 is an explanatory diagram showing a phase relationship between a modulated wave and a demodulated wave.

FIG. 13 is a block diagram showing a configuration of a conventional absolute phase detection circuit using a synchronization pattern.

FIG. 14 is an explanatory diagram showing a configuration of a data format.

FIG. 15 is an explanatory diagram showing spreading of received signal points.

FIG. 16 is an explanatory diagram showing a case where a BPSK signal that is a synchronization signal crosses an 8PSK determination boundary line.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 demodulator 3 reception symbol provisional decision unit 5 synchronization pattern capture unit 7 reception signal point averaging unit 9 synchronization detection unit 11 reception symbol hard decision unit 21 quadrature demodulator 23 demapping ROM 25 16 bit shift register 27 OR gate circuit 29 latch Circuit 31 Averaging circuit 33 Synchronous phase detection circuit 35 8PSK symbol determination circuit 37 QPSK symbol determination circuit 39 BPSK symbol determination circuit 41, 43 Parallel / serial conversion circuit 45 D flip-flop 47 Full adder 49 16 counter 51 Filter circuit 53, 53 '' Digital low pass filter (LPF)

Continuation of the front page (56) References JP-A-6-120995 (JP, A) JP-A-2-278940 (JP, A) JP-A-7-87149 (JP, A) JP-A-5-48665 (JP) , A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38 H04L 7/00

Claims (3)

(57) [Claims] When demodulating a multi-level phase modulation wave or a multi-level phase amplitude modulation wave obtained by multiplexing a synchronization signal part having a smaller number of signal points than a signal point number of a data signal part on the data signal part, A detector for detecting a phase, which receives an I signal and a Q signal demodulated by a demodulator and performs a tentative determination process on a received symbol, and captures a synchronization pattern tentatively determined by the tentative determination unit A synchronization pattern capturing unit for executing processing and generating a frame synchronization signal; inputting the I signal, Q signal demodulated by the demodulator and the frame synchronization signal, and receiving only at a timing of a symbol pattern at a synchronization pattern time. A received signal averaging unit that executes a process of averaging the signal points, and at which phase the synchronization pattern locks based on the averaged signal output from the received signal averaging unit. An absolute phase detection, comprising: a synchronization determination unit for determining whether a received symbol has a phase uncertainty removed by using phase information of the synchronization determination unit; vessel. 2. A multi-level phase-modulated wave or a multi-level phase-amplitude modulated wave obtained by multiplexing a synchronization signal part having a smaller number of signal points than a signal point number of a data signal part on the data signal part. A low-pass filter for detecting a phase, extracting a signal point position of only a "0" symbol or only a "1" symbol from a synchronization signal portion in the demodulated baseband signal and performing a filtering operation; And an absolute phase detector for detecting an absolute phase of the synchronization signal based on the signal filtered by the low-pass filter. 3. A digital modulation wave demodulator comprising the absolute phase detector according to claim 1.