JP3274963B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element and a metal lead frame are sealed with a sealing resin, and more particularly to a semiconductor element excellent in reliability without deterioration of characteristics of the semiconductor element.

[0002]

2. Description of the Related Art 80 of a package for mounting a semiconductor element.
% Or more is a resin-sealed type, that is, a semiconductor element is resin-sealed together with a metal lead frame, and the resin sealing is generally performed at a temperature of about 180 ° C. Mechanical residual stress is generated in the semiconductor element in accordance with the difference in thermal expansion coefficient of the semiconductor element.

[0003] With the advance of high integration of semiconductor devices (hereinafter sometimes simply referred to as "devices"), miniaturization is being advanced in thin film processing technology at the time of manufacturing semiconductor devices. The demand for improvement cannot be kept up, and the dimensions of highly integrated semiconductor elements tend to increase. Since the dimensions of the package are determined by the standard, if the device becomes larger with higher integration,
This will increase the stress generated in the device. An increase in stress generated in a semiconductor element leads to a defect that the element is broken in the worst case. Even when the element does not crack, the circuit characteristics of the semiconductor element, such as the resistance value of the resistor, the capacitance of the capacitor, and the amplification characteristic of the transistor, fluctuate depending on the mechanical stress (strain). Would. Further, an element in which a ferroelectric thin film is formed as a main material of a nonvolatile memory element is expected. In such an element, when remanent polarization occurs due to application of a predetermined electric field used for data storage, the crystal is formed. Since the generated strain is utilized, if an unnecessary external stress (strain) is applied, the above-mentioned polarization state, and thus the stored data may be changed, and the reliability of the product is reduced. Can have a significant effect.

[0004] Therefore, in order to prevent fluctuations in the circuit characteristics of the element, the stress generated in the semiconductor element due to the resin sealing must be minimized. As a conventional technique for reducing the stress generated in such an element, for example, as disclosed in JP-A-55-88357, after a coating material having a low elastic modulus is applied to one side of a semiconductor element, There is a method in which resin sealing is performed, and a method in which the entire element is covered with a gel resin as disclosed in JP-A-57-100752. In these conventional techniques, the stress applied to the element is reduced by a coating material having a low elastic modulus or a gel resin.

[0005]

SUMMARY OF THE INVENTION The above-mentioned JP-A-55-88 has been disclosed.
As in the prior art described in JP-A-357-357, when a coating material having a low elasticity is applied to one side of a semiconductor element and resin sealing is performed, the stress generated in the semiconductor element is not necessarily reduced. is there. This is because there is no consideration for the adhesive layer joining the semiconductor element and the lead frame, so even if the stress generated by the low elastic modulus coating material is reduced on the resin sealing side of the semiconductor element,
This is because stress is generated on the opposite surface mainly due to a difference in thermal expansion coefficient from the metal lead frame.

As described above, even if a coating material having a low modulus of elasticity is applied to one side of the semiconductor element, the stress generated in the semiconductor element due to the resin sealing cannot always be reduced, and the circuit characteristics vary. (Deterioration), which may reduce the reliability of the product. In particular, in the case of a non-volatile memory element formed with a ferroelectric thin film, as described above, it is considered that the sensitivity of the stress to the fluctuation of the circuit characteristics is high. As a result, the reliability of the product is significantly reduced.

Also, in the case of the prior art described in Japanese Patent Application Laid-Open No. 57-100752, there is no consideration for an adhesive layer with a metal lead frame. There is a concern that the reliability of the device will decrease. Furthermore, in this case, since the entire semiconductor element is covered with a soft gel, the state before resin sealing is not fixed but loose, so that assembly of the package becomes very difficult,
In addition, since the gel shrinks significantly in the cooling process after resin sealing, a space is created at the boundary with the surrounding resin, which leads to cracking of the gel itself. For this reason, this structure is very difficult to realize.

An object of the present invention is to provide a semiconductor device which can reduce stress applied to a semiconductor element at the time of sealing with a resin, can avoid fluctuation and deterioration of circuit characteristics, and can obtain high reliability.

[0009]

As described above, when a material having a low elastic modulus is arranged only on the surface of the semiconductor element on the resin sealing side, the stress generated on that surface is reduced. Since the metal lead frame (or resin depending on the package structure of the semiconductor device) exists on the side surface, a stress is generated due to a difference in thermal expansion coefficient therefrom.
This causes a change or deterioration of circuit characteristics and a decrease in product reliability.

On the other hand, according to the present invention, in a semiconductor device in which a semiconductor element and a metal lead frame are sealed with a sealing resin, the elastic modulus of the sealing resin is provided on both surfaces of the semiconductor element. There is provided a semiconductor device in which a stress absorbing layer made of a lower material is disposed.

As described above, according to the present invention, by disposing a stress absorbing layer having an elastic modulus lower than that of the resin on both surfaces of the semiconductor element, not only the surface of the element on the resin sealing side but also the opposite side thereof. That is, the thermal strain is absorbed by the low-modulus stress-absorbing layer also on the surface on the side of the metal lead frame (or resin depending on the package structure of the semiconductor device), and the generation of stress is reduced. As a result, the stress applied to the entire element is greatly reduced, and fluctuation and deterioration of circuit characteristics are prevented, and reliability is improved. Conversely, even if a material having a low elastic modulus is arranged only on the surface on the side of the metal lead frame (resin depending on the package structure of the semiconductor device), the stress generated in the semiconductor element cannot be reduced. Depending on the case, the stress may increase. Therefore, it is necessary to dispose a stress absorption layer having a low elastic modulus on both surfaces of the semiconductor element.

Further, depending on the package structure of the semiconductor device, a resin may come on one side of the element and a metal lead frame may come on the other side, or a resin may come on both sides of the element. The case where the resin comes to both sides of the element is, for example, the case of a lead-on-chip (LOC) type package. In general, the elastic modulus of resin is lower than the elastic modulus of metal, but in the present invention, the elastic modulus of the stress absorption layers disposed on both sides of the element is lower than the elastic modulus of the resin. It is possible to reduce the stress generated in the element irrespective of whether it is adjacent to the resin via the metal or the metal lead frame via the low elastic modulus material.

Here, in the semiconductor device of the present invention as described above, the stress absorbing layer preferably includes a coating film covering one surface of the semiconductor element, and further, the stress absorbing layer includes a semiconductor film covered with the coating film. It is preferable to include an adhesive layer that is arranged on the surface opposite to the surface of the element and that bonds the semiconductor element to the metal lead frame. That is, the coating film or the adhesive layer reduces the stress generated in the device.

The modulus of elasticity of the coating film and the adhesive layer is preferably smaller by at least one order of magnitude than the modulus of elasticity of the sealing resin, and the difference between the modulus of elasticity of the coating film and the modulus of elasticity of the adhesive layer is less than one digit. Is preferred. Further, the coating film and the adhesive layer may be made of the same material.

In the present invention, a ferroelectric thin film may be formed on one of both surfaces of the semiconductor element. An element formed with a ferroelectric thin film, which is expected as a non-volatile memory element, is considered to have a particularly high possibility that the circuit characteristics will fluctuate due to the occurrence of stress. Since it is greatly reduced, there is no need to worry about fluctuation or deterioration of circuit characteristics, and high reliability can be expected.

Further, it is preferable that the elastic modulus of each of the adhesive layer and the coating film is smaller than 1 GPa.
Further, the adhesive layer and the coating film may be made of a silicon rubber-based material, or the adhesive layer may be made of a silicon rubber-based material, and the coating film may be made of a gel-like coating film.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing the configuration of the semiconductor device according to the present embodiment.
The semiconductor element 1 is fixed to a die pad 7 of a metal lead frame 7a via an adhesive layer 5, and the semiconductor element 1 and the outer leads 4 of the metal lead frame 7a are electrically connected by thin metal wires (for example, gold wires) 3. It is connected. After the connection of the semiconductor element 1 and the outer leads 4 by the thin metal wires 3, a coating material is applied to one surface of the semiconductor element 1 to form a coating film 2, and then the sealing resin 6 is formed.
Is performed, and the outer leads 4 are further cut and bent to complete the manufacture of the semiconductor device. A ferroelectric thin film is formed in the surface of the semiconductor element 1 on the side of the sealing resin 6 or the die pad 7, and the metal lead frame 7a is, for example, an iron-nickel alloy such as 42Ni—Fe or a copper alloy. Is used. Note that a material other than an iron-nickel alloy or a copper alloy may be used for the metal lead frame 7a. As the adhesive layer 5, a low elastic modulus material having an elastic modulus (hereinafter also referred to as Young's modulus) lower than the elastic modulus of the sealing resin 6 (preferably 1 GPa or less, more preferably 0.1 GPa or less as described later). The coating film 2 is used, and the elastic modulus of the coating film 2 is also lower than the elastic modulus of the sealing resin 6 (preferably 1 as described later).
GPa or less, more preferably 0.1 GPa or less) is used.

FIG. 2 is a sectional view of the semiconductor device shown in FIG.
FIG. In FIG. 2, half of the semiconductor device is shown in consideration of the symmetry, and the positional relationship between the semiconductor element 1 and the lead frame 7a (the die pad 7 and the outer lead 4) is shown. 5 is omitted. In the present embodiment, the outer leads 4 are provided so as to extend from two opposite sides of the semiconductor device.

Table 1 shows the thermal expansion coefficient and Young's modulus (corresponding to the elastic modulus) of typical constituent materials used in the above-described semiconductor device.

[0020]

[Table 1]

In general, a thermosetting epoxy resin is used as a sealing resin, and has an elastic modulus of 10 to 20 GPa.
In many cases. In addition, an iron-nickel alloy having a linear expansion coefficient close to that of a semiconductor element or a copper alloy having high heat dissipation is mainly used as a metal lead frame material. The resin sealing step is performed at about 180 ° C. and then cooled to room temperature. However, as shown in Table 1, the metal lead frame and the sealing resin have larger thermal expansion coefficients than the semiconductor element. , A thermal stress is generated in the semiconductor element.

FIG. 3 is a diagram showing an example of analysis of the distribution of vertical stress generated on the surface of the semiconductor element 1. The nickel-nickel alloy is used as the metal lead frame 7 a, and the coating film 2 is the same as the sealing resin 6. This is an example in which a polyimide having an elastic modulus is used as an adhesive layer 5 and an adhesive having a Young's modulus equivalent to that of the coating film 2 is used. In FIG. 3, the horizontal axis represents the distance (mm) from the center of the semiconductor element 1,
The vertical axis indicates the vertical stress (MPa). In the figure,
The symbol sig-xx is the vertical stress in the longitudinal direction of the semiconductor element (x direction in the figure), and sig-yy is the vertical stress in the width direction (y direction in the figure). When the semiconductor element has a rectangular shape, the value of the vertical stress in the longitudinal direction is generally larger than the value of the vertical stress in the width direction. FIG. 3 shows that the vertical stress has a maximum value at the center of the element and has a distribution that decreases monotonically toward the end of the element. The maximum value of the stress in this example is about 200 MPa.

FIG. 4 shows the relationship between the stress generated in the semiconductor element 1 in the bonding step by the bonding layer 5 and the elastic modulus of the bonding layer 5.
In FIG. 4, the horizontal axis represents the Young's modulus of the adhesive layer 5, and the vertical axis represents the maximum stress generated on the surface of the semiconductor element 1.
The 2Ni-Fe alloy and the square mark indicate the case of a copper alloy. When the material of the metal lead frame 7a is a 42Ni—Fe alloy, the Young's modulus of the adhesive layer 5 is small because the thermal expansion coefficient difference between the semiconductor element 1 and the metal lead frame 7a is small as shown in Table 1. Is 10 GPa or less, the stress generated in the semiconductor element 1 is 50 MPa or less.
On the other hand, when a copper alloy is used for the metal lead frame 7a, the generated stress varies greatly depending on the Young's modulus of the adhesive layer 5, for example, about 10 GPa when the Young's modulus is 0.1 GPa.
0 MPa, but 2 when the Young's modulus is 10 GPa
It exceeds 00MPa.

The critical stress value shown in FIG.
a) is a value at which cracking starts to occur in the semiconductor element 1. In this bonding step, the stress generated in the element 1 needs to be less than this value. In addition, when the generated stress increases, the adhesive layer itself may be cracked, or peeling of the bonding interface (bonding peeling) may occur. Such adhesion peeling often occurs empirically when the stress generated in the element 1 exceeds 100 MPa. Further, when the adhesive peeling occurs, the stress generated in the element 1 decreases. However, the peeling of the adhesive interface may cause a resin crack after the sealing step by the sealing resin 6 and cause a failure. Anyway, peeling of the adhesive is not preferable, as is the occurrence of stress in the element 1.

Therefore, in order to prevent both the adhesive peeling and the cracking of the semiconductor element 1, it is preferable to adopt a material composition in which the value of the stress generated in the semiconductor element 1 is 100 MPa or less. From this viewpoint, particularly when a copper alloy is used as the metal lead frame 7a, it can be said that the Young's modulus of the adhesive layer 5 is preferably set to 0.1 GPa or less. Of course, 42Ni is used as the metal lead frame 7a.
There is no need to worry when using an -Fe alloy. As a specific material of the adhesive layer 5 having a Young's modulus of 0.1 GPa or less,
For example, there is a silicone rubber-based adhesive.

Tables 2 and 3 show changes in the stress (measured value of the maximum stress at the center of the element) generated in the semiconductor element 1 after sealing by the sealing resin 6 with the Young's modulus of the coating film 2 and the adhesive layer 5. Is a table showing the case where is changed,
Table 2 shows the case where the metal lead frame 7a is made of an iron-nickel alloy, and Table 3 shows the case where the metal lead frame 7a is made of a copper alloy.

[0027]

[Table 2]

[0028]

[Table 3]

According to Tables 2 and 3, the coating film 2
It is understood that the stress generated in the semiconductor element 1 does not tend to be reduced so much only by reducing the elastic modulus of the semiconductor element 1 alone.
In particular, when the metal lead frame 7a is made of an iron-nickel alloy (in the case of Table 2), the stress is hardly reduced. When only the adhesive layer 5 has a low elastic modulus, the stress generated in the element 1 tends to increase. This increase in stress is due to the fact that only one side (upper surface in FIG. 1) of the semiconductor element 1 is firmly adhered to the sealing resin 6, and the one side of the element 1 directly bears the shrinkage force of the sealing resin 6 during cooling. Is due. In particular, in the case of the copper alloys shown in Table 3, the change in stress due to the difference in the combination of the coating film 2 and the adhesive layer 5 is large, and the stress when the adhesive layer 5 alone has a low elastic modulus is remarkably increased. Accordingly, the sealing resin 6 can be used to seal the coating film 2 on only one side of the semiconductor element 1 with a low elastic modulus or the adhesive layer 5 between the semiconductor element 1 and the metal lead frame 7a. Semiconductor element 1
It can be understood that the stress generated at the time cannot always be reduced.

On the other hand, the effect of reducing the stress appears only when both the coating film 2 and the adhesive layer 5 are made of a material having a low elastic modulus, and the stress applied to the semiconductor element 1 is about 1/10 to 1 To about / 30, specifically to about several MPa or less. In particular, in the case of the iron-nickel alloy shown in Table 2, the effect of reducing the stress is great. Of course, this is the same even when the material of the metal lead frame 7a is a copper alloy, and it is considered that the same is true even when other materials are used. In particular, in the semiconductor device using the nonvolatile memory element in which the ferroelectric thin film is formed on any surface of the semiconductor element 1 as in the present embodiment, it is considered that the sensitivity of the stress to the fluctuation of the circuit characteristic is high, and In order to improve the reliability of the product, the Young's modulus of the coating film 2 and the adhesive layer 5 must be at least 1 GPa or less, preferably 0.1 GPa or less.

Generally speaking, the elastic modulus of the coating film 2 and the adhesive layer 5 is preferably at least one order of magnitude smaller than the elastic modulus of the sealing resin 6. Further, in consideration of the balance between the coating film 2 and the adhesive layer 5, it is more preferable that the difference in elastic modulus between them is not more than one digit. Further, the coating film 2 and the adhesive layer 5 may be made of the same material.

As described above, a silicon rubber-based material is suitable as a specific material having an elastic modulus of 0.1 GPa or less.
The coating film 2 may be a gel coating film.

The preferred size (thickness) of each component in the semiconductor device of this embodiment is about 0.1 to 1.0 mm for the semiconductor element 1 (more preferably 0.2 to 1.0 mm).
About 0.4 mm), and about 0.1 to 2.
0 mm (more preferably about 0.3 to 0.8 mm), and about 0.1 to 0.1 mm for the metal lead frame 7a.
The thickness is about 5 mm (more preferably about 0.2 to 0.3 mm), and the thickness of the coating film 2 or the adhesive layer 5 is about 0.1 μm to 100 μm (more preferably several tens μm). In particular, it is considered that the minimum value of the thickness of the coating film 2 or the adhesive layer 5 is about 0.1 μm in consideration of a physical formation limit such as a thin film volume method. The dimensions of each component are not limited to those described above, and may be other values depending on conditions.

According to the present embodiment as described above, the elastic modulus of the coating film 2 and the adhesive layer 5 disposed on both surfaces of the semiconductor element 1 is lower than the elastic modulus of the sealing resin 6 (preferably 1 GPa or less, Since it is more preferably 0.1 GPa or less, the thermal strain is absorbed by the coating film 2 having a low elastic modulus and the adhesive layer 5 at the time of sealing with the sealing resin 6, and the stress generated in the semiconductor element 1 is reduced.
As a result, the stress applied to the entire element 1 is greatly reduced, fluctuations and deterioration of circuit characteristics are prevented, and the reliability of the product can be improved. Further, in the present embodiment using the semiconductor element on which the ferroelectric thin film is formed, the effect of preventing the fluctuation and deterioration of the circuit characteristics due to the drastic reduction of the stress and improving the reliability is great. The same can be said for the case where a semiconductor element 1 on which a ferroelectric thin film is not formed is used.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIGS. In the cross-sectional view of the semiconductor device shown in FIG. 5, the semiconductor element 11 is fixed to a die pad 17 of a metal lead frame 17a via an adhesive layer 15, and the semiconductor element 11 and the outer lead 14 of the metal lead frame 17a are made of a thin metal wire. (For example, gold wire) 13
Are electrically connected. After the connection of the semiconductor element 11 and the outer leads 14 by the thin metal wires 13, a coating material is applied to one surface of the semiconductor element 11 to form a coating film 12, and thereafter, sealing is performed with a sealing resin 16. The lead 14 is cut and bent to complete the manufacture of the semiconductor device. As the metal lead frame 17a, for example, 42Ni-Fe
Although an iron nickel alloy or a copper alloy such as this is used, other materials may be used. As in the first embodiment, the adhesive layer 15 and the coating film 12 have an elastic modulus lower than that of the sealing resin 16 (preferably 1 GPa).
Hereinafter, a material having a low elastic modulus of 0.1 GPa or less is more preferably used.

FIG. 6 is a cross-sectional view of the semiconductor device of FIG.
It is a bird's-eye view shown excluding 6. In FIG. 6, 1/4 of the semiconductor device is shown in consideration of the symmetry, the positional relationship between the semiconductor element 11 and the lead frame 17a (the die pad 17 and the outer lead 14) is shown, and the coating film 12 and the adhesive layer 15 is omitted. In the present embodiment, the outer leads 14 are provided so as to extend from four sides of the semiconductor device. Note that, similarly to the first embodiment, a ferroelectric thin film may be formed on the semiconductor element 11.

Next, a third embodiment of the present invention will be described with reference to FIGS. In the cross-sectional view of the semiconductor device shown in FIG. 7, the semiconductor element 21 is fixed to the outer leads 24 of the metal lead frame 27a via the adhesive layer 25, and the semiconductor element 21 and the metal lead frame 27a
Outer lead 24 is a thin metal wire (for example, gold wire) 2
3 are electrically connected. After the connection of the semiconductor element 21 and the outer leads 24 by the thin metal wires 23, a coating material is applied to one surface of the semiconductor element 21 to form a coating film 22, and thereafter, sealing is performed by a sealing resin 26. The lead 24 is cut and bent to complete the manufacture of the semiconductor device. As the metal lead frame 27a, for example, 42Ni-F
Although an iron nickel alloy such as e or a copper alloy is used, other materials may be used. As in the first embodiment, the adhesive layer 25 and the coating film 22 have an elastic modulus lower than that of the sealing resin 26 (preferably 1 GP).
a or less, more preferably 0.1 GPa or less). In this embodiment, no die pad exists, and the semiconductor element 21 is directly connected to the outer lead 24.
Is fixed.

FIG. 8 is a sectional view of the semiconductor device of FIG.
It is a bird's-eye view shown excluding 6. In FIG. 8, half of the semiconductor device is shown in consideration of the symmetry, the positional relationship between the semiconductor element 21 and the lead frame 27a (outer lead 24) is shown, and the coating film 22 and the adhesive layer 25 are shown.
Is omitted. In the present embodiment, the outer leads 24
Are provided so as to extend from two opposite sides of the semiconductor device. Note that, similarly to the first embodiment, the semiconductor element 2
1, a ferroelectric thin film may be formed.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the cross-sectional view of the semiconductor device shown in FIG. 9, an insulating film 38 is formed on the surface of a metal lead frame 37 a, and the semiconductor element 31 has an outer lead 3 on which the insulating film 38 is formed via an adhesive layer 35.
The semiconductor element 31 and the outer lead 34 are electrically connected to each other by a thin metal wire (for example, a gold wire) 33. After the connection between the semiconductor element 31 and the outer lead 34 by the thin metal wire 33, a coating material is applied to one surface of the semiconductor element 31 to form a coating film 32, and thereafter, sealing is performed by a sealing resin 36. The leads 34 are cut and bent to complete the manufacture of the semiconductor device. Metal lead frame 37a
For example, an iron-nickel alloy such as 42Ni-Fe or a copper alloy is used, but other materials may be used. As the adhesive layer 35 and the coating film 32,
Similarly to the first embodiment, a low elastic modulus material having an elastic modulus lower than that of the sealing resin 36 (preferably 1 GPa or less, more preferably 0.1 GPa or less) is used.
In the present embodiment, no die pad exists, and the semiconductor element 31 is directly fixed to the surface of the outer lead 34 on which the insulating film 38 is formed.

FIG. 10 is a bird's-eye view showing the semiconductor device of FIG. 9 without the sealing resin 36. In FIG. 10, 1/4 of the semiconductor device is shown in consideration of symmetry.
1 shows the positional relationship between the lead frame 37a (outer lead 34) and the coating film 32, the adhesive layer 35, and the insulating film 38 are omitted. In the present embodiment, the outer leads 34 are provided so as to extend from four sides of the semiconductor device. In addition, similarly to the first embodiment,
A ferroelectric thin film may be formed on the semiconductor element 31.
Further, if the adhesive layer 35 is an insulating material, the insulating film 38
Is not necessary.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. In the cross-sectional view of the semiconductor device shown in FIG. 11, an insulating film 48 is formed on the surface of a metal lead frame 47a, and the semiconductor element 41 is fixed to an outer lead 44 on which the insulating film 48 is formed via an adhesive layer 45. , Semiconductor element 41 and outer lead 4
4 is electrically connected with a thin metal wire (for example, a gold wire) 43. At this time, for example, if the adhesive layer 45 near the connection portion is opened in a window shape so that the terminal portion of the semiconductor element 41 is exposed, the connection can be performed without being blocked by the adhesive layer 45. After the connection of the semiconductor element 41 and the outer lead 44 by the thin metal wire 43, the metal lead frame 47a
A coating material is applied to one surface of the semiconductor element 41 on the side opposite to the surface to which the substrate is adhered to form a coating film 42, which is thereafter sealed with a sealing resin 46, and further, the outer leads 44 are cut and bent. Thus, the manufacture of the semiconductor device is completed. Metal lead frame 47a
For example, an iron-nickel alloy such as 42Ni-Fe or a copper alloy is used, but other materials may be used. As the adhesive layer 45 and the coating film 42,
As in the first embodiment, a low elastic modulus material having an elastic modulus lower than that of the sealing resin 46 (preferably 1 GPa or less, more preferably 0.1 GPa or less) is used.
Further, the present embodiment is a lead-on-chip (LOC) type semiconductor device in which the surface of the outer lead 44 on which the insulating film 48 is formed is directly fixed to the upper surface of the semiconductor element 41.

FIG. 12 is a bird's-eye view showing the semiconductor device of FIG. 11 with the sealing resin 46 removed. However, in FIG.
1/4 of the semiconductor device is shown in consideration of the symmetry, and the semiconductor element 41 and the lead frame 47a (the outer lead 4) are shown.
The positional relationship of 4) is shown, and the coating film 42
The adhesive layer 45 and the insulating film 48 are omitted. In the present embodiment, the outer leads 44 are provided so as to extend from two opposite sides of the semiconductor device. Note that a ferroelectric thin film may be formed on the semiconductor element 41 as in the first embodiment. Further, if the adhesive layer 45 is an insulating material, the insulating film 48 is not necessarily required.

Next, a sixth embodiment of the present invention will be described with reference to FIGS. In the cross-sectional view of the semiconductor device shown in FIG. 13, an insulating film 58 is formed on the surface of a metal lead frame 57a, and the semiconductor element 51 is fixed to an outer lead 54 on which the insulating film 58 is formed via an adhesive layer 55. , Semiconductor element 51 and outer lead 5
4 is electrically connected with a thin metal wire (for example, a gold wire) 53. At this time, for example, if the adhesive layer 55 near the connection portion is opened in a window shape so that the terminal portion of the semiconductor element 51 is exposed, the connection can be performed without being blocked by the adhesive layer 55. After the connection of the semiconductor element 51 and the outer lead 54 by the thin metal wire 53, the metal lead frame 57a
A coating material is applied to one surface of the semiconductor element 51 on the side opposite to the surface to which the substrate is adhered to form a coating film 52, which is thereafter sealed with a sealing resin 56, and the outer leads 54 are cut and bent. Thus, the manufacture of the semiconductor device is completed. Metal lead frame 57a
For example, an iron nickel alloy such as 42Ni—Fe or a copper alloy is used, but other materials may be used. As the adhesive layer 55 and the coating film 52,
As in the first embodiment, a low elastic modulus material whose elastic modulus is lower than that of the sealing resin 56 (preferably 1 GPa or less, more preferably 0.1 GPa or less) is used.
Further, the present embodiment is a lead-on-chip (LOC) type semiconductor device in which the surface of the outer lead 54 on which the insulating film 58 is formed is directly fixed to the upper surface of the semiconductor element 51.

FIG. 14 is a bird's-eye view showing the semiconductor device of FIG. 12 without the sealing resin 56. However, in FIG.
The semiconductor device 51 and the lead frame 57a (the outer lead 5)
The positional relationship of 4) is shown, and the coating film 52 is shown.
The adhesive layer 55 and the insulating film 58 are omitted. In the present embodiment, the outer leads 54 are provided so as to extend from four sides of the semiconductor device. Note that a ferroelectric thin film may be formed on the semiconductor element 51 as in the first embodiment. Furthermore, if the adhesive layer 55 is an insulating material, the insulating film 58 is not necessarily required.

According to the above-described second to sixth embodiments, the same effects as those of the first embodiment can be obtained.

In the above description, the semiconductor element and the metal lead frame (outer lead) are electrically connected by a thin metal wire. However, a metal bump such as a solder ball may be used.

[0047]

According to the present invention, on both surfaces of a semiconductor device,
Since the stress absorption layer made of a material whose elastic modulus is lower than the elastic modulus of the sealing resin is disposed as a coating film or an adhesive layer, thermal stress is absorbed by the low elastic modulus stress absorbing layer at the time of sealing with the sealing resin, The stress generated in the semiconductor element is reduced. As a result, the stress applied to the entire element is significantly reduced, and fluctuation and deterioration of the circuit characteristics are prevented, and the reliability of the product can be improved. For example, the elastic modulus of the coating film and the adhesive layer disposed on both surfaces of the semiconductor element is preferably 1 GPa or less, more preferably 0.1 GPa or less.
Since the pressure is set to 1 GPa or less, the stress applied to the semiconductor element can be remarkably reduced to about 1/10 or less, specifically, to about several MPa or less. Further, when a semiconductor element on which a ferroelectric thin film is formed is used, the effect of preventing a change or deterioration of circuit characteristics due to a drastic reduction of stress and improving reliability is great.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a bird's-eye view showing the semiconductor device of FIG. 1 without a sealing resin.

FIG. 3 is a diagram showing an analysis example of a vertical stress distribution generated on the surface of a semiconductor element, in which an iron-nickel alloy is used as a metal lead frame, and a polyimide having an elastic modulus equivalent to that of a sealing resin is used as a coating film; It is a figure showing an example at the time of using an adhesive which has a Young's modulus equivalent to a coating film as an adhesive layer.

FIG. 4 is a view showing a relationship between stress generated in a semiconductor element in a bonding step using a bonding layer and an elastic modulus of the bonding layer.

FIG. 5 is a sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

6 is a bird's-eye view showing the semiconductor device of FIG. 5 without a sealing resin.

FIG. 7 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

8 is a bird's-eye view showing the semiconductor device of FIG. 7 without a sealing resin.

FIG. 9 is a sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment;

10 is a bird's-eye view showing the semiconductor device of FIG. 9 without a sealing resin.

FIG. 11 is a sectional view illustrating a configuration of a semiconductor device according to a fifth embodiment;

12 is a bird's-eye view showing the semiconductor device of FIG. 11 without a sealing resin.

FIG. 13 is a sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment;

14 is a bird's-eye view showing the semiconductor device of FIG. 13 without a sealing resin.

[Explanation of symbols]

 Reference Signs List 1 semiconductor element 2 coating film 3 thin metal wire 4 outer lead 5 adhesive layer 6 sealing resin 7 die pad 7a metal lead frame 11 semiconductor element 12 coating film 13 thin metal wire 14 outer lead 15 adhesive layer 16 sealing resin 17 die pad 17a metal Lead frame 21 Semiconductor element 22 Coating film 23 Thin metal wire 24 Outer lead 25 Adhesive layer 26 Sealing resin 27a Metal lead frame 31 Semiconductor element 32 Coating film 33 Thin metal wire 34 Outer lead 35 Adhesive layer 36 Sealing resin 37a Metal lead frame Reference Signs List 38 insulating film 41 semiconductor element 42 coating film 43 thin metal wire 44 outer lead 45 adhesive layer 46 sealing resin 47a metal lead frame 48 insulating film 51 semiconductor element 52 Coating film 53 thin metal wire 54 outer leads 55 adhesive layer 56 the sealing resin 57a metallic leadframe 58 insulating film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-110651 (JP, A) JP-A-3-2888464 (JP, A) JP-A-6-204264 (JP, A) JP-A-63-204 114241 (JP, A) JP-A-4-164353 (JP, A) JP-A-4-363032 (JP, A) JP-A-7-86461 (JP, A) JP-A-7-94642 (JP, A) Toray Dow Corning Silicone Co., Ltd., Silicone Materials Handbook, Japan, Toray Dow Corning Silicone Co., Ltd., pp. 220-225 Yukihiro Kumagai, Hideo Miura, Evaluation of polarization of ferroelectric capacitors by stress analysis, Japan Society of Mechanical Engineers Calculation Mechanics Lecture Meeting, Japan (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 23/28-23/31

Claims (3)

(57) [Claims] 1. A semiconductor device having one surface covered with a coating film and the other surface having an adhesive layer formed thereon, a metal lead frame joined to the semiconductor device via the adhesive layer, and A semiconductor device comprising an element and a sealing resin for sealing the metal lead frame, wherein the metal lead frame is made of a copper alloy or an iron nickel alloy.
, And the ferroelectric thin film is formed on the semiconductor element,
The modulus of elasticity of both the coating film and the adhesive layer is 0.1 GPa or less, and is a value that is at least one order of magnitude smaller than the modulus of elasticity of the sealing resin. A semiconductor device, wherein the difference from the elastic modulus is one digit or less. 2. The semiconductor device according to claim 1, wherein the elastic modulus of the coating film and the elastic modulus of the adhesive layer are:
A semiconductor device having substantially equal values. 3. The semiconductor device according to claim 1, wherein said coating film and said adhesive layer are made of the same material.