JP3271640B2 - Digital data receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention temporarily stores a plurality of digital data sequentially received from a transmission line in a reception data FIFO, and generates an error or the like generated for each of the received digital data. The present invention relates to a digital data receiving apparatus that temporarily stores auxiliary information data representing information related to the corresponding digital data in a reception status FIFO,
FIFO (first-in first-ou) used as reception buffer
The present invention relates to a digital data receiving apparatus capable of reducing a storage capacity required for t), thereby reducing costs and the like.

[0002]

2. Description of the Related Art A telephone network constructed for the purpose of voice communication, such as a telephone network such as a telephone-type public communication line or a specific communication line, requires transmission quality and transmission speed when used for data communication. There are restrictions on the point. For this reason, digital data public networks that are more suitable for characteristics unique to data communication, such as data traffic characteristics, are being promoted in countries around the world, including Japan. This digital data public network uses a transmission path and a switch for digital signals, and in Japan,
Services are provided by circuit switching networks and packet switching networks. For international connections, CCITT (intern
ational telegraph and telephone consultative commi
International standardization is being promoted by Ttee), and at present it is almost fully prepared as a new data network related recommendation (X series recommendation) such as a circuit switching system, a packet switching system, and a digital leased line.

On the other hand, in recent years, a LAN (local arbiter) has been used for sharing information (data) such as a database and peripheral devices.
A network called an ea network has been widely used. This LAN connects digital devices such as computers and communication terminal devices that are distributed and installed within a limited predetermined premises, for example, within a limited range of offices, factories, laboratories, universities, and the like. It has some sort of exchange function. Even in such a LAN, the IEEE (institute of electrical electronics)
Engineers) The 802 Committee, ISO (International Organization for Standardization) and the like standardize protocols and the like.

An open system interconnection (OSI) reference model applied to the digital data public network and a layer configuration of the LAN protocol standardized by IEEE use a protocol that can be hierarchically divided into a plurality of layers. It has become. Also, WAN (wide area
network) and protocols frequently used in other LANs and the like are standardized and can be generally divided into a plurality of layers.

[0005] The layers of the OSI reference model are a physical layer of the first layer, a data link layer of the second layer, a network layer of the third layer, a transport layer of the fourth layer, and a session of the fifth layer. It is composed of a layer, a presentation layer of a sixth layer, and an application layer of a seventh layer. In the layer structure of the protocol defined by IEEE, the first layer is a physical layer, the second layer is a medium access control sublayer and a logical link control sublayer, and the third layer is a network layer.

Here, the protocol used for the above-mentioned second data link layer, that is, the data link protocol includes, for example, BASIC procedure and HDLC (high lev).
There is a protocol called an el data link control) procedure.

For example, the BASIC procedure is used at a lower level of a public line network protocol, and communication by a teletype terminal has been studied. This BASIC procedure corresponds to, for example, the BSC procedure of IBM Corporation in the United States. The HDLC procedure is widely used at a lower level of a protocol widely used in a public line network or the like. In the HDLC procedure, the aforementioned BASIC
It evolved from a procedure and specifies, among other things, the probability and release of a data communication link, as well as the error control of the transferred data.

FIG. 8 is a diagram showing a format of the HDLC procedure.

As shown in FIG. 8, the format of one message conforming to the definition of the HDLC procedure is a flag A1.
, Address A2, control A3, transfer data A4, CRCAs 5 and A6, and flag A7.

First, one telegram is recognized by the flag A1 at the head and the flag A7 at the tail end.
For example, the flag A1 is a constant bit string of 8 bits, that is, a bit string of “01111110”. The address A2 indicates a transfer destination of the message. The control A3 is used for various settings or controls of the corresponding message. Each of the address A2 and the control A3 is an 8-bit bit string.

The transfer data A4 transmitted after the flag A1, the address A2 and the control A3 is:
This is digital data to be actually transmitted in the message.
In the HDLC procedure, the transfer data A4 is one in which a large number of bit data is sequentially and continuously transmitted, and is in a bit stream state. For example, even when digital data is transferred in units of bytes or in units of words such as 16 bits or 32 bits, the HDLC procedure does not perform such byte-based or word-based distinction, but sequentially in a bit stream state. Transmit digital data.

After the transfer data A4, the CRCAs 5 and A6 are transmitted. These CRCAs 5 and A6 are also called a frame check sequence. In addition, these C
Each of RCA5 and A6 is an 8-bit bit string, which is a total of 16-bit bit strings. These CRCA
5 and A6, H of digital data transmitted
Error control is performed for each message according to the DLC procedure.

FIG. 9 is a block diagram showing a configuration of a conventional digital data receiving apparatus.

FIG. 9 shows an example of a conventional digital data receiving apparatus using a FIFO as a receiving buffer. The digital data receiving apparatus shown in FIG. 9 includes a plurality of digital data R sequentially received from a transmission path.
First, the XD is temporarily stored in the reception data FIFO 12, and for each of the received digital data, auxiliary information data representing information on an error or the like that has occurred is received while corresponding to the corresponding digital data RD. The data is temporarily stored in the FIFO 14.

Such a digital data receiving apparatus is not limited to this, but can be used for receiving digital data transmitted in accordance with, for example, the HDLC procedure described above.

In the conventional digital data receiving apparatus, for example, when handling a message in accordance with the HDLC procedure, if a message in a format as shown in FIG. 8 is received, the received data FIFO 12 1 is accessed in units of one bit width, that is, in units of 8 bits.
The data is converted into data as shown in FIG.

That is, the bit stream in one received telegram between the flag A1 and the flag A7 is sequentially divided into 8-bit lengths. The address A2, the control A3, the CRCA5
And A6 are all 8 bits in the format of the HDLC procedure, and are therefore treated as 1 byte, and are treated as shown by reference numerals B2, B3, B7, and B8 in FIG. As for the transfer data A4, the data in the bit stream state according to the HDLC procedure is sequentially divided into 8-bit lengths.
Handled as shown in 4-B6.

The flags A1 and A7 shown in FIG. 8 are for synchronizing transmitted data. Therefore, after reception, these flags A1 and A7 are not taken into the reception data FIFO 12. Finally, the data of the flags A1 and A2 and the corresponding data of the flags B1 and B9 in FIG. 10 are discarded.

In this case, when the data is divided into 8 bits, the transfer data B corresponding to the end of the bit stream is transmitted.
As for 6, there is a case where the length is less than 8 bits.
The transfer data B6 when receiving the message of the HDLC procedure
The data less than the predetermined bit width L is hereinafter referred to as fractional data.

First, as shown in FIG. 9, the conventional digital data receiving apparatus includes a FIFO control unit 10 and
The reception data FIFO 12 and the reception status F
It is composed of an IFO 14, a serial / parallel conversion unit 16, and a fraction information encoder 18.

The reception data FIFO 12 stores the digital data RX sequentially received from the transmission line as described above.
D is used as a receiving buffer for temporarily storing D. The reception data FIFO 12 has a bit width of, for example, 8 bits.
Accessed bit by bit. The received data FIF
For O12, for example, a RAM of 1024 bytes in total is used.

On the other hand, the reception status FIFO 14
Stores, as described above, auxiliary information data in units of 6 bits, as shown in FIG. 11, representing information on an error that has occurred, for each of the digital data RXD sequentially received from the transmission path. The reception status FIFO 14
Is accessed in units of 6 bits, and is a (6 bits × 1024 words) RAM (random access memo).
ry).

As shown in FIG. 11, the reception status FIFO 14 includes RE bits B0 to B2 and CRC
It is composed of an E bit B3, an OVRE bit B4, and an EOF bit B5.

Here, in FIG. 11, first, RE
Bits B0 to B2 are “1” to
Indicates the numerical value of “8”. The numerical value indicates the actually valid bit length of the fraction data serving as the end portion divided by the 8-bit width, for example, the ten transfer data B6.

The CRCE bit B3 is transmitted according to the HDLC procedure, and a CRC
(Cyclic redundancy check) Indicates the presence or absence of an error. This CRC check is performed by the CRCAs 5 and A shown in FIG.
6 is performed.

The OVRE bit B4 is used to transmit the digital data RX
When sequentially receiving data D, an overrun that occurs when data temporarily stored in the reception data FIFO 12 and the reception status FIFO 14 is overwritten with another data although the data has not been read out. Indicates the presence or absence of an error. Such an overrun error is caused by the fact that data is sequentially written to the reception data FIFO 12 and the reception status FIFO 14 as the digital data RXD is sequentially received from the transmission path.
This occurs when reading data from O12 and reception status FIFO 14 is delayed.

The EOF bit B5 indicates that the corresponding data to be written to the reception data FIFO 12 is
9 shows whether or not the data is the final data of the data transferred by the HDLC procedure shown in FIG. For example, it indicates whether or not the data corresponding to the received data FIFO 12 is the final data, like the transfer data B6 in FIG.

Note that the final data is expressed as “EOF (end of frame)” hereinafter.

Next, in order to receive the received digital data RXD from the transmission line, the FIFO control unit 10 receives the received data FID according to the input write signal FWR.
The FO 12 and the reception status FIFO 14 are controlled. The write signal FWR is output from the serial / parallel converter 16 as described later. Specifically, the FIFO control unit 10 receives the received 8 bits according to the address register A of the FIFO control unit 10.
The 1-byte data divided into bits is written to the reception data FIFO 12, and the corresponding 6-bit auxiliary information data is written to the reception status FIFO 14. Such writing is performed by the control signals CT1 and CT2. After such writing, the address stored in the address register A is incremented (the value is increased by "1").

Further, the FIFO control unit 10 converts received data and the auxiliary information data corresponding to the received data into the reception data FIFO 12 or the reception status FIFO according to a read signal FRD input from the outside.
14 is read out. Specifically, the FI
The FO control unit 10 reads out the memory of the reception data FIFO 12 and the reception status FIFO 14 specified by the built-in address register B by using a control signal CT.
1 and CT2. After such reading of one data, the value of the address register B is incremented.

The values of the address registers A and B take on values from "0" to "1023". The initial values of these address registers A and B are both "0" and are sequentially incremented. Also, after "1023", it becomes "0" again. If the value of the address register A exceeds the value of the address register B, new data is overwritten on the unread data stored in the reception data FIFO 12 and the reception status FIFO 14. In this case, the above-mentioned overrun error occurs. Therefore, such an overrun error is determined by the address register A or B. When such an overrun error is determined, the FIFO control unit 10 outputs the control signal OV.
Output RE.

The serial-to-parallel conversion section 16 has an HD
The digital data RXD sequentially received from the transmission path in a bit stream state according to the LC
Perform parallel conversion. The serial / parallel conversion unit 16
The digital data RXD received in a bit stream state is sequentially read into a built-in 8-bit shift register. The 8-bit bit pattern of the shift register sequentially read in this manner is the HD pattern of the flag A1.
The flag pattern determined by the LC procedure (“011111
10 ″), the serial / parallel conversion unit 16
Sets the control signal F to the H state. Thereafter, the serial / parallel conversion unit 16 converts the received parallel 8-bit data RD1 after serial / parallel conversion into
The data is output to the reception data FIFO 12 in parallel.

Here, the serial / parallel converter 16
After the detection of the flag A1, during a period from the address A (the address B2) to the CRCA6 (the CRCB8), for each output of the parallel data RD1, a control signal RE1 described later in detail with reference to FIG. At the timing of “0”, the write signal FWR is set to the H state. The serial / parallel converter 16 also sets the write signal FWR to the H state when the flag A7 is detected. The detailed timing at which the write signal FWR becomes the H state will be described later with reference to FIG.

The serial / parallel converter 16 outputs control signals EOF and CRCE when receiving the digital data RXD. The control signal EO
The logic state of F is written to the EOF bit B5 shown in FIG. The logic state of the control signal CRCE is written to the CRCE bit B3. The logical state of the control signal OVRE output from the FIFO control unit 10 is the same as that of the OVRE.
Written to bit B4.

Next, as the fraction information encoder 18, a 3-bit binary counter 18a is used as shown in FIG.

As shown in FIG. 12, the reception clock RXC is input to the input D of the 3-bit binary counter 18a. The reception clock RXC is received from the transmission path together with the digital data RXD.
Also, the control signal F is the 3-bit binary counter 1
8a is input to the input RST. When the input RST goes to the H state, the value of the 3-bit binary counter 18a is reset to "0". And 3
When the logic state of the input D rises, the bit binary counter 18a increments the value being counted. The count value of the 3-bit binary counter 18a is output as the control signal RE1 in 3 bits. The control signal RE1 corresponds to the RE bits B0 to B2 in FIG.
14 is written.

The operation of the fraction information encoder 18 is as follows.
This is as shown in the time chart of FIG.

First, the reception clock RXC is a clock signal corresponding to each bit of the digital data RXD sequentially received from the transmission path and taken into the serial / parallel conversion unit 16. The control signal F is output from the serial / parallel converter 16 to the flag A1 or A7.
Is set to H state.

Therefore, as shown in the time chart of FIG. 13, when the control signal F goes to the H state at time t1,
First, the 3-bit binary counter 18a is reset. Therefore, the value of the control signal RE1 output from the 3-bit binary counter 18a is "0".

Thereafter, when the next reception clock RXC is input at time t2, the value of the 3-bit binary counter 18a is incremented to "1". Thereafter, when the clock of the reception clock RXC is sequentially input at times t3 and t4, the value of the 3-bit binary counter 18a is sequentially incremented.

The 3-bit binary counter 1 as described above
The increment of 8a is sequentially performed in response to reception of all the bit data of the transfer data A4. Further, if the value of the 3-bit binary counter 18a is "7", for example, at time t12 or t22 in FIG. 13, the value is "0" because the counter is a 3-bit binary counter. At this time, the write signal FWR
Is in the H state, and under the control of the FIFO control unit 10,
The reception data FIFO 12 and the reception status FI
Data writing to the FO 14 is performed. In particular, the data RD1 is written in the reception data FIFO12.

Here, when the flag A7 is detected,
For example, as shown at time t31 in FIG.
Becomes H state, and the write signal FWR becomes H state. At this time, for example, at the time t3 in FIG.
1, the value of the 3-bit binary counter 18a,
That is, the value of the control signal RE1 is the value X of the bit number of the fraction data as described above. This is because the increment from “0” to “7” in the 3-bit binary counter 18a is synchronized with the reception of the digital data RXD. When the number of bits of the fraction data is zero, at the time t31, the control signal RE is output.
The value of 1 is zero.

As described above, according to the conventional digital data receiving apparatus described with reference to FIGS.
The digital data RXD sequentially received from the transmission path according to the DLC procedure is stored in a reception buffer, specifically, the reception data FIFO 12 and the reception status FIFO.
14 can be received. In particular, since the reception buffer is provided as described above, the reception data RD2
Even if the reading of data is delayed, the digital data RXD can be efficiently received from the transmission path within a range where the above-mentioned overrun error does not occur.

In such a digital data receiving apparatus, the reception data temporarily stored in the reception data FIFO 12 is read out as 8-bit length reception data RB2. Further, the reception status as shown in FIG. 11 of each reception data RB2 thus read can be read from the reception status 14 as a control signal ST having a 6-bit length.

[0045]

However, in the conventional digital data receiving apparatus described above with reference to FIGS. 9 to 13, the conventional digital data receiving apparatus has six bits for storing the reception status corresponding to 8 bits of reception data. Takes a bit.

Specifically, the reception data FIFO 12
Reception status FIFO 14 provided for
FIG. 1 corresponds to the above-mentioned FIG.
A memory for storing the 6-bit reception status as shown in FIG.

In particular, when it is intended to store more detailed auxiliary information for each received data, the storage capacity of the reception status FIFO 14 is increased. For example, if the reception status as shown in FIG. 11 increases to 8 bits, the storage capacity of the reception data FIFO 12, which is essentially required as a reception buffer for storing data sequentially received from the transmission line, is stored. ,
As a whole, twice the storage capacity is required.

The present invention has been made to solve the above-mentioned conventional problems, and has been made in consideration of a FIFO used as a reception buffer.
It is an object of the present invention to provide a digital data receiving device capable of reducing the storage capacity required for the digital data and thereby reducing the cost.

[0049]

SUMMARY OF THE INVENTION According to the present invention, a plurality of digital data sequentially received from a transmission line are temporarily stored in a reception data FIFO, and a plurality of digital data are generated for each of the received digital data. A digital data receiving apparatus which temporarily stores auxiliary information data representing information on an error or the like in a reception status FIFO while associating the digital data with the corresponding digital data. When the received data becomes invalid data ,
An auxiliary information data generating means for generating the auxiliary information data indicating whether or not the error has occurred , stored in a status FIFO, and the reception data FIFO instead of the invalid data.
O, and a detailed information data generating means for generating detailed information on the error that has occurred.
The above object has been achieved.

Further, in the digital data receiving apparatus, the auxiliary information to be generated by paying attention to the mutual exclusion of occurrence or non-occurrence of a plurality of types of errors that can occur in the auxiliary information data. Auxiliary information data compression means for performing data data compression, and the reception status FI
By providing auxiliary information restoring means for reading out from the FO and expanding the compressed data of the auxiliary information data using the detailed information, the above-mentioned object is achieved, and the FIFO used as a reception buffer is required. Storage capacity is further reduced.

In the digital data receiving apparatus, a plurality of the digital data sequentially received from the transmission path are received in a bit stream state based on an HDLC procedure, and
O is constituted by a series of word memories each having a bit width L, and further, when the digital data sequentially received from the transmission path is temporarily stored in the reception data FIFO, a bit stream state Data conversion means for writing the digital data into the reception data FIFO while sequentially dividing the digital data by the length of the bit width L is provided. When the digital data is divided by the data conversion means and written to the reception data FIFO, At the end of the digital data received in a stream state, fractional data less than the bit width L is converted into the received data F.
When the fraction data to be written to the IFO is generated, the supplementary information data generating means has a fraction information generating means for generating the auxiliary information data indicating the occurrence of the fraction data, and the detailed information is generated as the detailed information when the fraction data is generated. Since the detailed information data generating means has a fraction bit number information generating means for generating information indicating the bit number N of the fraction data, the above-mentioned object is achieved and the received data based on the HDLC procedure is handled. Accordingly, the storage capacity required for the FIFO for storing the information on the fraction data as the auxiliary information data as described above is also reduced.

[0052]

As in the above-described conventional example, conventionally, data relating to the digital data RXD sequentially received from the transmission line is temporarily stored in the dedicated reception data FIFO 12. On the other hand, this is clearly distinguished, and auxiliary information relating to an error or the like generated at the time of receiving the digital data RXD is stored in the dedicated reception status FIFO 14 independent of the reception data FIFO 12. I have.

As described above, conventionally, the purpose of use of the reception data FIFO 12 and the reception status F
The purpose of use of the IFO 14 is clearly distinguished.

Here, in the present invention, when an error or the like occurs when the digital data RXD is received from the transmission line, the received digital data RXD is invalid or meaningless data. We pay attention to it. Further, in the present invention, when the received data becomes invalid data due to the occurrence of an error or the like, the memory for storing the received digital data RXD is diverted to another device to make the data more effective. It is configured to be used for

That is, in the present invention, the purpose of use of the reception data FIFO 12 and the reception status FIFO
The use purpose of O14 is not clearly distinguished as in the related art, and the reception data FIFO 12 also stores auxiliary information such as information on an error that has occurred. This makes it possible to reduce the storage capacity required for the reception status FIFO for storing such auxiliary information.

Specifically, when the received digital data becomes invalid data as described above due to an error or the like, only the auxiliary information data having the error is stored in the reception status FIFO. Remember. That is, the reception status FIFO 14 does not store detailed information of the error that has occurred in this manner.

On the other hand, more detailed information on the error or the like that has occurred in this way is stored in the reception data FIFO 12 instead of the data that has become invalid data due to the error that has occurred. I have. The digital data R received due to an error
If the XD becomes invalid data, it is meaningless to store such invalid data in the reception data FIFO 12. Therefore, instead of such invalid data, more detailed information such as the type of error that has occurred is stored in the received data FIFO 12. In addition, storing the detailed information in this way means that the reception status FIFO 14
The presence or absence of such an error stored in the auxiliary information data can be identified.

Therefore, according to the present invention, information relating to occurrence of an error or the like can be stored using not only the reception status FIFO 14 but also the reception data FIFO 12. Therefore, since the memory is shared in this way, it is possible to reduce the storage capacity required for the FIFO used as the reception buffer as a whole, thereby reducing costs and the like.

The data to be used as the auxiliary information data as described above is not limited to information on literal errors. In other words, the present invention can be similarly applied when any state occurs irrespective of an error occurrence state and at least some bits of the received data at this time become invalid data.

For example, in a conventional example described later, more detailed information on an error that has occurred is first written to the reception data FIFO 12 instead of invalid data. Further, in this embodiment, information on the fraction data when the HDLC procedure is used is written. That is, the fraction data is invalid bit data other than the fraction bit data according to the digital data RXD received from the transmission path. Therefore, in an embodiment described later, the reception status FIF
Only the auxiliary information data indicating whether the data is the fraction data is written into O14, and specific information on the bit number N of the fraction data is written into the reception data FIFO 12. For this reason, it is not necessary to store information indicating the number N of bits of the fraction data in the reception status FIFO 14 unlike the related art, and the storage capacity required for the FIFO used as the reception buffer can be reduced accordingly.

As described above, in the present invention,
When an error or the like occurs, the reception status FIFO 14 does not store detailed information on the error that has occurred, but merely stores information on whether or not the error has occurred. Here, for example, when attention is paid to some types of errors, there are combinations that cannot be generated simultaneously. As described above, there is a case where the presence / absence of occurrence is mutually exclusive among the types of errors that occur. In such a case, for example, as in an embodiment described later, the combination pattern of the presence or absence of an error in a plurality of types of errors is grasped, and coding is performed on each combination pattern, so that an error occurrence It is possible to perform data compression of the auxiliary information data indicating presence / absence.

For example, in an embodiment to be described later for handling data received from a transmission line based on the HDLC procedure, it is necessary to include not only whether an error has occurred, whether or not fractional data has occurred, but also whether or not an EOF has occurred. The presence or absence of these three specific states is identified only by the 2-bit auxiliary information data. By this data compression, in this embodiment, the auxiliary information data which originally needs 3 bits is reduced to 2 bits.

[0063]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital data receiving apparatus to which the present invention is applied.

In the digital data receiving apparatus of the present embodiment, the FIFO control unit 10 and the reception data FIFO 12 shown in FIG.
The fraction information encoder 18 has the same hardware configuration as the conventional example described above with reference to FIG.

The reception status FIFO1 shown in FIG.
4 does not perform data compression as described below,
(3 bits × 1024 words) RAM is used.
On the other hand, when performing data compression, the reception status FIFO 14 uses a (2 bits × 1024 words) RAM.

In addition to such a configuration, in the present embodiment, the status encoder 22 and the selector 24
And a status decoder 26.

The selector 24 has inputs S, 0 and 1
And an output U. The selector 24 selects either the input 0 or the input 1 according to the signal input to the input S, and outputs the logic state of the selected input to the output U. That is, when the L state is input to the input S, the logic state input to the input 0 is output to the output U. On the other hand, when the H state is input to the input S, the logic state input to the input 1 is output to the output U.

Next, the status encoder 22
As shown in FIG. 2, it is composed of an auxiliary information data generating means 22d and a detailed information data generating means 22e.

The auxiliary information data generating means 22d and the detailed information data generating means 22e are provided with the control signals EOF and CRCE output from the serial / parallel conversion unit 16 and the control signal EOF output from the FIFO control unit 10. OVRE and the aforementioned 3-bit control signal RE1 output from the fraction information encoder 18 are input. Further, a 2-bit status signal RS1 to be stored in the reception status FIFO 14 is output from the auxiliary information data generating means 22d. The 1-bit signal on the MSB side of the status signal RS1, that is, the status signal RS1 <1> is input to the selector 24 and used for switching selection of the selector 24. The LSB side of the status signal RS1 is RS <0>, and the MSB side is RS <1>. Further, the detailed information data generating means 22e is input to the selector 24,
The reception data FIFO is selected by the selector 24.
And outputs a data signal ECD to be input to and written into the E.12.

First, the auxiliary information data generating means 22d
This configuration is as shown in FIG. As shown in FIG. 3, the auxiliary information data generating means 22d
Is a NAND logic gate 2 having three negative logic inputs.
2a, an OR logic gate 22b, and a logic circuit 22c. The logic circuit 22c has a logic function as shown in a truth table shown in the diagram of FIG. 4, and outputs the status signal RS1.

In this embodiment, when the status signal to be stored in the reception status FIFO 14 is not compressed, the status signal is a 3-bit signal. That is, the status signal of 3 bits corresponds to the N signal.
The control signal R output by the AND logic gate 22a and the control signal E output by the serial / parallel converter 16
OF and a control signal ER2 output from the OR logic gate 22b. In this case, the logic circuit 22c only needs to have a function of generating the status signal RS1 <1>.

When the status signal stored in the reception status FIFO 14 is data-compressed, it becomes a 2-bit status signal in this embodiment. That is, the 2-bit status signal is the status signal RS
It is one.

In the HDLC procedure, the fraction data is generated only at the time of EOF. Therefore, only in the case of EOF, the presence or absence of fraction data is significant. For this reason,
Since the control signal R has a meaning only when the control signal EOF is in the H state, it is sufficient that the state of the control signal R can be determined only in the case of the EOF. In this embodiment, attention is paid to such a point, and three bits of the control signals R, EOF, and ER2 are data-compressed into the two-bit control signal RS1. By such data compression, the reception status FIFO 14 is originally (3 bits × 102 bits).
(2 words x 1)
024 bytes), and a total of 10
It is possible to reduce the storage capacity of 24 bits.

Next, the detailed information data generating means 22e
Generates the detailed information data ECD as shown in FIG. 5 when at least one of the control signals CRCE and OVRE is in the H state. The detailed information data EC
D is input to the selector 24. In particular, when one of these control signals CRCE or OVRE goes to the H state, the status signal RS1 <1> output from the logic circuit 22c goes to the H state, and the selector 24 transmits the generated detailed information data ECD. select. Therefore, the generated detailed information data ECD output by the detailed information data generating means 22e is replaced with the reception data RD1 output by the serial / parallel conversion unit 16,
The received data is written into the FIFO 12.

In this detailed information data ECD, as shown in FIG. 5, the logic state of the control signal OVRE is written in bit B5. Bit B6 contains the control signal C
The logic state of RCE is written. The logic state of the control signal EOF at the time of occurrence of the overrun error or the CRC error is written to the bit B7. As described above, the detailed information data ECD includes these control signals CRC.
When at least one of E or OVRE is in the H state, and when at least one of the CRC error or the overrun error occurs, it is detailed information data for identifying which error or EOF has occurred. .

When neither the CRC error nor the overrun error occurs, the detailed information data ECD is not generated even if an EOF occurs. Therefore, information indicating that such an EOF has occurred is stored in the reception status FIFO 14.

Next, the detailed information data generating means 22e
In the case where the fraction data is generated and EOF is set, No. in FIG. The reception data ECD shown in 2 to 8 is generated. Note that, in FIG. 1 is a case where the fraction data is not generated.

As described above, when the fraction data is generated, as shown in FIG. 6, the status signal RS1 <1> shown in FIG. 3 also goes to the H state. Therefore, the selector 24 has the No. The detailed information data ECD of 2 to 8 is selected and written in the received data FIFO 12.

Here, the received data ECD shown in FIG.
The “x” shown in the above indicates the data R in accordance with the digital data RXD received from the transmission line among the fractional data.
This is a valid data portion of D1. On the other hand, FIG.
In the received data ECD, the bit indicated by “0” or “1” indicates a bit pattern indicating that the invalid bit data is invalid bit data. In this embodiment, when the fraction data is generated, the invalid bit data adjacent to the valid bit data is set to “0”, and all other invalid bit data are set to “1”.
And

Here, the reception status FIFO 14
According to the control signal R or RS1 stored in
When the occurrence of fractional data is identified, the received data ECD stored in the received data FIFO 12 is "0" on the LSB (least significant bit) side.
MSB (most significa
The bit on the (nt bit) side is valid bit data as received data.

As described above, in this embodiment, when the fraction data is generated, the reception status FIFO 14
Stores only information in a range in which the occurrence of the fraction data can be identified. Further, the reception data FIFO 12
The number of valid bits in the fraction data stored in the reception data FIFO 12
To the invalid bit data of the fraction data written to
It can be identified by writing a predetermined bit pattern. Therefore, the reception status FIFO 14
No more detailed information of a plurality of bits, such as the RE1 bit data B0 to B2 of 11, need be written, and the storage capacity of the reception status FIFO 14 can be reduced.

FIG. 7 is a logic circuit diagram showing the status decoder.

The status decoder 26 outputs three bits of the reception data RD2 called from the reception data FIFO 12 as necessary, ie, RD5, RD6 and R
While using D7, the status signal RS2 read from the reception status FIFO 14 (each of the two bits is RS20 on the LSB side and RS21 on the MSB side).
), And outputs the control signals REOF, RCRCE and ROVRE, and the 3-bit control signal RE2.

In FIG. 7, control signal RS2
0 is the LSB side of the status signal RS2 output from the reception status FIFO 14. The control signal RS21 is on the MSB side of the status signal RS2.

The control signal REOF indicates that an EOF has occurred. The control signal RCRCE indicates that a CRC error has occurred. The control signal ROVRE indicates that an overrun error has occurred. The control signal RE2 is the same as the control signal RE1 output from the fraction information encoder 18 shown in FIG. 6, and indicates the effective bit number N of the fraction data.

First, as shown in FIG. 7, the status decoder 26 includes an AND logic gate 26a having one input having a negative logic, and AND logic gates 26c, 26d, 26
f, 26g and an exclusive OR logic gate 26b
, OR logic gate 26e, fraction code encoder 2
6h.

Note that the fraction code encoder 26h is
A priority encoder is used. As a result, the control signal RE2 (see FIG. 6) from the reception data RD2 read from the reception data FIFO 12, which is equivalent to the detailed information data ECD shown in FIG.
(Equivalent to RE1 of the above).

For example, the detailed information data E shown in FIG.
As is clear from the correspondence between CD and the control signal RE1,
When the LSB side of the reception data RD2 is “0”,
The control signal RE2 (or RE1) becomes "111 (binary number)". When the second bit from the LSB is “0”, it becomes “110”. When the third bit from the LSB side is “0”, the control signal RE2 becomes “101”.

The status decoder 26 shown in FIG. 7 is connected to the exclusive OR logic gate 2
6b, the AND logic gates 26c and 26d, and the OR logic gate 26e generate the control signal REOF indicating whether EOF has occurred.

Next, the AND logic gate 26c outputs the CR signal based on the control signals RS20 and RS21.
It is determined whether a C error or the OVR error has occurred. The output of the AND logic gate 26f and the output of the AND logic gate 26c generate the control signal RCRCE indicating that a CRC error has occurred. Further, the A
The ND logic gate 26g and the output of the AND logic gate 26c output the control signal ROV indicating the OVR error.
RE is being generated.

The control signals REOF, RCRCE
When generating the ROVRE and the bit data RD5 to RD of the bit B5 to bit B7 of the reception data RD2 read from the reception data FIFO 12 and allocated in the same manner as the bits B5 to B7 of FIG.
7 is used.

As described above, according to the present embodiment,
Applying the present invention, the reception status FIFO stores only more compressed bit data based on only the occurrence of the EOF, the occurrence of the overrun error, or the occurrence of the CRC error. Let me. Further, the data stored in the reception data FIFO 12 is used for the EOF or which error has occurred. For this reason, the bit length of one word of the reception status FIFO 14 can be further reduced. For example, the reception status F shown in FIG.
The storage capacity of the IFO 14 can be reduced to 3 bits per word or 2 bits per word. Therefore, for the reception status FIFO 14, the storage capacity of ((6−3) × 1024 = 3072) bits is reduced, or ((6−2) × 1024 = 40).
96) The storage capacity of bits can be reduced.

[0094]

As described above, according to the present invention,
An excellent effect can be obtained in that the storage capacity required for the FIFO used as the reception buffer can be reduced, thereby reducing costs and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital data receiving apparatus to which the present invention has been applied.

FIG. 2 is a block diagram showing a configuration of a status encoder used in the embodiment.

FIG. 3 is a logic circuit diagram showing auxiliary information data generation means used in the status encoder of the embodiment.

FIG. 4 is a diagram of a truth table showing a function of the detailed information data generating means of the status encoder of the embodiment.

FIG. 5 is a diagram showing data related to an error written to a reception data FIFO from the status encoder of the embodiment.

FIG. 6 is a diagram showing data relating to fraction data written from the status encoder of the embodiment to a reception data FIFO;

FIG. 7 is a logic circuit diagram of a status decoder used in the embodiment.

FIG. 8 is a diagram showing a format of a message in the HDLC procedure.

FIG. 9 is a block diagram showing a configuration of a conventional digital data receiving device.

FIG. 10 is a diagram showing a data structure taken into a reception data FIFO in the digital data receiving apparatus of the embodiment or the conventional example.

FIG. 11 is a diagram showing a configuration of bit data in a reception status FIFO of the conventional example.

FIG. 12 is a logic circuit diagram showing a fraction information encoder used in the embodiment or the conventional example.

FIG. 13 is a time chart showing the operation of the fraction information encoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... FIFO control part 12 ... Reception data FIFO 14 ... Reception status FIFO 16 ... Serial-parallel conversion part 18 ... Fraction information encoder 18a ... 3-bit binary counter 22 ... Status encoder 22d ... Auxiliary information data generation means 22e ... Detailed information data generation means 24 ... selector 26 ... status decoder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 13/00 H04L 29/00

Claims (3)

(57) [Claims] A plurality of digital data sequentially received from a transmission path are first temporarily stored in a reception data FIFO, and auxiliary information indicating information on an error or the like occurred for each of the received digital data. In a digital data receiving apparatus in which information data is temporarily stored in a reception status FIFO while corresponding to the corresponding digital data, the received digital data becomes invalid data due to an error or the like. Sometimes the receiving stator
Auxiliary information data generating means for generating the auxiliary information data indicating whether or not the error has occurred , stored in the received data FIFO, and storing the data in the received data FIFO instead of the invalid data
And a detailed information data generating means for generating detailed information on the error that has occurred. 2. The method according to claim 1, further comprising focusing on mutual exclusion of the occurrence or non-occurrence of a plurality of types of errors that can occur with respect to the auxiliary information data. An auxiliary information data compressing unit for performing data compression; and an auxiliary information restoring unit for performing data expansion of the data compressed auxiliary information data read from the reception status FIFO using the detailed information. Digital data receiving device. 3. The method according to claim 1, wherein the plurality of digital data sequentially received from the transmission path are received in a bit stream state based on an HDLC procedure. , A series of a plurality of word memories each having a bit width L. Further, when temporarily storing the digital data sequentially received from the transmission path in the reception data FIFO,
While sequentially dividing the digital data in the bit stream state by the length of the bit width L, the reception data FI
A data conversion unit for writing to the FO, and a division by the data conversion unit and the reception data FIFO
At the time of writing to the received data FIFO, at the end of the digital data received in a bit stream state, when writing fraction data less than the bit width L to the reception data FIFO, the occurrence of the fraction data is determined. Fraction information generating means for generating the auxiliary information data shown in the auxiliary information data generating means, wherein, when the fraction data is generated, a fraction bit for generating information indicating the bit number N of the fraction data as the detailed information A digital data receiving apparatus, comprising a number information generating means in the detailed information data generating means.