JP3268615B2 - Manufacturing method of package parts - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The leads to be connected to the electronic components of the electrode to a method of manufacturing a package part products to form the external connection terminals.

[0002]

2. Description of the Related Art FIG. 31 is a cross-sectional view showing a bonding process of an electrode of an LSI chip using wire bonding and a substrate on which leads connected to the electrode are formed, according to a conventional technology. In the figure, 1 is an LSI chip, 2
Is an electrode of the LSI chip 1, 3 is a lead, 4 is a substrate, for example, a glass epoxy substrate, and the lead 3 is formed on the substrate 4. A bonding wire 5 connects the electrode 2 and the lead 3.

[0003] A process of joining the electrodes of the LSI chip to the leads formed on the substrate will be described. The LSI chip 1 is die-bonded to a predetermined position of the substrate 4 with an adhesive or the like with the LSI electrode 2 facing upward (a), and the portion of the lead 3 of the substrate connected to the LSI electrode 2 is Au or the like. (B).

FIG. 32 shows another conventional joining process for joining an electrode of an LSI chip and a lead formed on a polyimide tape, and furthermore, a QTP (Quad-Flat Tape-Carrier Package) or a LTP by this joining process.
It shows a manufacturing process of a package component such as a CC (Leadless Chip Carrier). QTP is a package component that conducts to the LSI chip using copper foil leads formed on a polyimide tape, while LCC is connected to the LSI chip by using wiring formed on a small substrate made of glass epoxy or BT resin. This is a package component that conducts the current. In the figure, 6 is an Au bump formed on an electrode of an LSI chip, 7 is a polyimide tape having leads 3 formed on the upper surface in advance, 8 is a sealing resin for sealing the LSI chip 1, and other symbols are those in FIG. Is the same as

In the figure, bonding is performed using bumps formed on the ends of the electrodes or leads of the LSI chip. For example, a bump 6 made of Au is formed on the electrode 2 of the LSI chip 1 (a), mounted on a position where the electrode 2 is bonded to the lead 3 on the polyimide tape 7, and bonded by pressing (b). Further, the polyimide tape 7 is removed leaving a predetermined portion in accordance with the size of the package component to be formed (c), and sealing resin 8 is applied to both sides of the remaining polyimide tape so as to seal the LSI chip 1. Is formed and, if necessary, the leads 3 are formed to manufacture the QTP (d).

In forming an LCC, for example, a glass epoxy substrate 4 is used instead of the polyimide tape 7 in FIG. In the same process up to FIG. 32 (c), the sealing resin 8 is formed so as to further seal the LSI chip 1, while the leads 3 are formed into a predetermined shape along the glass epoxy substrate to form the LCC. . Package components such as QTP and LCC are not limited to the above Au bumps.
As in the case of 1, it is also formed by wire bonding.

[0007]

Conventionally, as described above, in the case of wire bonding, the speed and thickness of electronic components are limited due to the length and height of the bonding wire. There is a problem that the distance between adjacent electrodes is required to be at least about 100 μm for wire bonding, which has been an obstacle to miniaturization and increase in the number of pins.
There was a problem that chips were cracked.

For example, FIG. 33A is a conceptual diagram of an LSI chip wire-bonded on a substrate, and FIG.
Shows a cross-sectional view thereof. As shown in FIG. 33A, at least 100 μm is required for wire bonding.
A lead interval 51 of about m is required. (B)
As shown in the figure, the height 52 of the bonding wire 5 is larger than that of the bump bonding, and the bonding
Was occurring.

FIG. 34 is a sectional view of an LSI chip bump-bonded on a polyimide tape on which leads are formed. In the figure, reference numeral 8a denotes a bump formed at a normal height, and 8b denotes a bump formed lower than the bump 8a having a normal height. In FIG. 34A, since the bumps 8a and 8b have variations in height, there is a problem that an unbonded portion 54 is generated after pressing and bonding as shown in FIG. 34B. Even if all bumps 8 are formed at the same height, as shown in FIG.
Since the mounting position of the LSI chip 1 is shifted with respect to the above, a bridge failure 55 occurs as shown in FIG. When mounting such an LSI chip on a substrate with the electrodes facing each other, there has been a problem that a connection failure occurs due to a displacement during mounting.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and facilitates connection with electrodes of small electronic components such as an LSI chip, and connection with multi-pin electrodes, so that package components can be easily obtained. It is an object of the present invention to provide a method of manufacturing a package component which does not cause a contact failure between an electrode of a mounted electronic component and a lead connected thereto and does not cause cracking of the electronic component at the time of connection.

Further, in a package component on which a plurality of electronic components are mounted, even when an electrode of the electronic component is connected to an electrode of another component, a package for preventing poor connection of the connection and cracking of the electronic component is similarly provided. An object of the present invention is to provide a method for manufacturing a component.

[0012]

According to a method of manufacturing a package component according to the present invention, a resin layer is formed on the electronic component and the substrate after arranging the electronic component on a substrate with the electrodes of the electronic component facing the front. And forming a conductive layer on the surface of the resin layer as a lead connected to an electrode of the electronic component, and forming the lead into an external connection terminal.

Further, according to the method of manufacturing a package component according to the present invention, the electronic component and the substrate are disposed such that the electrodes of the electronic component face up and the resin layer is applied to the electronic component and the substrate so as to cover the electrodes. Forming an opening for exposing the electrode in the resin layer; forming a conductive layer on the surface of the opening and the resin layer as a lead connected to the electrode of the electronic component; and Is formed into an external connection terminal.

Further, in the method of manufacturing a package component according to the present invention, the electronic component and the lead connected to the electrode of the electronic component may be disposed on the substrate after the electronic component is disposed on the substrate with the electrodes of the electronic component facing up. And a step of forming the lead into an external connection terminal.

Further, in the method of manufacturing a package component according to the present invention, a step of fixing the electronic component to a predetermined position on the substrate so that the electrode of the electronic component faces one surface of the substrate; Forming an opening exposed on the back surface in the substrate, forming a conductive layer serving as a lead connected to an electrode of an electronic component in the opening, and forming the lead into an external connection terminal It is.

[0016]

According to the above-mentioned method for manufacturing a package component, after the electronic components are arranged on the substrate with the electrodes facing up, a resin layer is formed on the electronic component and the substrate, and a conductive layer is formed on the surface of the resin layer. Thereby forming a lead connected to the electrode,
Furthermore, since the lead serves as an external connection terminal, the electronic component is fixed to the substrate so that there is no displacement during mounting.In addition to forming the lead serving as the external connection terminal, the lead is joined to the electrode, Connection failure and damage to electronic components are eliminated.

Further, after the electronic component is arranged on the substrate with the electrodes facing up, a conductive layer is formed on the electronic component and the substrate, and the conductive layer forms a lead connected to the electrode of the electronic component. Even without the resin layer forming step, similarly, no displacement occurs when mounting the electronic component on the substrate, the lead formation and the electrode bonding are performed in the same process, and the connection failure and the electron Eliminates damage to parts.

Further, when connecting the first electrode of the electronic component to the second electrode of another electronic component, each of the electrodes is turned upside down, and after these electronic components are arranged on the substrate, the distance between the electrodes is reduced. Since the wiring is formed by forming a conductive layer on the substrate, a resin layer forming step is not required, and similarly, there is no displacement when the electronic component is mounted on the substrate, and a connection failure at the time of connection between the electrodes. And breakage of electronic components.

After the electrodes are opposed to the substrate and the electronic components are fixed, an opening for exposing the electrodes is provided, and a lead for forming a conductive layer is formed in the opening, so that the electrodes are opposed to the substrate. At the same time, even when electronic components are mounted on a board, the electronic components do not shift during mounting, and lead formation and electrode bonding are performed in the same process.
In addition, poor connection or breakage of electronic components during bonding with the electrodes is eliminated.

[0020]

[Embodiment 1] FIG. 1 is a process diagram showing a manufacturing process of a package component, for example, QTP or LCC, showing one embodiment of the present invention. In the figure, 1 is an LSI chip, 2 is an electrode of the LSI chip, 7 is a polyimide tape serving as a substrate on which the LSI chip 1 is mounted, and 10 is an epoxy formed on the LSI chip 1 and the polyimide tape 7 excluding the electrode 2. Resin, 13 is a conductor forming a lead of a package component, 14 is LS
It is a sealing resin for sealing the I chip 1.

A method of manufacturing the package component having the above configuration will be described. As shown in FIG. 1A, the LSI chip 1 is mounted with the surface having electrodes at predetermined positions on the polyimide tape 7 facing up (hereinafter referred to as face-up). When fixing the LSI chip 1, it is fixed with an epoxy adhesive.
The epoxy resin 10 is supplied from the electrode 2 to the polyimide tape 7 by using a dispenser (b), and is further subjected to electroless copper plating to form a conductor 13 from the electrode 2 on the surface of the epoxy resin 10 and further on the polyimide tape 7. (C). FIG. 2 is a perspective view at the time of the step of FIG. As shown in FIG. 2, the conductor 13 is formed so as to become the lead 8 connected to the electrode 2. As a forming method, a substance serving as a catalyst for promoting electroless plating (hereinafter referred to as a nucleus of electroless plating) is previously attached to a portion where the lead is to be formed, and then immersed in a plating solution. The conductor 13 is formed in the portion. For example, electroless copper plating is used, and palladium colloid is used as its core. Next, unnecessary portions of the polyimide tape are removed (d), the remaining lead portions are formed, and the LSI chip is covered with the sealing resin 14 to form QTP as a package component (e).

FIG. 1F is a sectional view of an LCC which is another package component. In the LCC, a glass epoxy substrate 4 as an LCC substrate is used instead of the polyimide tape 7. FIG. 1 (a) in a case where the forming process is QTP.
(D), and finally, the lead 8 may be formed along the substrate 14 to a predetermined portion on the back surface as shown in (f).

Conventionally, predetermined leads are formed on a polyimide tape in advance, and the leads and the electrodes on the LSI chip are joined, so that the lead formation and electrode connection are separate processes. As in the present embodiment, the electrodes can be connected together with the formation of the leads, and the formation process is further simplified. In addition, due to the above-described lead formation method, misalignment caused when mounting a small LSI chip having a multi-pin electrode, cracking caused by wire bonding or the like, and poor connection between the lead and the electrode as in the related art. Is also gone. Furthermore, since the conductor is formed by plating or the like, a thin package component can be manufactured.

Here, the conductor 13 serving as a lead is formed by electroless copper plating. However, it is also possible to form a lead by vapor deposition of gold, silver, copper, or the like, or to form a lead by ICB (Ion Cluster Beam). It can also be obtained by direct drawing.

Embodiment 2 FIG. FIG. 3 shows a method of connecting between the electrodes of the LSI chip when a plurality of LSI chips are mounted on the package component.
This is a case where the electrode 2b on the chip 1b is electrically connected. Further, it is assumed that leads serving as external connection terminals are formed from the electrodes 2c on the LSI chips 1a and 1b. The epoxy resin 10 is formed on the polyimide tape 7 in the same manner as the lead formation. At this time, the epoxy resin 10 is formed so that the electrode 2a and the electrode 2b have a continuous structure. Thereafter, a conductor for connecting the electrode 2a and the electrode 2b through the surface of the epoxy resin 10 is formed, whereby the wiring 15 is formed. The conductor 13 to be a wiring connected between the electrodes is formed by the same method as that of the lead formation of the first embodiment, such as electroless copper plating.

The steps up to the above are shown in FIGS.
This is performed in the same step as (c). Further, the subsequent steps of manufacturing the package component are the same as those shown in FIG.
As described above, a package component having a high mounting density in which a plurality of LSI chips are mounted is formed while simplifying the process. In addition, other electric components such as a capacitor and a resistor other than the LSI chip can be similarly bonded.

Further, as shown in FIGS. 4A and 4B, the connection between the electrode 2a of the electric component such as an LSI chip and the pad 2b on the substrate also has a continuous structure of the electrode 2a and the pad 2b. The resin layer 10 is formed as described above.
This can be achieved by forming a conductor on the surface of the zero. In this case, similarly, it is possible to prevent connection failure and breakage of the LSI chip in conventional wire bonding.

Embodiment 3 FIG. FIG. 5 is a process chart showing a method of manufacturing a package component such as QTP and LCC according to another embodiment of the present invention. In the figure, 10a is an ultraviolet curing resin film, 11 is an opening for exposing the electrode 2, 12 is an electroless copper plating film, and the others are the same as those in FIG.

A method for manufacturing the package component of this embodiment will be described. As shown in FIG. 5A, the LSI is located at a predetermined position.
The chip 1 is fixed face up using an epoxy adhesive. An ultraviolet light curable resin film 10a (40 μm thickness) is formed on the entire surface of the LSI chip 1 and the polyimide tape 7 using a spin coater (b), and an opening 11 for exposing the electrode 2 to the surface by photolithography is provided ( c). Then, electroless copper plating is performed on the entire surface of the coating film 10a of the ultraviolet light curable resin to form a plating film 12 (d), and thereafter, a necessary portion is selectively removed by photolithography, leaving only the lead portion 13 ( e). For example, unnecessary portions of the plating film 12 are removed so as to form leads connected to the electrodes as shown in FIG. Further, unnecessary portions of the polyimide tape 7 and the ultraviolet curable resin 10a are removed (f), lead molding is performed, and a package is formed with the sealing resin 14 to form a QTP (g). In the case of forming an LCC, the LCC substrate 4 is used in place of the polyimide tape 7 and the lead is formed as shown in FIG. . Therefore, similarly to the first embodiment,
It can prevent misalignment when mounting the LSI chip on the substrate and poor connection between leads and electrodes.
No chip breakage.

In the above method, the ultraviolet light curable resin film 10
Although a was formed using a spin coater, it can be formed by bonding a dry film. Although the openings 11a and 11b are formed by using photolithography, they can also be formed by ablation using an excimer laser, a carbon dioxide laser, and a YAG laser. In this case, an epoxy resin film may be used instead of the ultraviolet light curable resin film 10a. The lead portion 13 can also be obtained by direct evaporation using gold evaporation or a conductive paste.

Embodiment 4 FIG. FIG. 6 shows a method of mounting a plurality of LSI chips on a polyimide tape and joining the electrodes of the LSI chips as in FIG. In the figure, this is a case where the electrode 2a on the LSI chip 1a and the electrode 2b on the LSI chip 1b are electrically connected. In addition, LSI
It is assumed that leads serving as external connection terminals of the package component are formed from the electrodes 2c on the chips 1a and 1b, respectively. After mounting and fixing the LSI chips 1a and 1b at predetermined positions of the polyimide tape 7, the ultraviolet light curable resin 10
a is applied over the entire surface. After an opening is provided in the resin 10a so that the electrodes 2a and 2b are exposed on the surface, electroless copper plating is further performed thereon, and the plating film is selectively removed while leaving a necessary portion of the plating film. The lead 13 is further formed, and the wiring 15 for connecting the electrode 2a and the electrode 2b is formed.
In this step, the wirings 15 and the leads 13 may be formed directly with the conductive paste. The steps so far are shown in FIGS.
Step (d) is performed in the same step, and when a package component is further formed, it is performed in the same step as the steps after FIG.

As described above, by joining the LSI chip to the polyimide tape which is a substrate and forming leads, or by connecting the electrodes of a plurality of LSI chips, misalignment at the time of mounting and poor connection of leads and wirings are achieved. A package component such as a QTP or LCC without the defect can be obtained.

FIG. 7 shows a method of connecting the electrodes of the LSI chip and the pads of the substrate in the same manner as in this embodiment. In the figure, an LSI chip 2 is placed at a predetermined position on a substrate 4 and an ultraviolet light curable resin 10a (40 μm in thickness) is formed, and then the electrodes 2 of the LSI chip 1 and the pads 2b of the substrate 4 are exposed on the surface. Form a part. Thereafter, an electroless copper plating film is formed, and the plating film is selectively removed so as to form the wiring 13 connecting the electrode 2a and the pad 2b.
Alternatively, the wiring 13 may be directly formed by gold deposition or conductive paste. According to the above method, the displacement at the time of mounting the LSI chip and the bonding failure at the time of connection between the electrodes are eliminated.

The method of connecting electrodes and pads can also be used when a package component is formed by mounting an LSI chip on a substrate on which leads connected to the pads 2b are formed in advance.

Embodiment 5 FIG. FIG. 8 is a process chart showing a manufacturing process of a package component such as QTP, LCC and the like according to another embodiment of the present invention. In FIG. 5 of the third embodiment, the UV curable resin
Although the opening 11 was formed by applying the entire surface to the I chip 1 and the polyimide tape 7, in this embodiment, the lead is formed by directly applying the electroless copper plating film 12 to the LSI chip 1 and the polyimide tape 7. Things. 8, the reference numerals are the same as those in FIG.

First, as shown in FIG.
The SI chip 1 is fixed face up using an epoxy adhesive. Then, as shown in (b), electroless copper plating is performed on the surface to form a plating film 12, and then (c)
As shown in FIG. 5, the lead is selectively removed by photolithography to leave only the lead portion 13. Unnecessary portions of the polyimide tape 7 are removed as shown in (d), lead molding is performed as shown in (e), and packaged with the sealing resin 14 to obtain QTP. Also, as shown in (f), an LCC can be obtained by performing necessary lead molding using the LCC substrate 4 instead of the polyimide tape 7. In addition, the step (b) can be omitted, and the lead portion 13 can be obtained by direct evaporation using gold evaporation or a conductive paste. With this method,
By joining the LSI chips and forming the leads, a QTP or LCC free from displacement and bonding failure at the time of mounting can be obtained, and a step of forming a resin layer on the polyimide tape 7 is unnecessary, which is different from the case of the second embodiment. The process is simplified.

Embodiment 6 FIG. FIG. 9 shows wiring between electrodes of a plurality of LSI chips mounted on a polyimide tape. The formation method is the same as that of FIG. That is, the LSI chips 1a, 1b
And fix it with an adhesive, directly apply electroless copper plating thereon, and selectively remove the necessary portions of the formed plating film, leaving the wiring 15 connecting the electrodes 2a and 2b, the electrode 2c Is formed. Or LS
After the I-chip is fixed, wirings and leads may be formed directly with a conductive paste or the like.

FIG. 10 shows a case in which the electrode of the LSI chip mounted on the substrate is connected to the pad 2b of the substrate. Similarly, the electroless copper plating is selectively removed between the electrode 2a and the pad 2b. Or the wiring 13 with a conductive paste.
Get. The method for connecting the electrodes and the pads can be used also when a package component is formed by a substrate on which leads for connecting to the pads are formed in advance.

Embodiment 7 FIG. FIG. 11 shows another embodiment of the present invention, QTP or LCC.
FIG. 7 is a process chart showing a method of manufacturing a package component such as the above. In the figure, reference numeral 11a denotes an opening formed in the polyimide tape 7 for exposing the electrodes, and other reference numerals denote the third embodiment.
5 is the same as FIG.

A method of manufacturing a package component according to this embodiment will be described. First, as shown in FIG.
The surface of the electrode 2 of the SI chip 1 has a polyimide tape 7
Face to face (hereinafter called face down)
Place and fix using epoxy adhesive. next,
(B) As shown in FIG.
An opening 11a is formed at a location corresponding to the position by an excimer laser to expose the electrode 2. As shown in (c), a plating film 12 by electroless copper plating is formed on the back surface of the polyimide tape 7 together with the opening 11a.
Selective removal by photolithography as shown in (d),
While leaving only the lead portion 13 connected to the electrode 2, the unnecessary portion of the polyimide tape 7 is further removed, and the lead is formed as shown in (e) and packaged with the sealing resin 14 to form QTP. Also, as shown in (f), an LCC is obtained by using the LCC substrate 4 instead of the polyimide tape 7 and molding the leads 13 in the same manner as described above, and removing unnecessary portions of the substrate 4 and the leads 13. Here, in the step (b), an excimer laser is used for the opening 11, but a carbon dioxide laser or a YAG laser may be used.
Further, before fixing the LSI chip 1 to the polyimide tape 7, an opening 11 is formed in a portion corresponding to the electrode 2 in advance.
May be formed.

By bonding the LSI chips and forming the leads as described above, when mounting the semiconductor chip face down on the substrate as in the related art, bonding using bumps made of Au or the like is unnecessary, and the mounting time is reduced. Q without displacement and poor connection
TP and LCC are obtained.

Embodiment 8 FIG. FIG. 12 shows a method in which a plurality of LSI chips are mounted on a polyimide tape and the electrodes of the LSI chips are joined. In the figure, this is a case where the electrode 2a on the LSI chip 1a and the electrode 2b on the LSI chip 1b are electrically connected. Also, the LSI chip 1a,
It is assumed that the lead of the package component is formed from the electrode 2c on 1b. The LSI chips 1a and 1b are mounted face-down on predetermined positions of the polyimide tape 7 and fixed. After an opening is provided at a position corresponding to the electrodes 2a and 2b from the back surface of the polyimide tape 7, a plating film by electroless copper plating is further formed on the back surface of the polyimide tape 7 together with the opening, and a necessary portion of the plating film is formed. , The lead 13 is removed from the electrode 2c.
Further, a wiring 15 connecting the electrodes 2a and 2b is formed. The steps so far are performed in the same steps as in FIGS. 11A to 11D, and thereafter, the steps for manufacturing the package component are performed in the same manner as in FIG. 11E.

FIG. 13 shows an LSI in the same manner as in this embodiment.
FIG. 4 shows a method of connecting a chip electrode and a pad formed on a substrate. In the figure, the LSI chip 2 is mounted face down on a predetermined position on the back surface of the surface of the substrate 4 having the pad 2 b, and an opening is formed so as to be exposed on the electrode 2 of the LSI chip 1 and the surface of the substrate 4. Thereafter, an electroless copper plating film is formed so as to fill the opening, and a wiring 13 connecting the electrode 2a and the pad 2b is formed by selectively removing the plating film. In addition, this wiring 13 may be directly formed by gold evaporation or a conductive paste instead of this method. According to the above method, the displacement at the time of mounting the LSI chip and the bonding failure at the time of connection between the electrodes are eliminated.

The above-described electrode-pad connection method can also be used when a package component is formed by mounting an LSI chip on a substrate on which leads connected to the pad 2b are formed in advance.

Embodiment 9 FIG. FIG. 14 is a process diagram showing a case where leads and wires are directly formed without forming leads and wires by selective removal of the plating film formed as in the above-described embodiment. In the figure, reference numeral 22 denotes a direct drawing nozzle of a direct drawing apparatus for supplying a copper paste.

The figure shows a case in which the electrode 2a of the LSI chip is connected to the pad 2b on the substrate. First, the LSI chip 1 is fixed at a predetermined position face up using an epoxy adhesive as shown in FIG. I do. Then, as shown in (b), an ultraviolet curable resin film 10a (40 μm) is formed using a spin coater, and as shown in (c), an opening 11 is formed by photolithography, and the electrode 2a and the pad 2b are formed. To expose. Then, as shown in (d), the copper paste 13a is supplied to necessary portions by using a direct drawing apparatus, and (e).
A wiring portion 13b is formed as shown in FIG. Further, although the copper paste 13a is used, a gold paste or a silver paste can be used. Thus, by bonding the LSI chips, it is possible to obtain bonding between the electrodes of the LSI chip and the pads of the substrate without bonding defects due to positional displacement during mounting.

This is not only due to the connection between the electrodes, but also
A lead connected to an electrode on the SI chip may be formed, and this may be used in a manufacturing process of a package component formed on an external connection terminal.

Embodiment 10 FIG. FIG. 15 is a process diagram showing an embodiment in which wirings and leads are formed from a plating film, 16 is a dry film resist film, 17 is ultraviolet light, 18 is a photomask, and leads for connecting to the electrodes 2 of the LSI chip 1 are shown. Is formed.

For example, in the case of the third embodiment, an ultraviolet light curable resin 10a is applied to the entire surface of the LSI chip 1 and the substrate 4 and an opening for exposing the electrode 2 is formed, as shown in FIG. An electroless copper plating film 12 is formed, and the plating film 12 is coated with a dry film resist 16 as shown in FIG. Using a photomask 18 that transmits ultraviolet light in a portion to be left as a wiring or a lead, ultraviolet light 17 is exposed in the direction of the arrow as shown in FIG. The portion not irradiated with ultraviolet light is removed using a 1% aqueous solution of sodium carbonate. As shown in (d), the hardened dry film resist 16a remains only in the exposed portion, and when the exposed electroless copper plating film 12 is further etched, a necessary portion of the plating film 12 remains as shown in (e). Finally, the cured dry film resist is peeled off to form the leads 13 as shown in FIG. Although the dry film resist 16 is used here, it is also possible to use an ultraviolet curing photoresist resin. In this manner, by joining the LSI chips, the electrodes and leads of the LSI chip can be joined to the leads at the same time as the formation of the leads without any joining failure due to displacement during mounting, and the joining and the lead formation are performed accurately.

In addition to the above, the method of this embodiment may be used in the first to eighth embodiments in which leads and wiring between electrodes of an LSI chip are formed.

Embodiment 11 FIG. In the tenth embodiment, ultraviolet light is applied to a necessary portion for wiring, lead and the like with a dry film resist using a photomask, but in the present embodiment, a case where the dry film resist is directly irradiated with the ultraviolet light will be described. . FIG. 16 is a process diagram for forming a lead connected to the electrode 2 of the LSI chip, and 17a is an ultraviolet direct drawing beam.

In FIG. 16A, as in the tenth embodiment, the dry film resist 16 on the electroless copper plating film 12 is formed.
And direct writing beam 1 only for the part to be left as a lead
Irradiation is performed while scanning 7a as shown by a horizontal arrow in the figure. Further, when the portion not irradiated with the ultraviolet light 17 is removed using a 1% aqueous solution of sodium carbonate, a dry film resist 16b in which only the exposed portion is hardened remains as shown in FIG. Subsequent steps are the same as those shown in FIGS.

Embodiment 12 FIG. FIG. 17 is a process chart showing another embodiment for forming wirings and leads in the above embodiments. In the figure,
Reference numeral 20 denotes a palladium colloid serving as a core of electroless copper plating. In particular, this is a case where a wiring is formed between the electrode 2a and the pad 2b on the substrate.

First, as shown in (a), after applying the epoxy resin 10 to the entire surface of the LSI chip 1 and the substrate 4 as in the third embodiment, for example, (b) in a state where the electrodes 2a and the pads 2b are exposed. 2), the palladium colloid 20 is adhered to only the portion where the wiring is to be formed by using photolithography, and is immersed in a plating solution as shown in (c) to form an electroless copper plating film. To form When immersed in the plating solution, plating is formed at the location where the palladium colloid is applied, so that connection between the electrodes is accurately performed.

Here, the palladium colloid 20 is used as a nucleus for the electroless copper plating, but platinum or copper can be used as a nucleus by CVD or sputtering. Also, a lead connected to the electrode 2 of the LSI chip is formed,
It is also used when forming package components.

Embodiment 13 FIG. FIG. 18 is a process diagram showing another embodiment for forming wirings and leads in the above-described embodiments, and is a process diagram for forming wiring for connecting electrodes of an LSI chip and pads on a substrate. In the figure, reference numeral 21 denotes solder.

First, the LSI chip 1 is placed at a predetermined position on the substrate 4, and an ultraviolet curable resin 10a is applied from above. An opening for exposing the electrode 2a and the pad 2b is formed in the resin film 10a, a solder 21 is supplied to the opening, and then a wiring 13 is formed by electroless solder plating to connect the electrode and the pad. Next, it was left still on a hot plate at 200 ° C. for 2 minutes to melt the solder,
a portion and wiring 13, and pad 2 b portion and wiring 13
Are soldered, respectively. Here, as a method of heating the solder 21, it is also possible to irradiate the electrode 2 a or the pad 2 b portion from above the wiring 13 with a carbon dioxide gas laser or the like and heat it. As described above, by joining the LSI chip to the substrate using the solder, the joining strength between the electrode and the wiring portion can be increased. In addition to the wiring between the electrode and the pad, it is also used when forming a lead connected to the electrode 2 of the LSI chip to form a package component.

Although the method of supplying the solder 21 is the electroless solder plating, the solder paste can be supplied by a dispenser. For example, a solder paste containing platinum is supplied to the opening. By supplying a solder containing a catalyst such as platinum which serves as a nucleus of electroless plating, a copper plating film can be more reliably deposited on the solder, and disconnection failure can be prevented.

Further, gold may be supplied to the openings of the electrodes and pads instead of the solder. For example, it is supplied by a film of electroless gold plating. In this case, after the wiring 13 is formed, it is only necessary to press and adhere. By supplying a relatively soft metal such as gold to the electrode portion in this manner, conduction at the joint can be ensured.

Embodiment 14 FIG. FIG. 19 is a process chart of a method of manufacturing a package component according to another embodiment of the present invention. When forming a QTP in Examples 1 to 8, a conductor serving as a lead was formed on a polyimide tape while being bonded to an electrode,
Thereafter, the lead was formed into a desired shape to form an external connection terminal. In the present embodiment, when leads are formed so that a plurality of external connection terminals are aligned, variation in the shape of each external connection terminal is prevented. First, FIG.
Then, the LSI chip 1 is fixed to the polyimide tape 7 face up, and then the polyimide tape 7 is formed into a desired lead shape, for example, a gull wing shape as shown in FIG. After that, the leads 13 are formed as shown in (c) and sealed with the sealing resin 14 as shown in (d) to form a package. By manufacturing the QTP in this manner, it is possible to suppress the variation in the lead shape generated at the time of lead molding and to simplify the process.

Embodiment 15 FIG. FIG. 20 is a structural diagram of a QTP showing another embodiment of the present invention. In the figure, reference numeral 23 denotes a polyimide tape formed at the tip of the lead, and 24 denotes solder plating applied to the lead.

Conventionally, processed products of QTP are as shown in FIG.
A polyimide tape 23 is formed on a plurality of leads 13 formed as external connection terminals from the QTP main body as a fixing member for fixing these leads at the tip thereof. The polyimide tape 23 can prevent variations in lead height during lead molding. Normally, the lead 13 is moved from the state shown in FIG.
Is plated with solder 24. This makes the solder easy to wet when it is joined to another component with solder or the like. However, when soldering is performed with the polyimide tape 23 left at the tip of the lead 13, if the polyimide tape is heated and peeled off after bonding, as shown in FIG.
The lead 13 was exposed at the lead portion where the peeled polyimide tape 23b was disposed, and a defect such as corrosion occurred. Therefore, by forming the solder layer 24 also between the lead 13 and the polyimide tape 7 as shown in FIG. 4D, the lead 13 is not exposed even if the polyimide tape 23 at the tip of the lead is peeled off.

FIG. 21 is a process diagram showing a manufacturing process of a QTP in which the leads are not exposed at the portion of the separated polyimide tape 23b. In the figure, FIG. 21 (a) is the same as FIG. 5 (c). Next, as shown in (b), the solder layer is formed by pressing the solder sheet, and the surface of the solder layer 25 is further subjected to electroless copper plating to form the plating film 12. Thereafter, as shown in FIG. 3C, the plating film 12 and the solder layer 25 are selectively removed by photolithography so as to have a desired lead shape, thereby forming a lead 13. In (d), the polyimide tape 7 is removed from the QTP main body and the tip of the lead 13 formed as shown in FIG. 20 except for the polyimide tape 23, and the LSI is sealed with the sealing resin 14 as shown in (e). After the chip 1 is sealed, necessary lead molding is performed. Finally, solder plating 25a is applied to the lead portions not formed on the solder layer 12.

By implementing QTP as described above,
The entire surface of the lead is solder-plated, and a polyimide tape 23 is formed at the tip of the lead via the solder plating. Therefore, even if the polyimide tape 23 formed at the leading end of the lead is peeled off, the lead is not exposed and corrosion can be prevented.

Embodiment 16 FIG. FIG. 22 is a conceptual diagram showing a process of forming a LOC (Lead On Chip) as a package component according to another embodiment of the present invention. LOC is a form of QTP, especially L
This is a package component for forming a lead connected to an electrode formed at the center of the SI chip. Conventional LOC
As shown in FIG. 22 (a), the electrode 2 at the center of the LSI chip is
The lead 6 is formed on the polyimide tape 7 in advance, and the Au bump 8 at the tip of the lead 6 and the electrode 2 are joined by pressure bonding. In this case, it has been a problem that the formation of the bumps 8 is difficult and the rigidity of the leads is insufficient.

In order to alleviate the step between the polyimide tape and the LSI chip, as shown in FIG. 6B, a taper process is applied to the side of the opening of the polyimide tape 7 so as to provide an inclination (portion 7a). It is formed at a predetermined position. The LSI chip 1 is fixed to the opening of the polyimide tape 7. An electroless copper plating film 12 is formed on the entire surface as shown in FIG.
Is selectively removed to form a wiring 13 connecting the electrode 2 and the lead 6. Thereafter, as in the above-described embodiment,
Unnecessary portions of the polyimide tape 7 are removed, and leads are formed as needed to form LOC.
As described above, by manufacturing the LOC, the bump forming process can be omitted, and bonding of the LSI chips without displacement can be performed. Further, the structure in which the step between the opening and the LSI chip is buffered makes it easy to apply the electroless copper plating film uniformly. Also, as described above, without forming the leads 6 on the polyimide tape 7 in advance, the electroless copper plating 12 is applied directly to the polyimide tape 7 to form the leads to be connected to the electrodes 2 by selectively removing the plating film or the like. It is also possible.

Embodiment 17 FIG. In addition, at the time of forming the LOC in Example 16, a structure was formed in which the steps for mounting the LSI chip on the polyimide tape were alleviated. However, when forming a normal QTP or LCC, the side face of the LSI chip was formed. Create a step relief structure. FIG. 23 is a QTP manufacturing process diagram illustrating the present embodiment. In the figure, reference numeral 26 denotes an acrylic bump buffer, the height of which is 0.6 mm, which is the same as that of the LSI chip 1, and
It has an opening of the same size as the LSI chip 1 and the cross section of each side has a triangular shape to form a slope.

First, as shown in (a), the LSI chip 1 is fixed at a predetermined position of the polyimide tape 7 face-up using an epoxy-based adhesive, and the step buffer component 26 is aligned with the side surface of the LSI chip. And fix it. Then, as shown in (b), the coating 10a (40 μm)
m) is formed using a spin coater, an opening 11 is formed in the resin portion of the electrode 2 by photolithography, and the electrode 2 is exposed. Next, as shown in (c), the surface is subjected to electroless copper plating to form a plating film 12, and thereafter, as shown in (d), selective removal is performed by photolithography to leave only the lead portion 13.

By arranging the component for reducing the step of the LSI chip in this manner, the coating 10a and the electroless plating film 12 are easily formed at the step, and the photo for selectively removing the plating film 12 is removed. Defects such as insufficient light exposure in the lithography process can be avoided.

Here, the step buffering component 26 is fixed after the LSI chip 1 is fixed. However, the same effect can be obtained by fixing a component for buffering the step to the LSI chip in advance. It is also effective to taper the periphery of the LSI chip 1 instead of using the step buffer component 26. Further, instead of using the step buffer component 26, it is also effective to supply a highly viscous substance such as an epoxy resin to the step section by a dispenser and to cure the substance.

Embodiment 18 FIG. FIG. 24 is a manufacturing process diagram of QTP as a package component showing another embodiment of the present invention. In the figure, 10b
Is an ultraviolet light curable resin film, 13a and 13b are leads made of an electroless copper plating layer, 13c is a lead forming an external connection terminal of QTP, and 20 is a through hole for connecting the leads 13a and 13b.

The electrode arrangement of the LSI chip 1 is a convenient arrangement due to the structure of the internal circuit. However, if the electrode arrangement is inconvenient when mounted on a predetermined substrate, a desired electrode arrangement is formed by forming a laminated wiring structure in the package component. FIG. 24A shows FIG. 5 of the third embodiment.
It is formed by the steps (a) to (e). In (b), the resin film 10b is applied to the lead 13a or the resin film 1 such that a through hole 20 exposing a part of the lead 13a is formed.
0a. For example, after a resin film is formed on the entire upper surface, a portion of the resin film that will be a through hole is removed by photolithography. (C), through hole 2
The lead 13b is formed at a predetermined position of the resin film 10b so as to be connected to the lead 13a through the wire 0 and to form an external connection terminal at a desired external position of the QTP main body. This forming method is the same as that of the above-described embodiment, such as selective removal after electroless copper plating. Furthermore, as shown in (d),
Unnecessary polyimide tape 7 and resin coatings 10a and 10b are removed, sealing resin 14 is formed on both sides, and leads 13b are formed to form external connection terminals 13c. As described above, QTP in the manufacturing method of the present embodiment is obtained. Although the above example has a two-layer structure, a laminated structure of three or more layers may be used to form leads at desired external connection terminal positions.

Since a laminated wiring structure is formed while a plating film is formed on a resin film, even a small electronic component such as an LSI chip having multi-pin external terminals can easily arrange terminals different from those of the electronic component. And a package component free from poor connection can be obtained.

FIG. 25 is a configuration diagram in the case where FIG. 24 is applied to a BGA (Ball Grid Array) which is a package component, and similarly has a laminated wiring structure. 13c is a lead 13b
A mounting electrode 27 is formed on the electrode 13c so as to be connected to an external terminal. The figure has a three-layer structure. (B) is a perspective view of the BGA. By arranging the mounting electrodes 13c at required locations on the upper surface in a two-dimensional plane, the mounting density can be dramatically increased. According to the present embodiment, the mounting electrode 13
There is no need to prepare a substrate on which c is formed in advance. In addition, in the process of forming the mounting electrode 13c, L
Since the electrical connection with the SI chip 1 is performed, the process can be simplified.

Embodiment 19 FIG. FIG. 26 is a conceptual diagram showing a method of manufacturing a package component, for example, an LCC according to another embodiment of the present invention. In the figure, 13 is a lead also serving as a mounting electrode, and 4a is
The substrate is a glass epoxy substrate having a recess having the same shape as the LSI chip 1. The LSI chip is mounted in the recess so that the upper surface of the LSI chip and the upper surface of the substrate are aligned.

First, as shown in (a), the LSI chip 1 is placed in a concave portion formed at a predetermined position of the substrate 4a, and as shown in (b), an ultraviolet curing resin 10a is applied using a spin coater. The electrode portion is opened by photolithography. Further, as shown in (c), a lead 13 serving as an external connection terminal is formed by forming an electroless plating film from the surface of the electrode of the substrate 4a to the back surface,
C is obtained.

As described above, the LSI chip 1 is mounted on the substrate 4a.
Since there is no difference in level when mounting on a lead, it is easy to perform plating when forming leads. Further, since the LSI chip 1 is buried in the substrate 4, the package component can have a thin shape. As shown in (d), in the case of parts that need to mount a plurality of the same parts such as a memory, the mounting density is increased by stacking and mounting,
Higher signal speed can be achieved.

Embodiment 20 FIG. FIG. 27 shows this example and is a conceptual diagram showing the structure of leads and wirings formed of a plating film or the like. In the above embodiments, in the case where the lead 13 formed so as to be surrounded by the ultraviolet curing resin 10a or the polyimide tape 7 which is an insulator, when electricity flows through the lead 13,
Electricity flows in the peripheral portion of the lead 13. Also, the wider the side parallel to the horizontal plane, the lower the impedance, which is effective for speeding up the electric signal. Therefore, it can be said that the higher the surface area of the lead 13 is, the better the speed is. For example, 10 to the height of the lead viewed from the cross section in the drawing.
It is preferable to form a lead having a width of up to 1000 times.

Embodiment 21 FIG. FIG. 28 is a conceptual diagram of a method for connecting external electrodes of a package component and pads formed on a substrate according to an embodiment of the present invention. In the present embodiment, a package component in which an electrode of an LSI chip and a lead connected to this electrode are connected by soldering, for example, an LCC is mounted on a substrate as in Embodiment 13, and 21a is: LSI
Electrode 2a of chip 1 and lead 13 serving as an external connection terminal
Is a eutectic solder for connecting the lead 13 and the pad 2b on the substrate 4 (for example, a melting point of 183).
C.).

The LCC shown in the figure includes a step of fixing the LSI chip 1 face down to the LCC substrate 4 to form an opening for exposing the electrode 2 of the LSI chip, a step of supplying solder to the opening, and a step of conducting. To form a desired lead, pressurize and melt this solder to join the electrode 2 and the lead 13, and further form an LSI with the sealing resin 14.
It is formed by a step of coating a chip.

Lead 1 serving as an external connection terminal of this LCC
A method of connecting the pads 3 to the pads 3 on the substrate 4 will be described. First, as shown in FIG. 28A, an LCC having a structure in which the electrode 2 and the lead 13 are joined via a solder 21a (here, the above-described high-temperature solder is used) is applied to a pad formed on the glass epoxy substrate 4. A solder paste 21b made of eutectic solder is supplied to 3 and mounted. Next, as shown in FIG. 3B, the pad 3 and the lead 13 are soldered by leaving the solder paste 21b alone on a hot plate at 200 ° C. for 2 minutes to melt only the solder paste 21b. Thus, by heating at 200 ° C., the high-temperature solder 21 a is not melted and
Since the bonding state of the lead 13 and the lead 13 is maintained, it is possible to prevent a defect that the solder inside the LCC is melted and disconnected due to heat conduction during soldering when the LCC is mounted on the substrate.

Embodiment 22 FIG. FIG. 29 is a conceptual diagram of a method for connecting external electrodes of a package component and pads formed on a substrate according to another embodiment of the present invention. In the present embodiment, as in the twenty-first embodiment, a package component, for example, an LCC for connecting the electrode 2a of the LSI chip 1 and the lead 13 serving as an external connection terminal by soldering, and this LCC is mounted on a substrate. is there. Reference numeral 21d denotes solder supplied to an opening formed on the surface of the base substrate of the LCC to expose the electrode 2 of the LSI chip 1 to electrically connect the lead 13 serving as an external connection terminal. Reference numeral 28 denotes a solder to be mounted on the substrate 4, and reference numeral 28 denotes a thermal via hole formed in the base substrate of the LCC.

The LCC shown in FIG. 29 is formed in the same manner as in the twenty-first embodiment.
The LCC body is formed such that at least a portion between the lead portion contacting with the pad and the lead portion joined to the pad 3 is connected to the outside. By providing the thermal via hole 28 in contact with the lead 13, heat generated when the LCC is mounted on the substrate 4 is reduced by the thermal via hole 2.
8 to prevent conduction to the solder 21a and disconnection due to melting of the solder. For example, it is heated at the time of mounting, the atmosphere is kept at 210 ° C. for one minute, and the solder 21
Even when e was melted and soldered, the solder 21d did not melt.

Embodiment 23 FIG. FIG. 30 is a conceptual diagram of a method of connecting external electrodes of a package component and pads on a substrate according to another embodiment of the present invention. This embodiment is similar to the twenty-first embodiment in that the LSI
Electrode 2a of chip 1 and lead 13 serving as an external connection terminal
Are connected by soldering, and as in the eighteenth embodiment, the electrodes 2 of the LSI chip 1 are connected to external leads by a multilayer wiring structure.

A resin film 10 a is formed on the surface of the electrode 2 of the LSI chip 1 while providing an opening for exposing the electrode 2. A solder 21d is supplied to the opening, and a lead 13a of a resin film 10b and a plating film is formed on the upper surface, and the lead 13a is connected to the electrode 2 via the solder 21d. Further, a lead 13b of a resin film 10c and a plating film is formed, and the lead 13b is connected to the lead 13a. Similarly, a lead 13c of a plating film is formed on the resin film 10c, and further, the lead 13c is subjected to required molding to form an external connection terminal. LC
A C main body is formed, and the external connection terminals are joined to the pads 3 by the solder 21b. By taking such a multilayer wiring structure, the lead 1 which becomes an external connection terminal from the electrode 2a
The lead length up to 3c is longer than in the case of the single-layer structure, and the heat conduction to the solder 21d can be suppressed during the heating and joining of the solder 21e, so that disconnection due to melting of the solder 21d can be prevented. For example, the multilayer wiring structure is formed so that the length of the lead formed from the solder 21d of the LCC in the case of only one layer is about 2 to 5 times the length of the lead (generally, several hundred μm). In this case, the solder 21d was not melted even if the solder 21e was melted and soldered by heating during mounting and maintaining the atmosphere at 210 ° C. for 1 minute.

Not only the multilayer wiring structure described above, but also by sufficiently increasing the length between the solder 21d bonded to the electrode of the LSI chip and the external connection terminal portion bonded to the pad of the substrate, the melting of the solder 21d Can be prevented. Similarly, 2 to 5 times the normal length (several hundred μm) is preferable.

[0087]

As described above, according to the method for manufacturing a package component of the present invention, after the electrodes of the electronic component face up and the electronic component is arranged on the substrate, the resin layer is applied to the electronic component and the substrate. A conductive layer to be a lead connected to an electrode is formed on the surface of the resin layer, and the lead is formed into an external connection terminal. In this case, it is possible to prevent poor connection and damage to the electronic components at the time of connection, and furthermore, it is possible to form a lead to be an external connection terminal by the same process as the bonding with the electrode, thereby simplifying the manufacturing process.

After the electrodes of the electronic component are turned upside down and the electronic component is disposed on the substrate, a conductive layer serving as a lead connected to the electrode of the electronic component is formed on the surface of the electronic component and the substrate. When the leads are molded into external connection terminals, or when connecting the electrodes of a plurality of electronic components mounted on the package component, each electrode faces each other and after arranging these electronic components on the board, Since a conductive layer serving as a wiring connecting between the electrodes is formed on the surface of the electronic component and the substrate, the process for forming the resin layer is not required, and the same effects as described above can be obtained.

Further, the electronic component is arranged on the substrate so that the electrode of the electronic component faces the substrate, an opening for exposing the electrode is provided on the substrate, and a conductive material serving as a lead connected to the electrode is provided in the opening. When a layer is formed, this lead is formed into an external connection terminal, or when connecting electrodes of a plurality of electronic components mounted on a package component, each of the electronic components faces each other so as to face the substrate. After disposing the electronic component on the substrate, an opening for exposing an electrode to which the electronic component is connected is provided in the substrate, and a conductive layer serving as a wiring connecting between the electrodes is formed in the opening, so that the electrode faces the substrate. The same effect as described above can also be obtained when electronic components are mounted on a substrate.

[0090]

[0091]

[0092]

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a package component according to a first embodiment of the present invention.

FIG. 2 is a perspective view of a package component manufacturing process according to the first embodiment of the present invention when a lead connected to an electrode is formed.

FIG. 3 is a process chart of a method of manufacturing a package component for connecting electrodes of a plurality of electronic components according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of connecting between electrodes of an electronic component and pads of a substrate according to a second embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the package component according to the third embodiment of the present invention.

FIG. 6 is a process chart of a method of manufacturing a package component for connecting electrodes of a plurality of electronic components according to a fourth embodiment of the present invention.

FIG. 7 is a diagram illustrating a method for connecting between electrodes of an electronic component and pads of a substrate according to a fourth embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of the package component according to the fifth embodiment of the present invention.

FIG. 9 is a process chart of the method of manufacturing a package component for connecting electrodes of a plurality of electronic components according to the sixth embodiment of the present invention.

FIG. 10 is a diagram illustrating a method for connecting between electrodes of an electronic component and pads of a substrate according to a sixth embodiment of the present invention.

FIG. 11 is a manufacturing process diagram of the package component according to the seventh embodiment of the present invention.

FIG. 12 is a process chart of the method of manufacturing a package component for connecting electrodes of a plurality of electronic components according to the eighth embodiment of the present invention.

FIG. 13 is a diagram illustrating a method for connecting between electrodes of an electronic component and pads of a substrate according to an eighth embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of the package component according to the ninth embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of the package component according to the tenth embodiment of the present invention.

FIG. 16 is a manufacturing process diagram of the package component shown in Embodiment 11 of the present invention.

FIG. 17 is a manufacturing process diagram of the package component shown in Embodiment 12 of the present invention.

FIG. 18 is a manufacturing process diagram of the package component shown in Embodiment 13 of the present invention.

FIG. 19 is a manufacturing process diagram of the package component shown in Embodiment 14 of the present invention.

FIG. 20 is a sectional view of a QTP which is a package component according to a fifteenth embodiment of the present invention.

FIG. 21 is a manufacturing process diagram of the package component shown in Embodiment 15 of the present invention.

FIG. 22 is a manufacturing process diagram of the package component shown in Embodiment 16 of the present invention.

FIG. 23 is a view showing the manufacturing process of the package component shown in Embodiment 17 of the present invention;

FIG. 24 is a manufacturing process diagram of the package component shown in Embodiment 18 of the present invention.

FIG. 25 is a sectional view of a BGA which is a package component according to an eighteenth embodiment of the present invention.

FIG. 26 is a manufacturing process diagram of the package component shown in Embodiment 19 of the present invention.

FIG. 27 is a sectional view of a lead portion constituting a package component according to a twentieth embodiment of the present invention.

FIG. 28 is a sectional view of an LCC which is a package component according to a twenty-first embodiment of the present invention.

FIG. 29 is a sectional view of an LCC which is a package component according to a twenty-second embodiment of the present invention.

FIG. 30 is a cross-sectional view of an LCC which is a package component shown in Embodiment 23 of the present invention.

FIG. 31 is a diagram showing a method for connecting an electrode and a lead by wire bonding according to a conventional technique.

FIG. 32 is a diagram showing a manufacturing process of a package component including bonding by bumps according to a conventional technique.

FIG. 33 is a diagram showing a problem of connection by wire bonding according to the related art.

FIG. 34 is a view showing a problem of bonding by a bump according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LSI chip 2 LSI chip electrode 4 Glass epoxy substrate 7 Polyimide tape 10 Epoxy resin 10a Ultraviolet curing resin 11 Opening 12 Electroless copper plating film 13 Lead 14 Package sealing resin 15 Wiring between electrodes 16 Photoresist 17 Ultraviolet light 18 Photomask 20 Electroless copper plating activator 21 Solder 22 Direct drawing nozzle 24 Solder layer 25 Solder layer 26 Step buffer component 28 Thermal via hole

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Teru Adachi 8-1-1 Tsukaguchi Honcho, Amagasaki City Mitsubishi Electric Corporation Co., Ltd. Production Engineering Research Laboratory (72) Inventor Osamu Hayashi 8-1-1 Tsukaguchi Honcho Amagasaki City Mitsubishi Electric Corporation, Production Technology Laboratory (72) Inventor Susumu Hoshinouchi 8-1-1, Tsukaguchi Honcho, Amagasaki City Mitsubishi Electric Corporation Production Technology Laboratory (72) Inventor, Yoichi Kitamura 8-1-1, Tsukaguchi Honcho, Amagasaki City No. 1 Mitsubishi Electric Corporation In-house Research Laboratory (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 23/50 H01L 23/12 H01L 21/60 H01L 23/48

Claims (7)

(57) [Claims] A step of forming a resin layer on the electronic component and the substrate after placing the electronic component on a substrate with the electrodes of the electronic component facing the front, and connecting the electrode to the surface of the resin layer. A method of manufacturing a package component, comprising: a step of forming a conductive layer to be a lead to be formed; and a step of forming the lead into an external connection terminal. 2. A step of forming a resin layer on the electronic component and the substrate so as to cover the electrode after disposing the electronic component on the substrate with the electrode of the electronic component facing the front; Forming an opening in the resin layer for exposing the conductive layer, forming a conductive layer serving as a lead connected to the electrode on the opening and the surface of the resin layer, and forming the lead into an external connection terminal. A method for manufacturing a package component, comprising: 3. A step of forming a conductive layer serving as a lead connected to the electrode on the surface of the electronic component and the substrate after arranging the electronic component on a substrate with the electrodes of the electronic component facing up; A method for manufacturing a package component, comprising a step of forming a lead into an external connection terminal. 4. A step of fixing an electronic component having electrodes to one surface of a substrate so that the electrodes face each other, and a step of forming an opening in the substrate to expose the electrodes to the back surface of the substrate. A method for manufacturing a package component, comprising: forming a conductive layer serving as a lead connected to the electrode in the opening; and forming the lead into an external connection terminal. 5. The method of manufacturing a package component according to claim 1, wherein the conductive layer is an electroless plating film. 6. The method for manufacturing a package component according to claim 1, wherein the conductive layer is formed by direct drawing of a conductive paste. 7. The step of forming a conductive layer serving as a lead connected to an electrode or a wiring connected between electrodes includes forming a conductive layer at least at a location where the lead or the wiring is formed, and then forming the conductive layer A step of forming a photoresist film so as to cover, and after exposing and curing the lead or wiring portion of the photoresist film,
Removing a portion of the photoresist film that is not cured;
The method according to any one of claims 1 to 4 , further comprising a step of removing the remaining photoresist film after removing the exposed conductive layer portion.