JP3266136B2 - Automatic wiring method of semiconductor integrated circuit and semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ASIC (Application Specification) having a multilayer wiring structure.
The present invention relates to an automatic wiring method for a semiconductor integrated circuit constituted by c Integrated Circuit and the like, and a semiconductor integrated circuit device realized by the automatic wiring method.

[0002]

2. Description of the Related Art Conventionally, in the layout design of an LSI such as an ASIC, automatic layout of circuit cells and wiring has been performed using a layout apparatus having an automatic placement and routing function, and signal propagation delay of wiring has been performed. In order to reduce the time (wiring delay time), various wiring methods have been proposed as described below.

FIG. 4 is a flowchart showing an example of an LSI automatic wiring method disclosed in Japanese Patent Application Laid-Open No. 6-283602. In this automatic wiring method, in an LSI having a multilayer wiring structure, attention is paid to the fact that each wiring layer has unique electric characteristics such as electric resistance and capacitance and has different wiring delay times. By allocating the arrangement, the overall wiring delay time is reduced. Specifically, first, one of the plurality of wiring layers having a larger delay time is selected as a provisional wiring layer, the worst case is estimated by delay calculation, and nets to be routed are taken out in descending order of the delay amount ( Step S101). If the estimated wiring delay amount is larger than the specified value (step S102), a signal having the estimated wiring delay amount larger than the specified value is preferentially wired. At that time, when searching for the wiring route of the net of interest, in order to realize the least possible wiring delay, first, when deciding the wiring layer for the wiring line, the wiring delay is the minimum among the plurality of existing wiring routes. (Step S)
103). On the other hand, if the estimated wiring delay amount is smaller than the specified value, wiring is performed for the purpose of minimizing the unconnected state or the short circuit without considering the wiring delay (step S104). After that, the processes in steps S101 to S104 are repeatedly executed until the end condition is satisfied.

In the LSI automatic wiring method disclosed in Japanese Patent Application Laid-Open No. 5-368830, the wiring length is minimized as much as possible in consideration of the connection state of each net of wiring in the wiring area and wiring layer information. Furthermore, by minimizing the wiring length of a specific wiring layer, the resistance value of each net of the wiring in the wiring area is minimized as much as possible, and the wiring delay time is reduced.

[0005]

However, in the conventional automatic wiring method including the above-mentioned publication, the wiring layout is performed without considering the distance between circuit cell arrangements. There is a problem that the increase in the wiring delay time cannot be sufficiently suppressed. This point will be specifically described with reference to FIG.

FIG. 5 is a sectional view showing an example of a conventional LSI multilayer wiring structure. As shown in the figure, a first wiring layer 201 and a second wiring layer 20 are sequentially formed on a silicon substrate 200.
2, a third wiring layer 203, a fourth wiring layer 204, a fifth wiring layer 205, and a sixth wiring layer 206 are formed.
The wiring layer 201 is arranged in parallel with the silicon substrate 200,
The upper wiring layers 202 to 206 are disposed so as to be orthogonal to each other.

In recent years, miniaturization of LSIs, especially ASICs, has rapidly progressed, and accordingly, the spacing between wirings has been reduced and the number of wiring layers has been increased. As a result, the influence of the mutual wiring capacitance increases, and the unit wiring capacitances C1 to C6 (see FIG. 5) increase. In general, the wiring delay time increases when the wiring capacitance is large. Therefore, when the unit wiring capacitances C1 to C6 increase, there is a problem that the wiring capacitance increases when the wiring length is long and the wiring delay time increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems. An object of the present invention is to suppress an increase in the wiring capacitance even if there is a long wiring, and to reduce the wiring delay time. It is an object of the present invention to provide a method of automatically wiring a semiconductor integrated circuit capable of suppressing an increase in the number of semiconductor integrated circuits, and a semiconductor integrated circuit device realized by the automatic wiring method.

[0009]

According to a first aspect of the present invention, there is provided an automatic wiring method for a semiconductor integrated circuit, comprising the steps of: using a netlist satisfying a logical function of the semiconductor integrated circuit; Automatic placement processing for automatically placing cells, placement distance calculation processing for finding a distance between placements of the respective circuit cells placed in the automatic placement processing, and placement distance calculated in the placement distance calculation processing and presetting A comparison process of comparing the set reference value with the reference value, wiring a wiring path in which the distance between the arrangements exceeds the reference value to an upper layer shielded by a ground layer or a power supply layer, and setting the distance between the arrangements within the reference value. And a wiring process of wiring the wiring path under the ground layer or the power supply layer.

According to a second aspect of the present invention, in the semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate, a ground layer or a power supply layer is formed on the semiconductor substrate. A wiring layer having a wiring length longer than a predetermined reference value is formed in an upper layer shielded by the ground layer or the power supply layer, and a wiring layer having a wiring length shorter than the predetermined reference value is formed below the ground layer or the power supply layer. It is characterized by being formed in.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a method for automatically wiring a semiconductor integrated circuit according to one embodiment of the present invention, and FIG. 2 is a layout diagram of an ASIC according to this embodiment. The present embodiment describes, for example, an automatic wiring method for an ASIC. This automatic wiring method includes an automatic layout program according to a flowchart shown in FIG. It is realized by storing and executing this.

In the automatic wiring process according to the present embodiment, first, a netlist satisfying a logical function is input to start the process, and automatic placement of circuit cells is performed in step S1. The state at this time will be described with reference to FIG. In a predetermined LSI chip 11, each macro 21 for realizing a predetermined function is provided.
22 are arranged. The macro cell 21 contains the circuit cell 21
a, 21b are arranged, and the circuit cell 2 is
2a is arranged.

In the next step S2, the calculation of the distance between arrangements is executed. Here, the circuit cell 21a in the macro 21
Of the wiring path 31 between the circuit cell 21b and the macro 2
The distance between the circuit cell 21b and the wiring path 32 between the circuit cell 22a and the circuit cell 22a is calculated. The distance between the circuit cells is calculated, for example, in Manhattan length.

In the following step S3, step S2
Is compared with a preset reference distance between arrangements. Then, as a result, if there is a wiring route exceeding the reference distance between arrangements, the process proceeds to step S4, and the wiring route is wired in an upper layer shielded by a ground (GND) layer. On the other hand, if the inter-arrangement distance is a wiring route within the inter-arrangement reference distance, the process proceeds to step S5, and wiring is performed below the ground layer.

Here, the wiring processing in steps S4 and S5 will be described more specifically with reference to FIG. 3 showing a sectional structure of an ASIC realized by the automatic wiring method of the present embodiment. As shown in FIG.
A first wiring layer 41, a second wiring layer 42, and a third wiring layer 43 are sequentially disposed thereon, and a ground layer 44 is disposed thereon. Further, a fifth wiring layer 45 and a sixth wiring layer 46 are provided on the upper layer shielded by the ground layer 44.
Are sequentially arranged. The silicon substrate 40 and the first wiring layer 41 are arranged in parallel, and the first wiring layer 41, the second wiring layer 42, and the third wiring layer 43 are arranged orthogonal to each other. The ground layer 44 and the fifth wiring layer 45 are arranged in parallel, and the fifth wiring layer 45 and the sixth wiring layer 46 are arranged orthogonally.

Here, for example, assuming that the distance of the wiring path 31 is within the reference distance between wirings and the distance of the wiring path 32 exceeds the reference distance between wirings,
Is within the reference distance between the wirings, the first wiring layer 41, the second wiring layer 42, and the third wiring layer 43 below the ground layer 44.
And the wiring path 32 exceeding the reference distance between wirings is wired by the upper fifth wiring layer 45 and the sixth wiring layer 46 shielded by the ground layer 44. Then, after these processes are performed for all the wiring routes, the automatic wiring process of the present embodiment shown in the flow of FIG. 1 ends.

As described above, in the automatic wiring method according to the present embodiment, the processing of automatically arranging the netlist satisfying the logical function as an input, the processing of calculating the distance between the arrangements, A process of comparing the inter-arrangement distance obtained in the process, a process of wiring in an upper layer shielded by a ground layer if there is a wiring route (wiring length is longer) exceeding the inter-arrangement reference distance, and If the value is within the reference value, the process of wiring in the lower layer of the ground layer is executed, so that the following advantages are provided.

That is, as shown in FIG. 3, the capacitance between the wiring layers disposed between the silicon substrate 40 and the ground layer 44 is C1, C2, C3, and C4, respectively. When the capacitance between the respective wiring layers between the layer 46 and the layer 46 is C5 and C6, the capacitance between the wirings is generally large. It becomes smaller than the unit wiring length capacitances C2 to C4 in the lower layer.

Generally, when the wiring capacitance increases, the wiring delay increases. In the present embodiment, even if the wiring has a long wiring length,
Since only the long wiring is connected to another layer shielded by the ground layer 44, the unit wiring capacitance of the long wiring can be reduced. As a result, even if there is a long wiring, the increase in the wiring capacitance can be suppressed, and the increase in the wiring delay time can be reduced.

The present invention is not limited to the illustrated embodiment, but can be variously modified. As a modified example, for example, a power supply layer may be provided in place of the ground layer 44 to shield the upper layer and the lower layer.

[0021]

As described above in detail, according to the method for automatically wiring a semiconductor integrated circuit according to the first aspect of the present invention, even if the wiring is long, only the long wiring is shielded by the ground layer or the power supply layer. Since the wiring is formed in the upper layer, the unit wiring capacitance of the wiring having a long wiring length can be reduced. This makes it possible to suppress an increase in wiring capacitance even if there is a long wiring length, and to suppress an increase in wiring delay time. In particular, when the present invention is applied to an ASIC in which miniaturization progresses rapidly, the above effects can be remarkably enjoyed. According to the semiconductor integrated circuit device of the second aspect, the same effect as that of the first aspect can be obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for automatically wiring a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a layout diagram of an LSI according to the embodiment.

FIG. 3 is an ASI realized by the automatic wiring method according to the embodiment;
It is sectional drawing of C.

FIG. 4 is a flowchart showing an example of a conventional LSI automatic wiring method.

FIG. 5 is a cross-sectional view showing an example of a conventional LSI multilayer wiring structure.

[Explanation of symbols]

 11 LSI chip 21, 22 Macro 21a, 21b Circuit cell 31 Wiring path 32 Wiring path 40 Silicon substrate 41 First wiring layer 42 Second wiring layer 43 Third wiring layer 44 Ground layer 45 Fifth wiring layer 46 Sixth wiring layer

Claims (2)

(57) [Claims] 1. An automatic placement process for automatically placing a plurality of circuit cells using a netlist satisfying a logic function of a semiconductor integrated circuit, and a placement for determining a distance between the placement of each circuit cell placed in the automatic placement process. A distance calculation process, a comparison process of comparing the distance between arrangements obtained in the distance calculation between arrangements and a preset reference value, and a wiring path in which the distance between arrangements exceeds the reference value, a ground layer or While wiring in the upper layer shielded by the power supply layer, a wiring route in which the distance between the arrangement is within the reference value,
Performing a wiring process for wiring below the ground layer or the power supply layer. 2. A semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate, wherein a ground layer or a power supply layer is provided on the semiconductor substrate, and the wiring length is longer than a predetermined reference value. A semiconductor integrated circuit device, wherein a layer is formed on an upper layer shielded by the ground layer or the power supply layer, and a wiring layer having a wiring length shorter than the predetermined reference value is formed below the ground layer or the power supply layer. .