JP3260393B2 - Dynamic semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM) in which sense amplifier driving transistors are arranged in a distributed manner to increase the speed.

[0002]

2. Description of the Related Art FIG. 9 shows a configuration of a bit line sense amplifier of a conventional DRAM. A well-known memory cell MC having a one-transistor / capacitor configuration is arranged in a matrix to form a cell array. The cell array is provided with a plurality of word lines WL and a plurality of pairs of bit lines BL and / BL. When the data of the memory cell MC is the bit line pair BL,
/ BL is amplified by an NMOS sense amplifier NSA which is a flip-flop constituted by an NMOS transistor. Bit line pair BL, /
The BL is provided with a PMOS sense amplifier composed of a flip-flop using a PMOS transistor in order to amplify the “H” level side of the read data to the power supply potential, but this is omitted in the figure. The sense amplifier drive line / SAN connected to the common source node of the NMOS sense amplifier NSA is basically one drive NMOS
It is connected to the transistor Qn.

At the time of data reading, a sense amplifier driving NM
The drive signal SEN is input to the gate of the OS transistor Qn, whereby each NMOS sense amplifier NSA is activated. At this time, currents from all the bit line pairs BL and / BL flow through the NMOS sense amplifier NSA to the sense amplifier drive line / SAN. Therefore, large capacity DRA
In M, the potential of the common source node of each sense amplifier rises as the distance from the drive NMOS transistor Qn increases, due to the wiring resistance R of the sense amplifier drive line / SAN. This causes a large delay in the operation of the sense amplifier.

[0004] To solve this problem, the present inventors have proposed:
We have proposed a method of distributing NMOS transistors for driving NMOS sense amplifiers in word line snap areas (1990 IEICE Autumn National Convention p5-3)
06). The word line snap region is a region in which an Al wiring arranged over the word line is brought into contact with the word line in order to reduce the resistance of the word line made of polycrystalline silicon. The word line snap area is provided between the blocks by dividing the cell array into a plurality of blocks in the word line direction. This word line snap area and NMO
At the intersection of the S sense amplifier area, the sense amplifier driving NM
OS transistors are distributed and a second Al wiring is disposed in the bit line direction as a source power supply line that directly contacts the NMOS transistor. As a result, the currents of a large number of NMOS sense amplifiers can be dispersed, and the floating of the common source node of the NMOS sense amplifiers when driven by one NMOS transistor as in the related art can be suppressed.

However, in order to increase the speed of the DRAM, it is not sufficient to merely disperse the NMOS sense amplifier driving transistors as described above. Increasing the speed of the NMOS sense amplifier is effective in reducing the RAS access time of the DRAM, but shortening the cycle time requires increasing the speed of the PMOS sense amplifier that determines the restore time. The PMOS sense amplifier outputs "H" of the read data.
This is because it functions to amplify the level side.

[0006]

As described above, the NMO
In a method in which only the NMOS transistors for driving the S sense amplifier are dispersedly arranged, there is a problem that the speeding up of the DRAM is insufficient.

[Structure of the Invention]

[0008]

A DRAM according to the present invention.
Is a matrix of dynamic memory cells
Cell array and one of the cell arrays
Pairs of bits that exchange data with memory cells
Line in a direction that intersects with the bit line of the cell array.
Multiple word lines to drive memory cells
Formed on a line and arranged in the same direction as the word line
A plurality of first metal wirings and a cell array in a word line direction
Cell array block divided into multiple cells
Another cell array adjacent to the array block in the word line direction
And between the word line and the first line.
Word line with connecting parts for connecting to the metal wiring of
Cell area connected to snap area and each bit line pair
A plurality of PMOs arranged at the end of the block in the bit line direction
An S sense amplifier and a plurality of NMOS sense amplifiers;
PMOS sense amplifiers are arranged in the word line direction.
Extending in the bit line direction of the region and the word line snap region
PMOS sensors arranged in regions where the regions intersect with each other
A PMOS transistor for driving the amplifier and a plurality of N
The region where the MOS sense amplifier is arranged in the word line direction and
A region extending in the bit line direction of the word line snap region;
Are NMOS sense amplifiers arranged in the areas where
An NMOS transistor for driving the pump.
A PMOS transistor for driving a PMOS sense amplifier.
Second gold disposed in the bit line direction with the source terminal of the star
And the second metal wiring B is connected to the second metal wiring B.
NM that drives the NMOS sense amplifier
It is arranged in the bit line direction with the source terminal of the OS transistor.
Connected to the second metal wiring A, and the second metal wiring
A is a first source power supply line, and the first source
Source power line and the second source power line alternately
Are arranged for each snap line snap area.
You.

[0009]

According to the present invention, a PMOS sense amplifier, NM
By arranging the driving transistors in the OS sense amplifier in a distributed manner, the speed of the DRAM can be further increased. That is, the RAS access time can be shortened by dispersing the driving NMOS transistors of the NMOS sense amplifier, and the cycle time can be shortened by dispersing the driving PMOS transistors of the PMOS sense amplifier.

[0010]

Embodiments of the present invention will be described below.

FIG. 1 is a layout showing a configuration of a main part of a DRAM according to an embodiment, FIG. 2 is a diagram showing an equivalent circuit of the main part, and FIG. 3 is a specific layout of the main part. It is shown.

A dynamic memory cell MC composed of one transistor / one capacitor is arranged in a matrix on a semiconductor substrate to form a cell array 1. The cell array 1 includes word lines WL for driving the memory cells MC,
A bit line pair BL for exchanging data with the memory cell MC,
/ BL intersect. The cell array 1 is divided into a plurality of blocks in the word line WL direction as shown in FIG. The word line snap area 2 is between these cell arrays and blocks. That is, the word line WL is
As shown in FIG. 1, a polycrystalline silicon wiring 21 serving as a gate electrode of a cell transistor is continuously provided as it is, and a first Al wiring 22 is provided thereover, and a word line snap region 2 is provided. The contact portion 23 between the first Al wiring 22 and the polycrystalline silicon wiring 21 is arranged.

In this embodiment, an NMOS sense amplifier 3 and a PMOS are connected to one end of the cell array 1 in the bit line direction.
The sense amplifiers 4 are arranged adjacent to each other. As is well known, the NMOS sense amplifier is a flip-flop formed by cross-connecting the drain and gate of two NMOS transistors. The PMOS sense amplifier is a similar flip-flop. The NMOS transistors 5 for driving the sense amplifier, which are connected to the common source node of the NMOS sense amplifier, are arranged at both ends of the drive line / SAN.
Are arranged separately at each intersection. Similarly, PMOS transistors 6 for driving the PMOS sense amplifier are arranged at both ends of the drive line SAP,
The sense amplifiers 4 and the word line snap regions 2 are distributed and arranged at respective intersections. Then, by directly contacting the source of the NMOS transistor 5 arranged in the word line snap region 2 (contact portion 9), the source power supply line 7 (ground line) is arranged in the same direction as the bit line BL, and the word line A source power supply line 8 (Vcc line) is arranged in the same direction as the bit line BL in direct contact with the source of the PMOS transistor 6 arranged in the line snap region 2 (contact portion 10). As described above, the word line WL
Since the first Al wiring 22 is provided to reduce the resistance of the
Wiring is used.

FIG. 3 shows sense amplifier drive lines / SAN and SAP connected to a common source node of each sense amplifier.
As shown in (1), first Al wirings 25 and 26 are used, which are in contact with the drains of the NMOS transistor 5 and the PMOS transistor 6, respectively. NMOS
The control lines SEN and / SEP connected to the gates of the transistor 5 and the PMOS transistor 6, respectively, are also constituted by the first Al wirings 27 and 28, respectively.

FIG. 4 is a sectional view taken along the line AA 'of FIG. A word line snap region 2 is provided between cell array blocks 1 arranged on a semiconductor substrate 31. Here, as described above, a first Al The wiring 22 is in contact. On the first Al wiring 22, source power supply lines 7, 8 of the second Al wiring are further provided via an interlayer insulating film.

In this embodiment, the first Al wirings 22, 2
5 to 28 are the first layer metal wiring, and the source power supply lines 7 and 8 are the second metal wiring.
Although it is a layer metal wiring, the upper and lower relation of these wiring layers can be reversed.

In this embodiment, the NMOS transistor 5 and the PMOS transistor 6 are arranged in a straight line in the narrow word line snap region 2. Therefore, the source power supply lines 7 and 8 connected to each other are bent wirings as shown in the figure to avoid the respective contact portions 9 and 10 from each other. Therefore, it is necessary for the column selection line CSL using the same second Al wiring as the source power supply lines 7 and 8 to be bent in accordance with the bending of the source power supply lines 7 and 8. This is shown in FIG.

According to this embodiment, the bit line current at the time of data reading flows to the source power supply lines 7 provided for the respective elements through the NMOS transistors 5 for driving the NMOS sense amplifiers arranged in a distributed manner. NMOS
The effect of the potential drop due to the resistance of the drive line / SAN of the sense amplifier 3 is reduced. Therefore, high speed operation of the NMOS sense amplifier 3 becomes possible. Similarly, the current flowing through the PMOS sense amplifier 4 also flows through the source power supply lines 8 provided for the sense amplifier driving PMOS transistors 6 arranged in a distributed manner, so that the operation of the PMOS sense amplifier 6 is accelerated and the restoration time is reduced. Is shortened. As described above, a DRAM with reduced access time and cycle time can be obtained.

In the above embodiment, the PMOS transistor 6 for driving the PMOS sense amplifier and the NMOS transistor 5 for driving the NMOS sense amplifier arranged in the word line snap region are arranged in a straight line. In order to avoid the contact part, the wiring was bent.

On the other hand, as shown in FIG.
If the S transistor 6 and the NMOS transistor 5 are arranged so as to be displaced from each other in the word line direction, the source power supply lines 8 and 7 contacting them can be arranged in a straight line as shown without bending. However, in this case, the PMOS sense amplifier 4 and the NM
A shift also occurs between the OS sense amplifiers 3.

FIG. 7 shows an equivalent circuit of a main part of a DRAM according to another embodiment of the present invention. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment, and detailed description is omitted. In this embodiment, a PMOS sense amplifier 4 is arranged at the center of a cell array 1 and NM
This is a case where the OS sense amplifier 3 is provided. The bit line pairs are arranged such that one adjacent pair is inserted between one pair. Also in this embodiment, the NMOS transistor 5 for driving the NMOS sense amplifier and the PMOS transistor 6 for driving the PMOS sense amplifier are distributed at the intersection of the word line snap region 2 with the NMOS sense amplifier 3 and the PMOS sense amplifier 4, respectively. Source power lines 7 and 8 of the NMOS transistor 5 and the PMOS transistor 6 are arranged in each word line snap region by a second Al wiring.

FIG. 8 shows a DRAM according to still another embodiment of the present invention.
It is. In the above embodiment, the NMOS sense amplifier driving transistor 5 and the PMOS
The sense amplifier driving transistor 6 is arranged together, so that two source power supply lines 7 and 8 are arranged in each word line snap region 2. On the other hand, in this embodiment, one of the NMOS transistor 5 for driving the NMOS sense amplifier and the PMOS transistor 6 for driving the PMOS sense amplifier are alternately arranged in the plurality of word line snap regions 2. Therefore, one source power supply line 7 or 8 is provided in each word line snap area 2.

In this embodiment, the degree of dispersion of the sense amplifier current is slightly lower than that of the previous embodiment. DR compared
The speed of AM is improved.

The present invention is not limited to the above embodiment, but can be implemented in various modifications without departing from the spirit thereof.

[0025]

As described above, according to the present invention, the NMOS sense amplifier driving transistors and the PMOS sense amplifier driving transistors are dispersedly arranged in the word line snap region, and the source power supply lines contacting the respective sources are provided. By arranging them in the same direction as the bit lines, the speed of the DRAM can be increased.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a main configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing a configuration of a main part of the embodiment.

FIG. 3 is a layout diagram showing a configuration of a further main part of the embodiment.

FIG. 4 is a sectional view of a word line snap area according to the embodiment;

FIG. 5 is a view showing a pattern of a column selection line according to the embodiment.

FIG. 6 is a layout diagram showing a main part configuration of a DRAM according to another embodiment of the present invention.

FIG. 7 is a diagram showing an equivalent circuit of a DRAM according to still another embodiment of the present invention.

FIG. 8 is a layout diagram of a DRAM according to still another embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a sense amplifier section in a conventional DRAM.

[Description of References] MC: memory cell, BL, / BL: bit line pair, WL:
Word line, 1 ... cell array, 2 ... word line snap area, 3 ... NMOS sense amplifier, 4 ... PMOS sense amplifier, 5 ... NMOS transistor for driving NMOS sense amplifier, 6 ... PMOS transistor for driving PMOS sense amplifier, 7, 8 ... Source power supply line (second Al wiring),
9, 10 contact part, 21 polycrystalline silicon wiring (gate electrode), 22 first Al wiring, 23 contact part.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenji Tsuchida 1 Tokoba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture

Claims (8)

(57) [Claims] 1. A cell array in which dynamic memory cells are arranged in a matrix, a plurality of pairs of bit lines arranged in one of the cell arrays to exchange data with memory cells, A plurality of word lines arranged in a direction intersecting the bit lines to drive a memory cell; and a plurality of first metals formed on the word lines and arranged in the same direction as the word lines. A wiring, a cell array block in which the cell array is divided into a plurality in the word line direction, and a cell array block extending between the cell array block and another cell array block adjacent in the word line direction, and A word line snap area provided with a connection portion for connecting a word line to the first metal wiring; and a cell array block connected to each of the bit line pairs. A plurality of PMOS sense amplifiers and a plurality of NMOS sense amplifiers disposed at the ends in the bit line direction, and a region where the plurality of PMOS sense amplifiers are disposed in the word line direction and a word line snap region extending in the bit line direction. A PMOS transistor for driving a PMOS sense amplifier disposed in a region where existing regions intersect with each other; a region where the plurality of NMOS sense amplifiers are arranged in a word line direction; And an NMOS transistor for driving the NMOS sense amplifier disposed in a region where the region extending in the bit line direction intersects with each other, and for driving the PMOS sense amplifier. the are disposed with the source terminal of the PMOS transistor in the bit line direction 2
And the second metal wiring B is connected to the second metal wiring B.
And a source terminal of an NMOS transistor for driving the NMOS sense amplifier is connected to a second metal wiring A arranged in the bit line direction .
A first source power line, wherein the first source power lines and the second source power lines are alternately arranged for each of the plurality of word line snap regions. A dynamic semiconductor memory device. 2. The PMOS sense amplifier disposed in a region where the plurality of PMOS sense amplifiers are arranged in the word line direction and a region of the word line snap region extending in the bit line direction intersects with each other. P to drive the amplifier
A MOS transistor and the NMOS sense amplifier disposed in an entire region where a region where the plurality of NMOS sense amplifiers are arranged in the word line direction and a region where the word line snap region extends in the bit line direction cross each other; 2. The dynamic semiconductor memory device according to claim 1, further comprising: an NMOS transistor for driving the semiconductor device. 3. A channel is provided in each of two regions where the region where the plurality of PMOS sense amplifiers are arranged in the word line direction and the region where the word line snap region extends in the bit line direction intersect each other. 3. The dynamic semiconductor according to claim 2, further comprising a PMOS transistor for driving said PMOS sense amplifier, wherein gate electrodes thereof are connected to each other, and source terminals thereof are connected by the same diffusion layer. Storage device. 4. The PMOS sense amplifier disposed in all regions where the region where the plurality of PMOS sense amplifiers are arranged in the word line direction and the region where the word line snap region extends in the bit line direction cross each other. P to drive the amplifier
A MOS transistor and the NMOS sense amplifier disposed in an entire region where a region where the plurality of NMOS sense amplifiers are arranged in the word line direction and a region where the word line snap region extends in the bit line direction cross each other; And a plurality of NMOS sense amplifiers, each of which has a region where the plurality of NMOS sense amplifiers are arranged in the word line direction and a region where the word line snap region extends in the bit line direction crosses each other. , Channel 2
NMOS for driving the NMOS sense amplifier
2. The dynamic semiconductor memory device according to claim 1, wherein transistors are arranged, their gate electrodes are connected to each other, and their source terminals are connected by the same diffusion layer. 5. A plurality of regions in which the plurality of PMOS sense amplifiers are arranged in the word line direction and regions in the word line snap region extending in the bit line direction cross each other. A PMOS transistor for driving the PMOS sense amplifier is disposed every other region in this region, and a region where the plurality of NMOS sense amplifiers are disposed in the word line direction and a region in the bit line direction of the word line snap region. There are a plurality of regions where the extending regions intersect with each other in the word line direction.
2. The semiconductor memory device according to claim 1, further comprising an NMOS transistor for driving said NMOS sense amplifier. 6. A cell array in which dynamic memory cells are arranged in a matrix, a plurality of pairs of bit lines arranged in one of the cell arrays to exchange data with the memory cells, A plurality of word lines arranged in a direction intersecting the bit lines to drive a memory cell; and a plurality of first metals formed on the word lines and arranged in the same direction as the word lines. A wiring, a cell array block in which the cell array is divided into a plurality in the word line direction, and a cell array block extending between the cell array block and another cell array block adjacent in the word line direction, and A word line snap area provided with a connection portion for connecting a word line to the first metal wiring; and a cell array block connected to each of the bit line pairs. A plurality of PMOS sense amplifiers and a plurality of NMOS sense amplifiers disposed at the ends in the bit line direction, and a region where the plurality of PMOS sense amplifiers are disposed in the word line direction and a word line snap region extending in the bit line direction. A PMOS transistor for driving a PMOS sense amplifier disposed in a region where existing regions intersect with each other; a region where the plurality of NMOS sense amplifiers are arranged in a word line direction; And an NMOS transistor for driving the NMOS sense amplifier disposed in a region where the region extending in the bit line direction intersects with each other, and for driving the PMOS sense amplifier. the are disposed with the source terminal of the PMOS transistor in the bit line direction 2
And the second metal wiring B is connected to the second metal wiring B.
And a source terminal of an NMOS transistor for driving the NMOS sense amplifier is connected to a second metal wiring A arranged in the bit line direction .
A first source power line, and wherein the first source power line and the second source power line are arranged in one word line snap region; A plurality of regions in which a plurality of PMOS sense amplifiers are arranged in the word line direction and regions in the word line snap region extending in the bit line direction cross each other, and a plurality of regions exist in the word line direction. The region where the PMOS transistor is disposed and the region where the plurality of NMOS sense amplifiers are disposed in the word line direction and the region where the word line snap region extends in the bit line direction intersect each other. A dynamic semiconductor memory device, wherein a plurality of NMOS transistors are provided in a line direction, and the NMOS transistors are arranged every other in this region. 7. The plurality of PMOS sense amplifiers and NMs.
A PMOS transistor for driving the PMOS sense amplifier and an NMOS sense amplifier are driven in a region where a sense amplifier region in which an OS sense amplifier is arranged and a region extending in the bit line direction of the word line snap region cross each other. 2. The dynamic semiconductor memory device according to claim 1, wherein both of the NMOS transistors are arranged. 8. A word line direction, in parallel to a plurality of the NMOS sense amplifier during or adjacent portions, the first metal wiring A is disposed, is disposed in the word line snap region, the second metal A first source power supply line of the wiring A and the first source power supply line;
And extending the region where the plurality of NMOS sense amplifiers are arranged and the word line snap region to each other and connecting them in a region where they cross each other, in the word line direction,
A first metal wiring B is further provided in parallel with the plurality of PMOS sense amplifiers or in a portion adjacent thereto, and a second source power supply line of the second metal wiring B provided in the word line snap region. And the first metal wiring B are connected to each other in a region where the plurality of PMOS sense amplifiers are arranged and the word line snap region extend from each other and cross each other. 8. The dynamic semiconductor memory device according to 7.