JP3259529B2 - Selective etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selective etching method applied in the field of manufacturing semiconductor devices and the like, and more particularly to a method for ensuring a large etching selectivity between a silicon nitride-based material layer and a silicon oxide-based material layer. .

[0002]

2. Description of the Related Art As a constituent material of an interlayer insulating film in a silicon device, a silicon compound, in particular, a silicon oxide (SiO _x ; typically, x = 2) film is widely used.

Conventionally, dry etching of SiO _x has been mainly carried out using a fluorocarbon-based compound such as CHF ₃ , CF ₄ / H ₂ mixed gas, CF ₄ / O ₂ mixed gas, C ₂ F ₆ / CHF ₃ mixed gas, etc. Etching gas has been used. This is because (a) C atoms contained in the fluorocarbon-based compound generate C—O bonds having a large interatomic bond energy on the surface of the SiO _x layer, and have a function of cutting or weakening the Si—O bonds. (B) CF _x ⁺ (typically x = 3), which is the main etching species of the SiO ₂ layer, can be generated, and (c) the C / F ratio of the etching reaction system (the ratio of the number of C atoms to the number of F atoms) ) To optimize the amount of carbon-based polymer deposited and achieve high selectivity with respect to the resist mask and the underlying material layer.

[0004] The underlying material layer referred to here mainly refers to a silicon-based material layer such as a silicon substrate, a polysilicon layer, and a polycide film.

On the other hand, a silicon nitride (Si _x N _y; especially x
= 3, y = 4) are also insulating film materials applied to silicon devices. The dry etching of Si _x N _y layer,
Basically, a gas composition similar to that used for etching the SiO _x layer is applied. However, while the SiO _x layer is etched by a mechanism mainly based on the ion assist reaction,
Si _x N _y layer is etched on the basis of the radical reaction mechanism as a main etching species F ^*, faster than the etching speed SiO ₂ layer.

Incidentally, there are several steps in the manufacturing process of silicon devices that require highly selective etching between the SiO _x layer and the Si _x N _y layer.

For example, Si _x N on a SiO _x layer
The etching of the _y layer is performed at the time of patterning for defining an element isolation region in the LOCOS method. LOC
In the OS method, a Si _x N _y layer serving as an oxidation mask is etched on a pad oxide film (SiO ₂ layer). In recent years, this pad oxide film is formed to be extremely thin in order to minimize the bird's beak length. Therefore, high selectivity is required.

Further, miniaturization of the device, and an increasing number of cases of Si _x N _y layer with the complex is formed in many places as an etch stop layer to prevent etching damage, Si _x N _y The need also arises for highly selective etching of the SiO _x layer on the layer.

[0009] For example, thin on the surface of the substrate in order to reduce the substrate damage during the over-etching Si _x N _y
Layers or so-called ONO (SiO _x / S
i _x N _y / SiO _x) or have a gate insulating film is formed to have a structure, further or Si on the surface of the gate electrode
_{if x} N _y layers are stacked must reliably stop the etch of the SiO _x layer is performed on the surface of the Si _x N _y layer.

[0010] In general, high selective etching between different material layers to be laminated is easier when the values of the interatomic bond energies of the two material layers are largely different from each other.
However, if the SiO _x layer and the Si _x N _y layer, a high selective etching is difficult because the value of the SiO bond and Si-N bonds of interatomic bond energy is relatively close.

[0011] Therefore, Si _x N _y on the SiO _x layer
Several methods have been proposed for selective etching of layers.

For example, the applicant of the present application has previously described in
No. 142744 discloses that a gas such as CH ₂ F ₂ having a small C / F ratio (ratio of the number of C atoms to the number of F atoms in a molecule) has C
O ₂ and disclose a technique of using mixed etchant gas in a molar ratio of 30% to 70%. This can be achieved by reducing the production of by generating CO ^* in plasma to capture a portion of the F ^*, CF _x ⁺ (especially x = 3) produced by the recombination of F ^*, Si _x N _{This is} to significantly lower the etching rate of the SiO _x layer compared to the etching rate of the _y layer.

[0013] The proceedings of symposium on dry process (Proceedings of Symposium)
posium on Dry Process), Vol. 88, No. 7, pp. 86-94 (1987), NF ₃ and Cl ₂ are supplied to a chemical dry etching apparatus, and FCCl generated in a gas phase by microwave discharge is disclosed. Utilizing Si on SiO _x
technique of etching the _x N _y layer is described. Si
The -O bond contains 55% of ionic bondability, whereas Si-
The N bond is 30%, and the ratio of covalent bonds is high. That is, the nature of the chemical bonds of Si _x N _y layer is close to that of the chemical bonding of a single crystal silicon (covalent bond), F ^* generated dissociated from FCl, it is etched by radicals such as Cl ^*. On the other hand, since the SiO _x layer is hardly etched even by these radicals, highly selective etching becomes possible.

[0014]

As described above, the etching reaction system in which F ^* is present causes the Si on the SiO _x layer to be formed on the SiO _x layer.
For _x N _y layer is selectively etched technique, there are several proposals. The high degree of feasibility is based on the fact that the magnitude relationship between the interatomic bond energies is as follows:
From the fact that Si—O bond (465 kJ / mol)> Si—N bond (440 kJ / mole), it can be imagined to some extent. That is, if the process of etching the Si _x N _y in mechanism mainly composed of radical reaction, the etching rate at the time when the SiO _x layer is exposed on the way is because inevitably reduced.

However, this technique also has a problem. For example, in the above-described process using FCl, anisotropic processing is essentially difficult because a radical reaction is used.

On the other hand, on the other hand, S on the Si _x N _y layer
There are few reports on the technique of selectively etching the iO _x layer because it is difficult to ensure the selectivity. this is,
SiO _x by a mechanism mainly based on ion assist reaction
Also be etched layers, that are always radicals in the reaction system is generated, because the etching rate of the underlayer by the radical when Si _x N _y is exposed is increased.

Recently, there has been proposed a technique for realizing this by using a high-density plasma in which the amount of radical generation is reduced by employing a new plasma source. For example,
Proceedings of the Forthird Symposium on Semiconductors and Integrated Circuits Technology (Proceedi
ngs of the 43rd Symposium on Semiconductors and In
integrated Circuits Technology), p. 54 (199
2) includes inductively coupled plasma of C ₂ H ₆ gas (ICP =
Induction Coupled Plasma)
Is used to etch the SiO _x layer formed by the TEOS-CVD method on the Si ₃ N ₄ layer formed by the LPCVD method using C ₂ F ₆ (hexafluoroethane), and a part of the gate electrode is formed. An example process for opening overlapping connection holes is described. In a high-density plasma, the dissociation of the gas proceeds to a high degree, so that C ₂ F ₆ is decomposed into CF ⁺ having a small ionic amount, which is considered to contribute to etching. In addition, C /
C atoms in the lower F ratio fluorocarbon polymer, since Si _x N easily combined with O atoms in the SiO _x than N atom in _y, but is removed at the surface of the SiO _x layer, Si _x N Deposits on _y . This is the interpretation of the mechanism of achieving selectivity.

This technique is quite promising, but has the drawback that it is difficult to obtain stable selectivity. For example, the selectivity in the above-described process is infinite at the flat portion, but drops to a level of at least 20 at the corner portion. The in-plane variation of the selectivity is C ₂ F
_This is probably due to the contribution of F ^* generated as a result of the advanced dissociation of ₆ .

Accordingly, an object of the present invention is to provide a dry etching method for an SiO _x layer that can ensure a high selectivity with respect to a Si _x N _y layer.

[0020]

SUMMARY OF THE INVENTION The selective etching method of the present invention is proposed in view of the above-mentioned object, and is provided on a substrate having a silicon oxide-based material layer formed on a silicon nitride-based material layer. In the step of selectively etching the silicon oxide-based material layer, in the just etching step of etching the silicon oxide-based material layer substantially by the thickness thereof, an etching gas mainly containing a fluorocarbon-based compound was used. In the over-etching step of performing dry etching to etch the remaining portion of the silicon oxide-based material layer, dry etching using an etching gas containing the fluorocarbon-based compound and the nitrogen-containing organic silicon compound is performed.

As the above fluorocarbon compound,
A compound generally used for etching the silicon oxide-based material layer can be appropriately selected and used.

After the completion of the over-etching step, the substrate may be subjected to a hot phosphoric acid solution treatment to dissolve and remove silicon nitride-based deposits deposited during the over-etching.

In the above-described selective etching, a resist pattern is usually used as an etching mask. After the etching, ashing with oxygen-based plasma is performed to remove the resist pattern. In this case, the hot phosphoric acid solution treatment is desirably performed before ashing. This is because, if ashing is performed first, silicon nitride-based deposits deposited on the surface of the resist pattern may be oxidized and silicon oxide-based particles may be generated.

If the underlying silicon nitride-based material layer is relatively thin and deterioration of the anisotropic shape is not so problematic, the treatment time of the hot phosphoric acid solution treatment is appropriately extended to obtain The silicon-based material layer can be etched.

Contrary to the above-described process, when the silicon oxide-based material layer underneath is selectively etched using the silicon nitride-based material layer patterned into a predetermined shape as a mask, fluorocarbon is used as the etching. Dry etching is performed using an etching gas containing a base compound and a nitrogen-containing organic silicon compound.

Here, as the nitrogen-containing organosilicon compound used in the present invention, a compound capable of forming a silicon nitride-based deposit in a chemical vapor reaction system is used. This is to improve the selectivity to the underlying silicon nitride-based material layer during overetching. In order to efficiently produce a silicon nitride-based deposit, an azide group (—N ₃ ) or a dialkylamino group (—N
It is preferable to use a compound in which at least one of R ₂ ) is bonded to a Si atom. That is, these compounds have a Si-N bond. Further, an alkyl group or an alkoxyl group may be bonded to a part of a bond of a Si atom so that the generated film-forming precursor has improved fluidity. The nitrogen-containing organosilicon compound satisfying such requirements can be represented by the following general formula.

[0027] _{Si n (NR 2) w (} N 3) x (R ') y (OR ") z , however, n, w, x, y , z is n ≧ 1, w + x + y + z
= 2n + 2, 0 ≦ w ≦ 2n + 2, 0 ≦ x ≦ 2n + 2, 1,
≤w + x≤2n + 2, 0≤y≤2n + 1, 0≤z≤2n
It is an integer satisfying the relationship of +1. R is a hydrocarbon group, which may be saturated / unsaturated or linear / branched / cyclic. Examples of R include a methyl group, an ethyl group and a cyclopentadienyl group. Further, R ′ and R ″ represent an alkyl group. The applicant of the present invention has a formula of CV of silicon nitride based thin film.
It is proposed as a gas for D.

[0028]

According to the present invention, high selectivity to the silicon nitride-based material layer during etching of the silicon oxide-based material layer is achieved by the nitrogen-containing organic silicon compound added to the etching gas. This high selectivity results from the competition between the process of depositing silicon nitride-based deposits generated in the gas phase from the nitrogen-containing organosilicon compound on the exposed surface of the silicon nitride-based material layer and the process of removing by sputtering. I do. Therefore, this nitrogen-containing organosilicon compound is added to the etching gas in the over-etching step when the silicon nitride-based material layer is a base for etching, and the silicon nitride-based material layer is used as an etching mask. In the case of, the effect of improving selectivity is exhibited by being added to the gas system from the beginning of etching.

In the present invention, since such high selectivity is obtained due to the deposit from the gas phase, the selectivity is not so high as in the case of using a high-density plasma of a conventional high-order fluorocarbon-based gas. There is no internal variation.

The silicon nitride-based deposit generated during the dry etching can be dissolved and removed by performing a hot phosphoric acid solution treatment after the completion of the etching, so that it does not cause any contamination on the substrate.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Embodiment 1 In this embodiment, in a process of opening a contact hole by dry etching in a SiO _x interlayer insulating film having a Si _x N _y underlayer, c
-C ₄ F ₈ (octafluorocyclobutane) gas, c-C ₄ F ₈ / overetching step _{[(CH 3) 2 N]} 4 S
This is an example using an i (tetradimethylaminosilane) mixed gas. This process will be described with reference to FIGS.

First, as shown in FIG. 1, on a silicon substrate 1 on which an impurity diffusion region (not shown) has been formed in advance, a 6 nm-thick Si _x N _y is formed by, eg, LPCVD.
A base film 2 is formed, and then a layer thickness of 50
A 0 nm SiO _x interlayer insulating film 3 was formed. Further, on this SiO _x interlayer insulating film 3, a chemically amplified positive photoresist material (WKR-PT2, manufactured by Wako Pure Chemical Industries, Ltd.)
Was patterned by KrF excimer laser lithography and development to form a resist mask 4 having an opening 5 having a diameter of about 0.35 μm.

Next, the wafer was set in a magnetic field microwave plasma etching apparatus, and the SiO _x interlayer insulating film 3 was just etched under the following conditions as an example.

C-C ₄ F ₈ flow rate 40 SCCM gas pressure 0.27 Pa microwave power 1200 W (2.45 G
Hz) RF bias power 225 W (800 kHz)
z) Wafer temperature 20 ° C. In this just etching step, a large amount of CF _x ⁺ generated in high-density plasma of a higher-order fluorocarbon-based gas is used.
And F ^* , the SiO _x interlayer insulating film 3 was subjected to high-speed anisotropic etching, and a contact hole 6 was formed halfway.

The state of the wafer after the completion of the just etching is as shown in FIG. That is, due to the variation of the etching rate in the wafer surface, the underlying Six _{x Ny} underlying film 2 starts to be exposed in a certain region.
In other regions, as shown in the figure, a small portion of the SiO _x interlayer insulating film 3 remains.

Next, as an example, the etching conditions were changed as follows, and over-etching was performed to remove the remaining portion.

C-C ₄ F ₈ flow rate 40 SCCM [(CH ₃ ) ₂ N] ₄ Si flow rate 10 SCCM gas pressure 0.27 Pa microwave power 1200 W (2.45 G
Hz) RF bias power 225 W (800 kHz)
z) wafer temperature 20 ° C. In this over-etching process, as shown in FIG. _{3, [(CH 3) 2} N] Si x N y based deposits 7 for generating from ₄ Si is Si _x N _y underlayer 2 In order to protect the exposed surface, the remaining portion of the SiO ₂ interlayer insulating film 3 was etched while ensuring a high selectivity of about 40 with respect to the Si _x N _y base film 2.

The Si _x N _y based deposit 7 was also deposited on the surface of the resist mask 4.

Next, the wafer was immersed in a hot phosphoric acid solution. As a result, as shown in FIG. 4, Si _x N _y based deposits 7, and S is exposed to the contact hole 6
i _x N _y underlayer 2 is dissolved and removed, the contact hole 6 is completed. At this time, no damage occurred to the underlying impurity diffusion region.

Finally, as shown in FIG. 5, the resist mask was removed by O ₂ plasma ashing.

[0042] Example 2 In this example, a so-called ONO structure (SiO _x / Si _x
When a sidewall made of a SiO _x layer is formed by etch-back on both side walls of a gate electrode formed on a gate insulating film having a N _y / SiO _x laminate structure, CHF ₃ (trifluoromethane ) Gas, CHF ₃ / (C ₂
H ₅₎ using ₃ SiN ₃ (triethylsilyl azide) mixed gas. This process will be described with reference to FIGS. This process is included in the manufacturing process of the MOS-FET having the LDD structure.

First, as shown in FIG.
Lower SiO _x film 12 on 1 (film thickness of about 40 nm), middle S
i _x N _y film 13 (thickness: about 60 nm) and upper SiO _x film
A gate insulating film 15 having an ONO structure made of a film 14 (about 20 nm in thickness) is formed, and an n ⁺ -type polysilicon layer is patterned thereon to form a gate electrode 16, and ions using the gate electrode 16 as a mask are formed. A low-concentration impurity diffusion region (not shown) was formed in the Si substrate 11 by implantation, and an SiO _x film 17 was formed by covering the entire surface of the wafer.

This wafer was set in a magnetic field microwave plasma etching apparatus, and as an example, Si was obtained under the following conditions.
The _Ox film 17 was etched back.

CHF ₃ flow rate 30 SCCM Gas pressure 0.27 Pa Microwave power 1200 W (2.45 G
Hz) RF bias power 200 W (800 kHz)
z) Wafer temperature: 20 ° C. This etch back was performed until just before the gate electrode 16 was exposed, as shown in FIG. At this time, in the portion facing the low concentration impurity diffusion region, the upper layer SiO _x film 1
5 may be etched away, but the middle layer S
It is particularly desirable to i _x N _y film 14 is etched is stopped immediately before the exposure.

Next, the etching conditions were changed as an example as follows, the residual portion and the upper layer Si of SiO _x film 17
The exposed portion of the O _x film 14 is removed.

CHF ₃ flow rate 40 SCCM (C ₂ H ₅ ) ₃ SiN ₃ 10 SCCM gas pressure 0.27 Pa microwave power 1200 W (2.45 G
Hz) RF bias power 200 W (800 kHz)
z) Wafer temperature 20 ° C. By this over-etching, SiO _x sidewalls 17s as shown in FIG. 8 were formed. At this time, about relative Si _x N _{for y} based deposits reduces the etch rate in the vertical plane of incidence of the ion, middle Si _x N _y film 14 exposed generated from _{(C 2 H 5) 3 SiN} 3 40 High selectivity was achieved.

The Si _x N _y deposited on the surface of the wafer
The system deposits could be removed by hot phosphoric acid solution treatment.

[0049] EXAMPLE 3 In this example, Si _x N in SiO _x interlayer insulating film through a _y mask in the process of opening the contact _{hole, c-C 4 F 8 /} (C 2 H 5) 2 Si ( A mixed gas of N ₃ ) ₂ (octafluorocyclobutane / diethylsilyldiazide) was used. This process will be described with reference to FIGS.

First, as shown in FIG. 9, an SiO _x interlayer insulating film 22 having a thickness of about 1 μm is deposited on a Si substrate 21 on which an impurity diffusion region (not shown) has been formed in advance by a normal pressure CVD method. and to form a Si _x N _y mask 23 thereon. The Si _x N _y mask 23 has an opening width of about 0.35 μm by patterning a Si _x N _y layer formed by a plasma CVD method and having a thickness of about 100 nm using a resist mask (not shown). Is formed. The resist mask has already been removed by ashing.

The wafer was set in a magnetic field microwave plasma etching apparatus, and as an example, Si was obtained under the following conditions.
The dry etching of O _x interlayer insulating film 22 was performed.

[0052] c-C ₄ F ₈ flow rate _{30 SCCM (C 2 H 5)} 2 Si (N 3) 2 5 SCCM Gas pressure 0.27 Pa microwave power 1200 W (2.45 G
Hz) RF bias power 225 W (800 kHz)
The z) wafer temperature 20 ° C. Here, since the layer comprising the previously Si _x N _y before starting the etching (Si _x N _y mask 23) is exposed, the nitrogen-containing organic silicon compound from the beginning [(C ₂ H _{5) 2} Si
(N ₃ ) ₂ ] was used. During etching, the surface of the Si _x N _y mask 23 is protected by the Si _x N _y based deposits (not shown.), The occurrence of pattern shift Ri by retraction of the mask is prevented, FIG. 10 As shown, a contact hole 25 having a good anisotropic shape was formed. The mask selection ratio in the present embodiment is:
It was about 30.

Embodiment 4 In this embodiment, in a process of opening a contact hole in a self-aligned manner in an SiO _x interlayer insulating film in order to connect a gate electrode of a load TFT of an SRAM and a storage node, a just etching step is performed. in c-C ₄ F ₈ gas, c-C ₄ overetching step _{F 8 / [(CH 3)} 2 N] 4
A mixed gas of Si (octafluorocyclobutane / tetradimethylaminosilane) was used. This process is illustrated in FIG.
This will be described with reference to FIGS.

FIG. 11 shows the configuration of a wafer used as an etching sample in this embodiment. That is, a gate oxide film 32 is formed on a Si substrate 31 by thermal oxidation, and two gate electrodes 3 of a driver transistor are formed thereon.
5, and an offset oxide film 36 composed of a SiO _x layer was formed in a common pattern. Here, the gate electrode 3
5 consists of the lower polysilicon layer in this order from the side 33 and a tungsten silicide (WSi _x) layer 34 and a tungsten polycide film laminated the. SiO _x sidewalls 37 are formed on both side walls of the gate electrode 35 by an etch-back process, and impurities having an LDD structure are formed by ion implantation twice using the gate electrode 35 and the SiO _x sidewalls 37 as masks. A diffusion region (not shown) was formed in the silicon substrate 31.

Further, for example, a reduced pressure CV
The Si _x N _y etch stop layer 38 is deposited by method D,
An SiO _x interlayer insulating film 39 was deposited thereon by normal pressure CVD to flatten the wafer surface, and a resist mask 40 having a predetermined pattern was formed thereon. The resist mask 40 has an opening 41 facing the space between the gate electrodes.

Next, the etching of the SiO _x interlayer insulating film 39 is performed by just etching or over etching.
It went in stages. The etching conditions at each stage are the same as those described in the first embodiment. First, the c-C ₄ F ₈ gas is used to form the SiO _x interlayer insulating film 39 immediately before the underlying Six _x N _y etching stop layer 38 is exposed. Then, the remaining portion of the SiO _x interlayer insulating film 39 was over-etched using a mixed gas of c—C ₄ F ₈ / [(CH ₃ ) ₂ N] ₄ Si. Thus, as shown in FIG. 12, contact holes 42 while maintaining a high selectivity with respect to Si _x N _y etch stop layer 38 is opened halfway.

Further, a hot phosphoric acid treatment is performed to deposit Six _x N _y -based deposits (not shown) deposited on the wafer surface, and a Six _x N _y etching stop layer 38 exposed at the bottom of the contact hole 42. Was dissolved and removed to complete the contact hole 42.

There are various modifications of the self-aligned contact structure. For example, as shown in FIG. 14, the opening position of the contact hole may be about half of the space between the gate electrodes. In this case, Si
When it _x N _y to the formation of the etch stop layer 38 is the same as in Example 4 above, the on the flatly coated with SiO _x interlayer insulating film 43, a resist mask 44,
The position of the opening 45 is narrowed as shown, and a contact hole 46 is formed.

[0059] Further alternatively, without providing the Si _x N _y etch stop layer can also form side walls by Si _x N _y layer.

For example, as shown in FIG.
A gate oxide film 52 on the substrate 51, and the polysilicon layer 53 and the WSi _x layer 54 is the two gate electrodes 55 are sequentially formed comprising laminated, Si _x N _y sidewalls 56 on both sides wall by etch back These surfaces are flatly covered with a SiO _x interlayer insulating film 57, and a resist mask 58 having an opening 59 thereon is further formed.
When the present invention is applied when Si _x N is formed,
_The contact hole 60 can be opened while maintaining a high selectivity with respect to the _y side wall 56.

Although the present invention has been described based on the four embodiments, the present invention is not limited to these embodiments, but includes a fluorocarbon-based compound used as an etching gas and a combination thereof. Any of the nitrogen-containing organic silicon compound, the configuration of the sample wafer, the etching conditions, the etching apparatus used, and the like can be appropriately changed.

[0062]

As is clear from the above description, according to the selective etching method of the present invention, the selective etching of silicon oxide-based material and silicon nitride-based material, which has been difficult in the prior art, can be performed with a high selectivity and excellent surface area. It is possible to perform with uniformity inside. In particular, since the selective etching of the SiO _x silicon-based material layer on the silicon nitride-based material layer becomes possible, the process and the device structure can be widely selected.

Therefore, the present invention is designed based on fine design rules, is suitable for manufacturing a semiconductor device having a high degree of integration and high performance, and its industrial value is extremely large.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a state of a wafer before starting etching in a process example in which the present invention is applied to contact hole processing.

FIG. 2 is a schematic cross-sectional view showing a state where the SiO _x interlayer insulating film of FIG. 1 is just etched.

FIG. 3 is a schematic cross-sectional view showing a state in which the SiO _x interlayer insulating film of FIG. 2 is over-etched.

4 is a schematic cross-sectional view of the Si _x N _y based deposits and Si _x N _y underlayer is selectively removed illustrating a state in which to complete the contact holes of FIG.

FIG. 5 is a schematic cross-sectional view showing a state where the resist mask of FIG. 4 is removed.

FIG. 6 is a schematic cross-sectional view showing a state of a wafer before the start of etching in a process example in which the present invention is applied to the formation of an LDD sidewall on a gate insulating film having an ONO structure.

FIG. 7 is a schematic cross-sectional view showing a state in which the SiO _x film of FIG. 6 is etched back immediately before a base is exposed.

FIG. 8 is a view showing a state where the remaining portion of the SiO _x film shown in FIG.
FIG. 4 is a schematic cross-sectional view showing a state where a DD sidewall is completed.

Contacts 9 The present invention by Si _x N _y mask
FIG. 9 is a schematic cross-sectional view showing a state of a wafer before starting etching in a process example applied to hole processing.

FIG. 10 is a schematic cross-sectional view showing a state where a contact hole is formed by etching the SiO _x interlayer insulating film of FIG. 9;

FIG. 11 is a schematic cross-sectional view showing a state of a wafer before starting etching in a process example in which the present invention is applied to a self-aligned SRAM contact hole processing.

12 is a schematic cross-sectional view showing a state in which the SiO _x interlayer insulating film of FIG. 11 is etched and a contact hole is partially opened.

[13] The Si _x N _y etch stop layer exposed to the bottom surface of the contact hole 12 is removed contact
FIG. 4 is a schematic cross-sectional view showing a state where a hole is completed.

FIG. 14 is a schematic cross-sectional view showing a state in which an SiO _x interlayer insulating film is etched in another process example of the self-aligned contact processing of the SRAM.

FIG. 15 is a schematic cross-sectional view showing a state where a contact hole is completed in still another process example of the self-aligned contact processing of the SRAM.

[Explanation of symbols]

1,11,21,51 silicon substrate 2 Si _x N _y underlayer 3,22,39,43,57 SiO _x interlayer insulating film 4,40,44,58 resist mask 6,25,42,46,60 Contacts Hall 13 middle Si _x N _y film 14 upper SiO _x film 16,35,55 gate electrode 17 SiO _x film 17s, 37 SiO _x sidewall 36 offset oxide film 38 Si _x N _y etch stop layer 56 Si _x N _y side Wall

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065 C23F 4/00 H01L 21/205

Claims (4)

(57) [Claims] 1. A selective etching method for selectively etching a silicon oxide-based material layer on a substrate in which a silicon oxide-based material layer is formed on a silicon nitride-based material layer, comprising: In the just etching step of etching substantially by the thickness of the layer, dry etching using an etching gas mainly containing a fluorocarbon-based compound is performed, and in the over-etching step of etching the remaining portion of the silicon oxide-based material layer, the fluorocarbon is used. Etching containing nitrogen-based compound and nitrogen-containing organic silicon compound
A selective etching method comprising performing dry etching using a gas. 2. The selective etching method according to claim 1, wherein, after the over-etching step, a hot phosphoric acid solution treatment is performed on the substrate. 3. A selective etching method for selectively etching a silicon oxide-based material layer below a silicon nitride-based material layer patterned in a predetermined shape as a mask, wherein the etching includes a fluorocarbon-based compound and a nitrogen-containing organic compound. A selective etching method comprising performing dry etching using an etching gas containing a silicon compound. 4. The compound according to claim 1, wherein at least one of an azide group and a dialkylamino group is bonded to a Si atom as the nitrogen-containing organic silicon-based compound. Item 4. The selective etching method according to item 1.