JP3256185B2 - Run-length code error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a run-length code error correction apparatus for correcting an error in digital data by referring to the run-length.

[0002]

2. Description of the Related Art In the present specification, a run-length code error correction device is abbreviated as an RLL error correction device.
RLL is an abbreviation for Run Length Limited. First,
Referring to FIG. 6, as a conventional RLL error correction device,
What is disclosed in JP-A-6-112846 will be described. In FIG. 6, the RLL error correction device is NR
It includes a ZI conversion unit 61, a prohibited pattern detection unit 62, a pattern conversion unit 63, and an error correction unit 64.

[0003] The NRZ-I conversion section 61 has a NRZ (Non Ret
urn to Zero) modulates the digital data into NRZ-I
(Non Return to Zero Inverse), and outputs the result to the prohibited pattern detection unit 62. The prohibition pattern detection unit 62 detects whether or not the input digital data includes a prohibition pattern including a bit pattern “11” (a bit pattern with a run length of 0). When a predetermined prohibition pattern is detected, the pattern conversion unit 63 converts this prohibition pattern “11” into a bit pattern “01”. The error correction unit 64 performs error correction using an error correction code on the error-corrected digital data, and outputs the digital data as error-corrected symbol data.

[0004]

Such an RLL error correction apparatus converts a prohibited pattern "11" to a bit pattern "01" so that the run length is "0".
Can be eliminated from the digital data. Next, with reference to FIG. 7, a process of error correction by the prohibited pattern detection unit 62 and the pattern conversion unit 63 will be specifically described. FIG. 7 (a) shows the NRZ-I conversion unit 61.
It is assumed that NRZ-modulated digital data including the bit pattern “010001” shown in FIG. FIG.
The digital data of (a) is converted by the NRZ-I converter 61 into a bit pattern “011001” shown in FIG.
Are converted to NRZ-I-modulated digital data. Here, in run-length encoding, at least the lower limit of the run-length is determined. For example, when the lower limit is “2”, it can be estimated that the bit pattern “11” (run length is “0”) is incorrect.

The prohibition pattern detection section 62 detects the prohibition pattern “11” from the bit pattern “011001”, and the pattern conversion section 63 converts the detected prohibition pattern “11” into the pattern “01”. As a result, the digital data input to the error correction unit 64 is
The bit pattern “001001” shown in FIG.

[0006] However, the NRZ-I conversion unit 61
If there is a change in value between two consecutive bits, the value is converted to "1". If there is no change, the value is converted to "0". In consideration of such NRZ-I modulation, the total number of “1” in the bit pattern after error correction is determined by the NR having an error.
An odd number is reduced as compared with that of the ZI modulated bit pattern (see FIGS. 7B and 7C). When the NRZ-I-modulated digital data after the error correction is NRZ-modulated again, it becomes digital data including the bit pattern shown in FIG. Comparing the bit patterns of FIGS. 7D and 7A shows that the bit patterns of “1” and “0” after the error-corrected portion are all inverted. Therefore, the digital data input to the error correction unit 64 has a problem that an error exists at one or more other bit positions. Such a problem needs to be solved because the RLL error correction device is required to be able to correct more errors while reducing erroneous corrections.

Therefore, an object of the present invention is to provide an RLL that can correct more errors while reducing the number of erroneous corrections compared to the prior art.
An object of the present invention is to provide an error correction device.

[0008]

A first aspect of the present invention is a run-length error correction device for correcting an error in digital data by referring to the run-length, and comprising:
A first converter for converting the modulated digital data into NRZ-I modulated digital data, and a prohibited run from the digital data converted by the first converter by one less than a preset lower limit of run length. A detecting unit that detects the length, a first run length that is located in front of the prohibited run length and is larger than the lower limit value, and detects the first run length when the prohibited run length and the first run length are detected. A second converter for reducing the forbidden run length to a lower limit by shortening by 1 and an error correction unit for performing error correction based on an error correction code of digital data processed by the second conversion unit; .

In a transmission path or in a recording / reproducing process, the quality of digital data may be degraded due to delay or noise. In the first invention, when a prohibited run length and a first run length larger than a lower limit value are detected in front of the prohibited run length, the first run length is reduced by one and the conversion is performed so that the prohibited run length becomes the lower limit value. Therefore, the second conversion unit:
Even if error correction is performed on the NRZ-I modulated digital data, it is possible to prevent the bit pattern after the correction point from being inverted. That is, according to the processing of the second conversion unit, erroneous correction of the bit pattern is reduced as compared with the conventional one. Therefore, the error correction unit at the subsequent stage can perform error correction based on the error correction code on the digital data with few errors, and can correct more errors.

A second invention is dependent on the first invention,
The detection unit further includes a forbidden run length, a second run length located in front of the forbidden run length and equal to or less than the lower limit, and a third run length located behind the forbidden run length and greater than the lower limit. Upon detecting the prohibited run length, the second run length, and the third run length, the second conversion unit further shortens the third run length by 1 and sets the prohibited run length to a lower limit. Elongate.

In the second invention, when the first run length cannot be detected, the detecting section detects the prohibited run length, the second run length located in front of the prohibited run length, and the third run length located in rear of the prohibited run length. Then, the third run length is reduced by one, and the conversion is performed so that the prohibited run length becomes the lower limit. Therefore, the second conversion unit can correct more bit pattern errors than that of the first invention. Therefore, the error correction unit at the subsequent stage can perform error correction based on the error correction code on the digital data in which more errors have been corrected, and thus can correct more errors than in the first invention.

A third invention is dependent on the first invention,
The detecting unit further detects a prohibition pattern of “11”, and when the prohibition pattern is detected, the second conversion unit further converts the prohibition pattern into a pattern of “00”.

In the third aspect, the bit pattern "11" included in the digital data is regarded as an error due to noise, and is set as a prohibition pattern. This prohibition pattern is converted into a bit pattern “00”. As a result, a bit pattern having a run length of 0 disappears from the digital data. Thereby, the error correction capability of the above-described bit pattern is further improved. Therefore,
The error correction unit can perform error correction based on the error correction code on the digital data in which more errors have been corrected, and thus can correct more errors than in the first invention.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a CD reproducing apparatus as an example of a device including an RLL error correction apparatus according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, a CD reproducing device includes a servo unit 1, a motor 2,
It includes a pickup 3, an RF amplifier 4, an RLL error correction device 5, a signal processing unit 6, and a D / A converter 7. The servo unit 1 controls an R (to be described later) so that a compact disk (hereinafter referred to as a CD) 8 rotates at a predetermined rotation speed.
The motor 2 is controlled using the output signal of the F amplifier 4.
The pickup 3 reads the RF signal from the rotating CD 8. The read RF signal is amplified and waveform-shaped by the RF amplifier 4, and then an error signal for servo or 8
The error signal is converted into a −14 modulated EFM signal, the error signal is fed back to the servo unit 1 (described above), and the
The M signal is output to the RLL error correction device. The RLL error correction device 5 performs an error correction process described later on the input signal and outputs an error-corrected signal to the signal processing unit 6. The signal processing unit 6 applies 8
-14 Performs demodulation and deinterleaving / error correction of a cross-interleaved Reed-Solomon code (hereinafter, referred to as CIRC), and outputs demodulated symbol data to the D / A converter 7. The D / A converter 7 performs D / A conversion on the input symbol data, and outputs it as an audio signal.

Next, the RLL error correction device 5 will be described with reference to FIGS. The RLL error correction device 5 shown in the block diagram of FIG. 2 is different from the conventional device shown in FIG.
3, a prohibited run length / prohibited pattern detector 2
1 and a run length / pattern conversion unit 22. Since there are no other differences, in the configuration shown in FIG. 2, those corresponding to FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

The forbidden run length / inhibited pattern detecting section 21 selects the forbidden run length, the first to third run lengths related to the forbidden run length and the forbidden run length from the digital data converted by the NRZ-I conversion section 61. A pattern (details will be described later) is detected. When the forbidden run length and the first to third run lengths or the forbidden patterns related thereto are detected, the run length / pattern conversion unit 22 performs an error correction process according to the detected forbidden run length and the digital data error. To correct. There are three types of error correction processing, specifically, forward error correction, backward error correction, and replacement error correction.

Next, the RLL error correction device 5 having the above configuration
Will be described with reference to FIGS. 2 and 3. FIG. NRZ-I converted digital data is input to the NRZ-I conversion unit 61. This digital data includes, for example, an erroneous bit pattern “000011000” as shown in FIG. In this bit pattern, the direction indicated by arrow A is the front as the bit position, and the direction indicated by arrow B is the rear as the bit position. That is, the italicized bit “0” is first input to the NRZ-I conversion unit 61, and subsequent bits are input in order. The digital data of FIG. 3A is converted by the NRZ-I conversion unit 61 into an NRZ signal including a bit pattern “00010100” as shown in FIG.
-Converted into I-modulated digital data.

The digital data converted by the NRZ-I conversion unit 61 is output to the prohibited run length / prohibited pattern detection unit 21. The prohibition run length / prohibition pattern detection unit 21 sets the bit pattern of the input digital data to a prohibition run length that is smaller than a preset lower limit of the run length by one, and forwards the prohibition run length (specifically, (I.e., immediately before) and a first run length greater than the lower limit is detected. As described above, the lower limit of the run length is predetermined. For example, in a run-length encoding method used for a CD reproducing device, the lower limit is “2”. In this case, the prohibited run length is “1”, and the first run length is longer than “2”. Therefore, the forbidden run length / prohibited pattern detection unit 21 detects the forbidden run length at the fifth bit of the input bit pattern (see FIG. 3B), and further, sets the first to third bits as the first forbidden run length. Detect run length. In the bit pattern of FIG. 3B, the bit “0” in italic is counted as the first bit for convenience.

The run length / pattern conversion section 22 shortens the detected first run length by one, and further extends the detected forbidden run length in the forward direction so as to set the lower limit to the lower limit. change. Therefore, FIG.
The bit pattern of (b) is converted by the run-length / pattern conversion unit 22 into the bit pattern “0” shown in FIG.
0100100 ". In other words, the run-length / pattern conversion unit 22 inverts the third bit and the fourth bit “01” included in the bit pattern of FIG. 3B, and converts the inverted bit pattern into the bit pattern of FIG. As a result, the run length of the fourth and fifth bits becomes 2 (lower limit), and the prohibited run length that is estimated to be an error is corrected from the bit pattern of FIG.

According to the above forward error correction, FIG.
The pulse width of the NRZ-modulated digital data in (a) is expanded in the forward direction. That is, when the digital data of FIG. 3B is subjected to NRZ modulation, digital data having the bit pattern “000111000” shown in FIG. 3D is generated. The pulse width of the digital data in FIG. 3D is more clearly understood to be wider in the front direction than that in FIG. 3A. by the way,
Since a short pulse contains many high frequency components, the phase characteristics of a transmission path or a recording / reproducing system circuit are different from ideal. Generally, the higher the frequency, the larger the phase delay, so that correcting the edge of the pulse in the forward direction has a higher probability of correct error correction. Therefore, forward error correction is preferable to backward error correction described later.

FIG. 3 shows the error corrected as described above.
The digital data (c) is output from the run-length / pattern conversion unit 22 to the error correction unit 64. The error correction unit 64 performs an error correction process based on the error correction code of the input digital data. When the present RLL error correction device 5 is applied to a CD playback device, this error correction
This is performed based on the IRC.

As described above, before the error correction unit 64 performs the error correction, the forward error correction is performed so that the error correction is reduced as much as possible. For this reason, the error correction unit 64 performs error correction on digital data with less erroneous correction, so that more errors can be corrected as compared with the conventional one.

By the way, in forward error correction, when the first run length is equal to or smaller than the lower limit, the prohibited run length cannot be corrected. This is because the first run length itself becomes less than or equal to the lower limit. The process of correcting such prohibited run length is backward error correction. Hereinafter, the backward error correction of the RLL error correction device 5 will be described with reference to FIGS.
This will be described with reference to FIG. 4 is referred to in FIG.
It is similar to that of

NRZ input to NRZ-I converter 61
The modulated digital data has, for example, an error-containing bit pattern “1000110” as shown in FIG.
000 ". The digital data in FIG.
The data is converted into digital data having the bit pattern “100101000” shown in FIG. 4B by the RZ-I modulation, and is output to the prohibited run-length / prohibited pattern detection unit 21.

Forbidden run length / inhibited pattern detector 2
1 is the bit pattern of the input digital data,
The above-described prohibited run length, a second run length located in front of the prohibited run length and equal to or less than the lower limit, and located behind (specifically, immediately after) the prohibited run length and larger than the lower limit. It is detected whether or not the third run length is included. This lower limit is “2” as described above.
And Therefore, the second run length is less than or equal to "2" and the third run length is greater than "2". The prohibited run length / prohibited pattern detection unit 21 detects the prohibited run length at the fifth bit of the bit pattern in FIG. 4B, and further detects the second run length at the second and third bits. , The third run length is detected at the 7th to 9th bits.

The run length / pattern conversion section 22 shortens the detected third run length by one, further extends the detected forbidden run length in the backward direction to a lower limit value, and converts both run lengths. change. Therefore, FIG.
The bit pattern of (b) is converted into the bit pattern “100100100” shown in FIG. In other words, the run-length / pattern conversion unit 22
The bit pattern “10” of the sixth and seventh bits included in the bit pattern of FIG. 4B is inverted to be converted to the bit pattern of FIG. As a result, the run length of the fifth and sixth bits becomes 2 (lower limit), and FIG.
The forbidden run length estimated as an error is corrected from the bit pattern.

According to the above backward error correction, FIG.
The pulse width of the digital data in (a) is expanded backward. That is, if the digital data of FIG. 4C is subjected to NRZ modulation, digital data having the bit pattern “10000111000” shown in FIG. 4D is generated. The pulse width of the digital data in FIG.
When compared with that of FIG. 4A, it can be clearly seen that it is expanded in the backward direction. The error correction unit 64 performs an error correction process based on the same error correction code as described above on the error-corrected digital data of FIG. 4C.

By combining the above-described backward error correction and the above-described forward error correction, it becomes possible to correct the prohibited run length that could not be corrected by only the forward error correction. Therefore, the RLL error correction device 5 can correct more errors in the error correction unit 64 as compared with the case where only forward error correction is performed.

Next, the replacement error correction of the RLL error correction device 5 will be described with reference to FIGS. In addition,
The manner of referring to FIG. 5 is the same as that of FIG. NRZ
The NRZ-modulated digital data input to the −I conversion unit 61 has, for example, an error-containing bit pattern “010001” as shown in FIG.
The signal is converted into a signal including the bit pattern “011001” shown in FIG. 5B by the ZI modulation, and output to the prohibited run length / prohibited pattern detection unit 21.

Prohibition run length / prohibition pattern detection section 2
1 is the bit pattern of the input digital data,
It is detected whether or not a prohibition pattern composed of a bit pattern “11” (a bit pattern with a run length of 0) is included. Prohibited run length / prohibited pattern detector 2
When the bit pattern of FIG. 5B is input, 1 detects the forbidden pattern “11” in the third and fourth bits of the bit pattern.

When the prohibition pattern is detected, the run-length / pattern converter 22 detects the prohibition pattern “11”.
Is replaced with “00”. Therefore, the bit pattern in FIG. 5B is the same as the bit pattern “000” shown in FIG.
001 ”. As a result, the prohibition pattern “11” whose run length is 0 and which is estimated to be an error is corrected from the bit pattern of FIG. 5C.

According to the above replacement error correction, FIG.
Pulses presumed to be caused by noise are removed from the digital data of (a). That is, when NRZ modulation is performed on the digital data of FIG. 5C, digital data having the bit pattern “000001” shown in FIG. 5D is generated. The digital data in FIG.
Compared to that of FIG. 5A, it can be clearly seen that the pulse on the front side has been removed. Error correction unit 64
Performs an error correction process based on the same error correction code as described above on the error-corrected digital data of FIG. 5C.

As described above, according to the replacement error correction, NR
The prohibition pattern “1” is added to the ZI modulated digital data.
If "1" is detected, the prohibited pattern is determined to be an error caused by noise, and replaced with a bit pattern "00". If such replacement error correction is performed before the above-described forward error correction processing, the error correction ability by forward error correction in post-processing is improved. as a result,
The RLL error correction device 5 allows the error correction unit 64 to correct more errors as compared with the case of only forward error correction.

In the above embodiment, the case where the RLL code error correcting device 5 is used as the CD reproducing device has been described. However, the RLL code error correction device 5 may also be used for an optical disk device, a magneto-optical disk device, or a magnetic disk device. Further, it may be used at the time of error correction in decoding processing of digital data provided by communication or broadcasting.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a CD playback device including a run-length error correction device 5 according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a run-length error correction device 5 shown in FIG.

FIG. 3 is a diagram for explaining forward error correction of a run-length error correction device 5 shown in FIG. 2;

FIG. 4 is a diagram for explaining backward error correction of a run-length error correction device 5 shown in FIG. 2;

FIG. 5 is a diagram for explaining replacement error correction of the run-length error correction device 5 shown in FIG. 2;

FIG. 6 is a block diagram showing a configuration of a conventional RLL code error correction device.

FIG. 7 is a diagram for explaining a problem of the RLL code error correction device shown in FIG. 6;

[Explanation of symbols]

 5 RLL error correction device 61 NRZ-I conversion section 21 prohibited run length / prohibited pattern detection section 22 run length / pattern conversion section 64 error correction section

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04L 25/49 H04L 25/49 C (56) References JP-A-6-120844 (JP, A) JP-A-6-112846 ( JP, A) JP-A-6-112845 (JP, A) JP-A-5-225716 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G11B 20/00 H03M 7/00 H04L 25/00

Claims (3)

(57) [Claims] 1. An apparatus for correcting an error in digital data with reference to a run length, comprising: a first conversion unit that converts NRZ-modulated digital data into NRZ-I-modulated digital data; (1) detecting, from the digital data converted by the conversion unit, a forbidden run length smaller than a preset lower limit of run length by one and a first run length located in front of the forbidden run length and larger than the lower limit. And a second conversion unit that, when the forbidden run length and the first run length are detected, shortens the first run length by 1 and extends the forbidden run length to the lower limit. An error correction unit for performing error correction based on the error correction code of the digital data processed by the second conversion unit. Location. 2. The prohibition run length, a second run length located in front of the prohibition run length and equal to or less than the lower limit, and a detection unit located behind the prohibition run length and the lower limit. The second conversion unit further detects a third run length greater than the third run length, and when the forbidden run length, the second run length, and the third run length are detected, sets the third run length to one. 2. The run-length code error correction device according to claim 1, wherein said forbidden run-length is extended to said lower limit value by shortening. 3. The detection unit further detects a prohibition pattern of “11”, and the second conversion unit further converts the prohibition pattern into a pattern of “00” when the prohibition pattern is detected. The run-length code error correction device according to claim 1.