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JP3254053B2 - Optical integrated circuit - Google Patents

Optical integrated circuit

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Publication number
JP3254053B2
JP3254053B2 JP19735893A JP19735893A JP3254053B2 JP 3254053 B2 JP3254053 B2 JP 3254053B2 JP 19735893 A JP19735893 A JP 19735893A JP 19735893 A JP19735893 A JP 19735893A JP 3254053 B2 JP3254053 B2 JP 3254053B2
Authority
JP
Japan
Prior art keywords
electrode
optical
isolation
optical element
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19735893A
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Japanese (ja)
Other versions
JPH0758310A (en
Inventor
博久 佐野
立身 井戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
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Priority to JP19735893A priority Critical patent/JP3254053B2/en
Publication of JPH0758310A publication Critical patent/JPH0758310A/en
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Publication of JP3254053B2 publication Critical patent/JP3254053B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は光集積回路、更に詳しく
いえば、半導体基板上に形成された複数の光機能素子か
らなる集積化光素子、特に複数の電極を有する光集積回
路の電極構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical integrated circuit, and more particularly, to an integrated optical device comprising a plurality of optical functional elements formed on a semiconductor substrate, and more particularly to an electrode structure of an optical integrated circuit having a plurality of electrodes. It is about.

【0002】[0002]

【従来の技術】光機能素子を集積化する場合に最も問題
となるのは素子間の相互作用である。一般に相互作用と
しては、複数の光機能素子の相互間の光信号のクロスト
ークによるものと、電気信号のクロストークによるもの
がある。なかでも電気信号のクロストークを低減するこ
とは、素子間の光結合効率向上という相反する条件を同
時に満たさねばならないため、実現が難しい。例えば、
1989年電子情報通信学会秋季全国大会 C-179 古津、雙
田他「高抵抗層埋め込み構造光変調器/DFBレーザ集
積化光源」は、光変調器とレーザの集積化光源におい
て、素子間分離部にFe−InP等の半絶縁性半導体を
埋め込む手法により、電気的アイソレ−ションを確保し
ようとした例である。しかしこの手法を用いた場合にお
いても、残留するドーピング層を介した漏れ電流、即
ち、電気信号のクロストークを完全に除去することは困
難である。一般に集積化光源では、電気的相互作用を完
全に除くためには数メガオーム以上の分離抵抗が必要で
あると言われており、上記従来例においても充分な素子
間アイソレ−ションが得られているとは言えない。ま
た、半絶縁性半導体の導入に伴って製造工程が複雑化す
るため、作製コストが増大すると共に歩留まりが低下す
る。
2. Description of the Related Art Interaction between elements is most problematic when integrating optical functional elements. In general, the interaction is based on crosstalk between optical signals between a plurality of optical functional elements and crosstalk between electric signals. Above all, it is difficult to reduce the crosstalk of the electric signal because the conflicting condition of improving the optical coupling efficiency between the elements must be satisfied at the same time. For example,
1989 IEICE Autumn National Convention C-179 Furutsu, Sojita et al. "High-resistance embedded optical modulator / DFB laser integrated light source" In this example, an attempt is made to secure electrical isolation by a method of embedding a semi-insulating semiconductor such as Fe-InP. However, even with this method, it is difficult to completely remove the leakage current through the remaining doping layer, that is, the crosstalk of the electric signal. It is generally said that an integrated light source requires a separation resistance of several megaohms or more in order to completely eliminate electrical interaction, and sufficient isolation between elements is obtained in the above-mentioned conventional example. It can not be said. In addition, since the manufacturing process becomes complicated with the introduction of the semi-insulating semiconductor, the manufacturing cost increases and the yield decreases.

【0003】[0003]

【発明が解決しようとする課題】本発明の目的は、上記
従来例のもつ問題を解決することを目的としている。即
ち、素子作製工程を複雑化することなく、素子間の素子
間の光結合効率を低下させることなく、同時に素子間の
アイソレ−ションを確保した光集積回路を実現すること
である。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art. That is, it is an object of the present invention to realize an optical integrated circuit in which isolation between elements is secured without complicating the element manufacturing process and reducing the optical coupling efficiency between the elements.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明では、半導体基板上に形成された複数の機能
素子からなる集積化回路において、複数の機能素子の中
の少なくとも一組みの光機能素子の接続部に所定の分離
抵抗値を有する素子間分離構造と共に新たにアイソレ−
ション電極を設けた。上記アイソレーション電極は素子
内部で接地されるか、素子外部で所定の低インピーダン
ス回路(もしくはアース)に接続される。上記素子間分
離構造に要求される分離抵抗はアイソレーション電極部
のインピーダンスに比べて充分に大きく設定する。しか
し、その値は従来の分離抵抗のみでアイソレーションを
確保する場合に比べて1〜2桁小さいものでよい。本発
明の好ましい実施形態における一組みの光機能素子は、
以下の実施例で説明するレーザダイオード等の半導体光
源と光変調部であるが、それらに限定されない。
According to the present invention, there is provided an integrated circuit comprising a plurality of functional elements formed on a semiconductor substrate, wherein at least one set of optical elements among the plurality of functional elements is provided. A new isolator with a device-to-element isolation structure with a predetermined isolation resistance value
An electrode was provided. The isolation electrode is grounded inside the element or connected to a predetermined low impedance circuit (or ground) outside the element. The separation resistance required for the element isolation structure is set to be sufficiently large as compared with the impedance of the isolation electrode portion. However, the value may be smaller by one or two orders of magnitude than the case where the isolation is secured only by the conventional separation resistor. One set of optical functional elements in a preferred embodiment of the present invention is:
A semiconductor light source such as a laser diode and a light modulation unit described in the following embodiments, but are not limited thereto.

【0005】[0005]

【作用】本発明によるアイソレ−ション電極は、常に定
電位に保たれるため、各機能素子とアイソレ−ション電
極間での漏れ電流が生じても素子間での漏れ電流は発生
しない。このため素子間絶縁抵抗が比較的小さな場合に
おいても、素子間の電気的相互作用は生じない。本発明
で新たに設置するアイソレ−ション電極は、機能素子の
電極形成工程と同時に作製可能であるため、従来素子と
同様な作製プロセスを用いることが可能である。また、
本発明の分離抵抗部に要求される抵抗値は前述の様に従
来構造に比べて1〜2桁小さなものでよい。従ってその
構造も単純であり、従来の様に半絶縁性半導体による埋
め込み等を導入する必要が無い。このため、作製プロセ
スを大幅に簡単化することが可能となる。つまり、本発
明により簡便な工程による素子間の完全なアイソレ−シ
ョンが実現され、素子作製の歩留まりが大幅に向上する
と共に、素子性能の安定化が図れる。
Since the isolation electrode according to the present invention is always kept at a constant potential, even if a leakage current occurs between each functional element and the isolation electrode, no leakage current occurs between the elements. Therefore, even when the insulation resistance between elements is relatively small, no electrical interaction occurs between the elements. The isolation electrode newly installed in the present invention can be manufactured at the same time as the electrode forming step of the functional element, so that the same manufacturing process as that of the conventional element can be used. Also,
As described above, the resistance value required for the separation resistance portion of the present invention may be smaller by one to two digits as compared with the conventional structure. Therefore, the structure is also simple, and there is no need to introduce a burying or the like with a semi-insulating semiconductor as in the related art. Therefore, the manufacturing process can be greatly simplified. That is, according to the present invention, complete isolation between devices can be realized by simple steps, and the yield of device fabrication can be greatly improved, and device performance can be stabilized.

【0006】[0006]

【実施例】図1は、本発明による光集積回路の第一の実
施例の構造を示す。本実施例は、電界吸収型光変調器部
14と半導体レーザダイオード(LD)13をモノリシ
ック集積化した半導体光集積回路であり、(a)は上面
図、(b)は(a)のb−b’部の部分断面図である。
LD部13及び光変調器部14は同一のn型InP基板
1上に形成されている。両者の層構成は光導波路層
(0.2μm厚、吸収端波長1.15μm)2とp−クラ
ッド層4(2.0μm厚)、p−キャップ層(0.2μm
厚)5の間に形成されたアンドープの多重量子井戸層か
ら成っている。但し、LD部13は基板1にグレーティ
ング7が形成されている領域上に形成されていると共
に、アンドープ多重量子井戸層が動作波長(1.55μ
m)にほぼ等しい吸収端波長を有する活性層3となって
おり、この点で平坦基板部に形成された動作波長よりも
数十nm短波長側に吸収端波長をもつ多重量子井戸層を
用いている光変調器部14と構造が異なっている。
FIG. 1 shows the structure of a first embodiment of an optical integrated circuit according to the present invention. This embodiment is a semiconductor optical integrated circuit in which an electro-absorption type optical modulator section 14 and a semiconductor laser diode (LD) 13 are monolithically integrated, (a) is a top view, and (b) is b- in (a). It is a fragmentary sectional view of b 'part.
The LD section 13 and the optical modulator section 14 are formed on the same n-type InP substrate 1. The layer structure of both layers is an optical waveguide layer (0.2 μm thick, absorption edge wavelength 1.15 μm) 2, a p-cladding layer 4 (2.0 μm thick), and a p-cap layer (0.2 μm thick).
(Thickness) 5 formed of an undoped multiple quantum well layer. However, the LD section 13 is formed on the region where the grating 7 is formed on the substrate 1 and the undoped multiple quantum well layer has an operating wavelength (1.55 μm).
m), the active layer 3 having an absorption edge wavelength substantially equal to that of the multi-quantum well layer having an absorption edge wavelength several tens nm shorter than the operating wavelength formed on the flat substrate portion. The structure is different from that of the optical modulator section 14.

【0007】LD部13から放射された波長1.55μ
mの導波光9は、アイソレ−ション領域12を介して光
変調器部14に導かれ、ここで所定の電気信号に従って
変調を受ける。この際、光変調器部14に印加した電気
信号が共通導電層であるp−クラッド層4を介してLD
部13に漏れ込むことが電気的クロストークの主要因で
あり、これを抑圧するために本実施例ではアイソレーシ
ョン領域12に新たに電極6−1を配置すると共に、電
極6−3と6−1との間及び電極6−1と6−2との間
のpークラッド層4に分離溝8を形成している。ここ
で、分離溝8の深さは、導波光9のpークラッド層への
漏れ込みを考慮して、約1.2μmとした。この場合、
約1μmのpークラッド層4が溝下部に残留するため、
アイソレ−ション領域12での導波光9の散乱は充分に
小さく抑えられる。
The wavelength 1.55 μ radiated from the LD unit 13
The m guided light 9 is guided to the optical modulator section 14 via the isolation region 12, where it is modulated according to a predetermined electric signal. At this time, the electric signal applied to the optical modulator section 14 is transmitted through the p-clad layer 4 which is a common conductive layer to the LD.
Leakage into the portion 13 is a main cause of electrical crosstalk. To suppress this, in the present embodiment, a new electrode 6-1 is arranged in the isolation region 12 and electrodes 6-3 and 6- 1 and between the electrodes 6-1 and 6-2 are formed isolation grooves 8 in the p-cladding layer 4. Here, the depth of the separation groove 8 was set to about 1.2 μm in consideration of leakage of the guided light 9 into the p-cladding layer. in this case,
Since about 1 μm of the p-cladding layer 4 remains under the groove,
Scattering of the guided light 9 in the isolation region 12 is sufficiently suppressed.

【0008】個々の分離溝部8の抵抗は数十キロオーム
程度(10μmの分離溝を使用)であるが、アイソレー
ション電極6−1をこれよりも充分に小さなインピーダ
ンスを持つ定電圧回路(接地することも可能)に接続す
ることで、光変調器部14とLD部13との間の電気的
接続を断つことが可能となる。この場合、LD部13及
び光変調器部14に数十μA程度の漏れ電流は生じる
が、これらは共に定電圧回路と個々の素子間において流
れる電流成分であり、光変調器14に印加した電気信号
がLD部13に流れ込むことは無い。アイソレ−ション
電極6−1を使用しない通常の素子構成では、LD13
と光変調器14を集積化する場合に必要とされる電気的
アイソレーションを確保するために分離溝下部のpーク
ラッド層4を完全に除去する必要が生じるが、この場
合、導波光の散乱により光変調器部14とLD部13の
光結合効率が大幅に低下する。本実施例ではこの様な困
難を生じさせることなく、両者の電気的アイソレーショ
ンを実現することができる。また、アイソレ−ション電
極6−1はLD部13、光変調器部14の電極6−3、
6−2を形成する工程と同一時に作成できるため、素子
作成プロセスを変更する必要は無い。従って光集積回路
素子作成上の困難を生じさせる事無く、素子間アイソレ
ーションを大幅に改良する。
Although the resistance of each isolation groove 8 is about several tens of kilo-ohms (using a 10 μm isolation groove), the isolation electrode 6-1 is connected to a constant voltage circuit having a sufficiently smaller impedance (grounding). (Also possible), it is possible to cut off the electrical connection between the optical modulator unit 14 and the LD unit 13. In this case, a leakage current of about several tens of μA occurs in the LD unit 13 and the optical modulator unit 14, but these are current components flowing between the constant voltage circuit and the individual elements. No signal flows into the LD unit 13. In a normal element configuration not using the isolation electrode 6-1, the LD 13
It is necessary to completely remove the p-clad layer 4 below the separation groove in order to secure the electrical isolation required when the optical modulator 14 is integrated with the optical modulator 14. In this case, scattering of the guided light The optical coupling efficiency between the optical modulator section 14 and the LD section 13 is greatly reduced. In this embodiment, electrical isolation between the two can be realized without causing such difficulties. The isolation electrode 6-1 is connected to the LD unit 13, the electrode 6-3 of the optical modulator unit 14,
Since it can be created at the same time as the step of forming 6-2, there is no need to change the element creation process. Therefore, isolation between elements is greatly improved without causing difficulty in producing an optical integrated circuit element.

【0009】図2は、本発明によるの光集積回路の第二
の実施例の構造を示す。本実施例はアイソレーション構
造をマッハツェンダ型光変調器に適用したものである。
(a)は上面図、(b)は(a)のa−a’部の部分断
面図である。図に示した用にマッハツェンダ型光変調器
は、並列に配置された2個の位相変調器20と2個のY
分岐回路21を組み合わせた構造から成っており、これ
らの間での電気的アイソレーションを確保することが素
子特性の安定化を図る上で重要である。本実施例では、
半導体基板1の上の光導波路層2を介して作製されたア
ンドープ多重量子井戸構造3を光導波層とし、これを
p、n型半導体層で積層したPin構造を持つ素子につ
いての本発明の適用例を示しているが、本発明の適用例
は必ずしもPin構造に限定されるものでは無く、ショ
ットキー構造により電界を印加する構造もしくは電流注
入型の構造に対しても同様に適用することが可能であ
る。本実施例では、アイソレーション電極6−1は位相
変調領域の両端に配置されている。これは、位相変調領
域間の主たる漏れ電流が、Y分岐部21の光導波路上の
p導電層を介して流れるためであるが、この様な配置を
採ることによりY分岐部21への電界印加自体をも防ぐ
ことが可能となり、Y分岐部21での導波光の吸収損失
を低減することが可能となる。
FIG. 2 shows the structure of a second embodiment of the optical integrated circuit according to the present invention. In this embodiment, the isolation structure is applied to a Mach-Zehnder optical modulator.
(A) is a top view, and (b) is a partial cross-sectional view taken along line aa ′ of (a). As shown in the figure, the Mach-Zehnder optical modulator has two phase modulators 20 and two Y modulators arranged in parallel.
It has a structure in which the branch circuits 21 are combined, and ensuring electrical isolation between them is important for stabilizing element characteristics. In this embodiment,
Application of the present invention to a device having a Pin structure in which an undoped multiple quantum well structure 3 produced via an optical waveguide layer 2 on a semiconductor substrate 1 is used as an optical waveguide layer and this is laminated with p and n-type semiconductor layers. Although an example is shown, the application example of the present invention is not necessarily limited to the Pin structure, and can be similarly applied to a structure in which an electric field is applied by a Schottky structure or a current injection type structure. It is. In this embodiment, the isolation electrodes 6-1 are arranged at both ends of the phase modulation area. This is because a main leakage current between the phase modulation regions flows through the p conductive layer on the optical waveguide of the Y branch portion 21. By adopting such an arrangement, an electric field is applied to the Y branch portion 21. It is also possible to prevent itself, and it becomes possible to reduce the absorption loss of the guided light in the Y branch portion 21.

【0010】図3は、本発明によるの光集積回路の第三
の実施例の構造を示す。本実施例は図2の実施例のアイ
ソレーション電極6−1を、素子内においてnドープ基
板2とコンタクトさせることにより、強制的に接地22
した例を示している。同図において、図2同一部分には
同一番号を付す。このように素子内で電極6−1を接地
することにより、素子外部との接続点数を少なくするこ
とができ、素子の実装が簡単化される。この場合、コン
タクト面での接触抵抗値は分離溝部8での抵抗値よりも
十分に小さければ問題はないので、Pドープ層との接触
を前提として使用される通常の電極材料(例えばCr/
Au,Ti/Au等の電極材料)をアイソレーション電
極6−1に使用した場合においても、問題無く基板1と
の電気的接触を得ることができる。
FIG. 3 shows the structure of a third embodiment of the optical integrated circuit according to the present invention. In this embodiment, the isolation electrode 6-1 of the embodiment shown in FIG. 2 is forcibly grounded by making contact with the n-doped substrate 2 in the device.
An example is shown. 2, the same parts as those in FIG. 2 are given the same numbers. By grounding the electrode 6-1 in the element as described above, the number of connection points with the outside of the element can be reduced, and the mounting of the element is simplified. In this case, there is no problem as long as the contact resistance value at the contact surface is sufficiently smaller than the resistance value at the separation groove 8, so that a normal electrode material (for example, Cr /
Even when an electrode material such as Au or Ti / Au) is used for the isolation electrode 6-1, electrical contact with the substrate 1 can be obtained without any problem.

【0011】図4は、本発明による光集積回路の第四の
実施例を示した上面図である。本実施例の特徴は、アイ
ソレーション電極6−1を素子間分離部だけでなく、機
能素子の周囲全域に配置したことにある。これにより、
素子間の漏れ電流によるクロストークだけでなく、他の
電磁的相互作用によるクロストークの発生をも低減する
ことが可能となり、特にギガヘルツ以上の高周波領域に
おけるアイソレーション特性が向上する。なお、アイソ
レーション電極6−1以外の構成は図1に示した実施例
と同じであるので説明を省く。
FIG. 4 is a top view showing a fourth embodiment of the optical integrated circuit according to the present invention. The feature of the present embodiment lies in that the isolation electrode 6-1 is arranged not only in the inter-element isolation part but also in the entire area around the functional element. This allows
It is possible to reduce not only the crosstalk due to the leakage current between the elements but also the crosstalk due to other electromagnetic interaction, and the isolation characteristic is particularly improved in the high frequency region above gigahertz. The configuration other than the isolation electrode 6-1 is the same as that of the embodiment shown in FIG.

【0012】図5は、本発明による光集積回路の第五の
実施例を示す構成図である。図中集積化光素子は図1又
は図4に示した光集積回路と同様のもので、LD部1
3、アイソレーション部12、変調部14を持つ。LD
部13の電極6−1にはLD部駆動回路15が接続さ
れ、変調部14の電極6−2には変調部駆動回路16が
接続され、アイソレーション電極6−1はバイアスT回
路(DCバイアスと高周波信号の分波回路)17を通し
て、DCバイアス回路(制御回路)18がに接続されて
おり、分波された高周波成分は接地されている。アイソ
レーション領域12の活性層の吸収端波長を、動作光波
長に近く設定した場合、正バイアス印加によるアイソレ
ーション領域12への電流注入によって光増幅作用が生
じる。即ち、アイソレーション領域12は、機能素子間
の電気的相互作用を低減する作用と共に、光を増幅する
機能をも併せ持つことにになり、集積化回路内での光信
号の減衰を補償することができる。
FIG. 5 is a block diagram showing a fifth embodiment of the optical integrated circuit according to the present invention. The integrated optical device in the figure is the same as the optical integrated circuit shown in FIG. 1 or FIG.
3, an isolation unit 12 and a modulation unit 14. LD
The LD unit drive circuit 15 is connected to the electrode 6-1 of the unit 13, the modulation unit drive circuit 16 is connected to the electrode 6-2 of the modulation unit 14, and the isolation electrode 6-1 is connected to the bias T circuit (DC bias). A DC bias circuit (control circuit) 18 is connected to a DC bias circuit (control circuit) 18 through a multiplexing circuit 17 and a high-frequency signal demultiplexing circuit, and the demultiplexed high-frequency component is grounded. When the absorption edge wavelength of the active layer in the isolation region 12 is set close to the operating light wavelength, a current is injected into the isolation region 12 by applying a positive bias to cause an optical amplification effect. That is, the isolation region 12 has a function of amplifying light as well as a function of reducing electrical interaction between the functional elements, and can compensate for attenuation of an optical signal in an integrated circuit. it can.

【0013】また、アイソレ−ション領域12での活性
層の吸収端波長を動作光近傍もしくはそれよりも数十n
m程度短波長側に設定した場合には、同領域は光吸収領
域として働く。特に、吸収端波長を動作光よりも短波長
側に設定した場合には吸収係数を印加電圧によって調整
することも可能となる。これによりLD部13から発光
される導波光の一部をアイソレ−ション領域12におい
て光電流19として検出し、光出力をモニターすること
ができる。従来、LD出力モニターはLDの外部に光検
出器を配置して行っていたが、本実施例の方式を用いる
ことで光検出機能を素子内に集積化することが可能とな
り、光学系の簡単化及び安定化が図れる。なお、アイソ
レ−ション領域12に流れる光変調器14からの漏れ電
流は常に所定の周波数以上の信号成分を有する交流信号
と見做せるので、バイアスT回路17において完全に除
去可能であり、光検出信号に混入することは無い。
The absorption edge wavelength of the active layer in the isolation region 12 is set to a value close to the operating light or several tens of nm.
When the wavelength is set to the shorter wavelength side by about m, the region functions as a light absorption region. In particular, when the absorption edge wavelength is set to a shorter wavelength side than the operation light, the absorption coefficient can be adjusted by the applied voltage. As a result, a part of the guided light emitted from the LD section 13 can be detected as the photocurrent 19 in the isolation region 12 and the optical output can be monitored. Conventionally, an LD output monitor has a photodetector disposed outside the LD. However, by using the method of this embodiment, the photodetection function can be integrated in the device, and the optical system can be simplified. And stabilization. Since the leakage current from the optical modulator 14 flowing in the isolation region 12 can always be regarded as an AC signal having a signal component of a predetermined frequency or more, the leakage current can be completely removed in the bias T circuit 17 and the light detection can be performed. There is no mixing in the signal.

【0014】アイソレーション領域12での活性層の吸
収端波長を、動作光波長から数十〜百nm程度短波長側
に設定した場合、同領域は導波光の強度もしくは位相に
対する光変調器として動作する。この場合にも、その変
調度の調整はバイアス回路17によって調整することが
可能であり、光集積回路の高機能化に有効に働く。
When the absorption edge wavelength of the active layer in the isolation region 12 is set to a wavelength shorter than the operating light wavelength by several tens to hundreds of nm, the region operates as an optical modulator for the intensity or phase of the guided light. I do. Also in this case, the adjustment of the modulation degree can be adjusted by the bias circuit 17, which effectively works for enhancing the function of the optical integrated circuit.

【0015】[0015]

【発明の効果】本発明により、集積化光回路内での素子
間の電気的分離を簡便な構造により実現することが可能
となり、集積化に伴う素子間のクロストークの問題を解
決することが可能となる。
According to the present invention, electrical isolation between elements in an integrated optical circuit can be realized by a simple structure, and the problem of crosstalk between elements due to integration can be solved. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるの光集積回路の第一の実施例の構
成を示し、(a)は上面図、(b)は部分断面図を表わ
す。
FIGS. 1A and 1B show the configuration of a first embodiment of an optical integrated circuit according to the present invention, wherein FIG. 1A is a top view and FIG.

【図2】本発明によるの光集積回路の第二の実施例の構
成を示し、(a)は上面図、(b)は部分断面図を表わ
す。
FIGS. 2A and 2B show a configuration of an optical integrated circuit according to a second embodiment of the present invention, wherein FIG. 2A is a top view and FIG.

【図3】本発明によるの光集積回路の第三の実施例の構
成を示し、(a)は上面図、(b)は部分断面図を表わ
す。
3A and 3B show the configuration of a third embodiment of the optical integrated circuit according to the present invention, wherein FIG. 3A is a top view and FIG. 3B is a partial sectional view.

【図4】本発明によるの光集積回路の第四の実施例の構
成を示し、(a)は上面図、(b)は部分断面図を表わ
す。
FIGS. 4A and 4B show the configuration of a fourth embodiment of the optical integrated circuit according to the present invention, wherein FIG. 4A is a top view and FIG.

【図5】本発明の第五の実施例であり、本発明の光集積
化素子を用いた光送信機の構成を表す。
FIG. 5 is a fifth embodiment of the present invention, and shows a configuration of an optical transmitter using the optical integrated device of the present invention.

【符号の説明】[Explanation of symbols]

1:半導体基板、 2:光導波路層、 3:活性層、 3’:光吸収層、 4:クラッド層、 5:キャップ層、 6:p電極、 7:グレーティング、 8:分離溝、 9:導波光、 10:光導波路、 11:パッシベーション、 12:アイソレーション部、 13:LD部、 14:変調器部、 15:LD部駆動回路、 16:光変調器駆動回路、 17:バイアスT回路、 18:制御回路、 19:光電流、 20:位相変調器、 21:Y分岐回路。 1: semiconductor substrate, 2: optical waveguide layer, 3: active layer, 3 ′: light absorbing layer, 4: clad layer, 5: cap layer, 6: p electrode, 7: grating, 8: separation groove, 9: conductive Wave light, 10: optical waveguide, 11: passivation, 12: isolation section, 13: LD section, 14: modulator section, 15: LD section drive circuit, 16: optical modulator drive circuit, 17: bias T circuit, 18 : Control circuit, 19: photocurrent, 20: phase modulator, 21: Y branch circuit.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−55877(JP,A) 特開 平5−63179(JP,A) 特開 平1−192168(JP,A) 1992年電子情報通信学会秋季大会C− 146 p.4−168 (58)調査した分野(Int.Cl.7,DB名) H01S 5/00 - 5/50 H01L 27/15 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-55877 (JP, A) JP-A-5-63179 (JP, A) JP-A-1-192168 (JP, A) 1992 Electronic Information Communication Conference Autumn Meeting C-146 p. 4-168 (58) Fields surveyed (Int. Cl. 7 , DB name) H01S 5/00-5/50 H01L 27/15

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に第1の光素子及び第2の光
素子がモノリシック集積され、 第1の光素子及び第2の光素子は光導波路層、第1導電型
層を共有し、 前記第1の光素子の第1電極及び前記第2の光素子の第2
電極と同じ高さに、かつ、前記第1の光素子と前記第2
の光素子とのアイソレーション領域に第3の電極が設け
られ、前記第3の電極と前記第1の電極との間及び前記
第3の電極と前記第2の電極のと間に分離溝が、前記第1
導電型層に溝下部が残るように設けられ、 前記第3の電
極は、素子内部又は外部で接地されるか、又は素子外部
で所定の低インピーダンス回路に接続されたことを特徴
とする光集積回路。
A first optical element and a second optical element on a semiconductor substrate;
The elements are monolithically integrated, and the first optical element and the second optical element are an optical waveguide layer, a first conductivity type.
A first electrode of the first optical element and a second electrode of the second optical element
The first optical element and the second
The third electrode is provided in the isolation region with the optical element
Between the third electrode and the first electrode and the
A separation groove is provided between the third electrode and the second electrode.
Conductive layer is provided so that the grooves bottom remains, the third electrode, characterized in that it is connected either to ground inside the device or external, or outside of the element a predetermined low impedance circuit
Optical integrated circuit.
【請求項2】InP基板上に半導体レーザダイオード及
び電界吸収型光変調器がモノリシック集積され、 前記レーザ及び前記変調器は光導波路層、p-クラッド層
を共有し、 前記レーザ上の第1の電極及び前記変調器上第2の電極と
同じ高さに、かつ、前記レーザと前記変調器との接続部
であるアイソレーション領域に第3の電極が設けられ、 前記第3の電極と前記第1の電極との間及び前記第3の
電極と前記第2の電極との間に分離溝が、前記p-クラッ
ド層に溝下部が残るように設けられ、 前記第3の電極
は、素子内部又は外部で接地されるか、又は素子外部で
所定の低インピーダンス回路に接続されたことを特徴と
する光集積回路。
2. A semiconductor laser diode and an InP substrate.
And an electro-absorption type optical modulator are monolithically integrated, and the laser and the modulator are an optical waveguide layer, a p-cladding layer.
And a first electrode on the laser and a second electrode on the modulator.
At the same height and at the connection between the laser and the modulator
A third electrode is provided in the isolation region, which is located between the third electrode and the first electrode and the third electrode.
A separation groove is provided between the electrode and the second electrode.
The third electrode is provided so that the lower part of the groove is left in the gate layer.
Is grounded inside or outside the device, or
It is characterized by being connected to a predetermined low impedance circuit
Optical integrated circuit to be.
JP19735893A 1993-08-09 1993-08-09 Optical integrated circuit Expired - Lifetime JP3254053B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19735893A JP3254053B2 (en) 1993-08-09 1993-08-09 Optical integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19735893A JP3254053B2 (en) 1993-08-09 1993-08-09 Optical integrated circuit

Publications (2)

Publication Number Publication Date
JPH0758310A JPH0758310A (en) 1995-03-03
JP3254053B2 true JP3254053B2 (en) 2002-02-04

Family

ID=16373161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19735893A Expired - Lifetime JP3254053B2 (en) 1993-08-09 1993-08-09 Optical integrated circuit

Country Status (1)

Country Link
JP (1) JP3254053B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815960B2 (en) 2001-08-27 2004-11-09 Seiko Epson Corporation Electron beam test system and electron beam test method

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69721272T2 (en) * 1997-11-11 2004-02-05 Agilent Technologies Inc., A Delaware Corp., Palo Alto Electrical isolation of optoelectronic components
JP2002280662A (en) * 2001-03-15 2002-09-27 Opnext Japan Inc Semiconductor electric field absorbing modulator integrated laser module and light transmission device using the same
JP2012058432A (en) * 2010-09-08 2012-03-22 Opnext Japan Inc Semiconductor gain area-integrated mach-zehnder modulator
JP2012084627A (en) * 2010-10-08 2012-04-26 Anritsu Corp Semiconductor light-emitting element, and optical pulse tester using the same
JP6068210B2 (en) * 2013-03-14 2017-01-25 日本電信電話株式会社 Multi-channel laser array light source
JP6037952B2 (en) * 2013-06-20 2016-12-07 三菱電機株式会社 Semiconductor optical integrated device, optical transmission module, and optical transmission integrated module
CN107078460B (en) * 2014-09-08 2019-11-19 朗美通技术英国有限公司 Single chip integrated semiconductor laser with tunable

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1992年電子情報通信学会秋季大会C−146 p.4−168

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815960B2 (en) 2001-08-27 2004-11-09 Seiko Epson Corporation Electron beam test system and electron beam test method

Also Published As

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