JP3252606B2 - Digital chroma demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Digitally in the digital chroma signal processing of the chroma modulation and demodulation of the video signal
It relates to a luchroma demodulator .

[0002]

2. Description of the Related Art FIG. 5 shows a chroma signal phase control circuit used in a conventional chroma demodulator. Conventionally, this kind of the chroma signal phase control device, a two-phase quadrature modulation circuit 33 for quadrature two-phase modulation with a PLL circuit 31 and the clock generation circuit 32 in synchronization therewith by the clock synchronized with the burst signal as shown in FIG. 5 Provided, PLL circuit 31
Thus, the phase control device synchronizes the clock phase of the clock generation circuit 32 with the input burst signal and outputs the color difference signals (RY, BY) from the quadrature two-phase modulation circuit 33.

[0003]

However, the conventional phase control device is an all-analog chroma demodulation circuit that performs quadrature two-phase modulation at the burst frequency (fsc) locked by the PLL circuit 31. High-precision phase synchronization (at a frequency of 4 fsc and 2 fsc) with the burst signal (fsc) required by the chroma demodulator
There was a problem that a clock could not be obtained.

The present invention solves such a conventional problem and provides an excellent digital chroma demodulator capable of controlling the clock phase (4 fsc and 2 fsc) required for the digital chroma demodulator with high accuracy. It is intended to provide.

[0005]

The digital clock according to the present invention is provided.
The demodulator receives the input clock to achieve the above purpose .
A clock pulse having a different phase synchronized with the burst signal of the roma signal is generated, and the clock pulse having the different phase is generated during a blanking period.
Corresponding to the clock selection code from the clock pulses
A clock selection unit for selecting each clock pulses, the
Each clock pulse created by the clock selection unit is used.
There wherein the absolute value of the digitized the burst signal
Chroma absolute value circuit for calculating for each clock pulse, the absolute at twice the sampling frequency of the burst signal
An adding circuit for adding the data sampled values, before
Each addition of the addition circuit calculated for each clock pulse
From the result, the minimum value and code corresponding to the minimum value
The minimum value detecting section for detecting a de, co corresponding to the minimum value
A latch for holding over de as a clock selection code, blanking
During the video period excluding the ranking period, the
The clock selection unit based on the selected clock selection code.
The input is performed using the clock pulse selected in
A / D converter for converting the chroma signal into digital
It is a thing.

Also, in order to increase the accuracy of the addition result sampled from the burst signal, instead of the above-described addition circuit, an operation of adding N data at the sampling frequency to the data from the absolute value circuit and calculating an average value is performed. It may have a circuit.

Further, in order to increase the accuracy of the addition result sampled from the burst signal, instead of the above-described addition circuit, an arithmetic circuit for calculating the cumulative sum of N data at the sampling frequency by using the data from the absolute value circuit is provided. It may be provided.

[0008]

Therefore, according to the present invention, the data from the chroma absolute value circuit is added at 2 fsc, and a pulse having a different phase every 3 to 30 nS synchronized with the burst signal prepared in advance so that the result is minimized. 4fsc), it is possible to obtain a 4fsc clock which is phase-synchronized with the input chroma burst signal required in the digital chroma demodulator with high precision.

Further, the accuracy of phase detection can be increased by using an average value arithmetic circuit or a cumulative sum arithmetic circuit instead of the adder circuit.

[0010]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram of an entire digital chroma demodulator using the present invention. FIG. 3 is a detailed circuit diagram of the minimum value detection unit in the digital chroma signal phase control device. FIG. 4 is a detailed circuit diagram of the clock selection unit in the digital chroma signal phase control device.

In FIG. 1, a chroma absolute value circuit 4 receives a digitized digital chroma signal 1 as an input, and an output is connected to an adder circuit 5. The minimum value detection unit 7 receives the addition result 6 of the addition circuit 5 as an input, and two outputs are connected to the latch 9 and the selector 11, respectively.

The selector 11 selects one of the output of the minimum value detector 7 from the code 10 and the output of the latch 9 in accordance with the switching signal 12. The output of the clock selection code 13 is transmitted to the clock selector 14. Can be The clock selecting unit 14 selects pulses having different phases generated from the clock (4fsc) 3 according to the clock selection code 13, and the selected clock pulse 2 of the output is connected to the AD converter 16.

FIG. 2 shows a configuration when the present invention is used in a digital chroma demodulator. A chroma signal 15 is connected to a burst PLL circuit 22 and an AD converter 16 and is converted into a digital chroma signal. The signal 1 is input to the digital chroma signal phase control circuit 21 to selectively control the phase of the clock (4fsc) 3 from the clock pulse generation circuit 23, and the selected clock 2 is used as the AD converter 1
6 given.

[0014] In the above embodiment, at a selected by the switching Rikae signal 12 vertical or horizontal blanking period
The counter 26 or Rako over de 10 of the minimum value detecting section 7 is selected by the cell <br/> selector 11, the results corresponding to coat 10 Taha Ru phase P of the selected clock pulse (4 fsc) 2
Is output from the clock selection unit 14 to the AD converter 16. Chroma signal 1 5 AD by the selected clock 2
Is transducer 16 Dede Ijitaru reduction, is the digitized
And calculates the absolute value of the click Loma signal 1 from the chroma absolute value circuit 4 Device paste signal, the second burst signal frequency (fsc)
Frequency corresponding to double sampling frequency (2fsc)
The absolute value is added by the adding circuit 5 and the result is expressed by A
Held in latches 24 and the (P), the selector 11 to the next
Therefore, the selected clock pulse of another phase P + 1 selected
(4fsc) 2 is supplied to the AD converter 16 and similarly added, the result is held in the latch 25 as A (P + 1), the result of the latch 24 is compared with the result of the latch 25 by the comparator 28, and the smaller The data is held in the latch 24. Here is a circuit for holding the two data click <br/> lock selection code 13 latches 24 and 25 and the selector 27 to be used in the addition result and the clock selector 14. By repeating the above operation, the clock corresponding to the minimum
Find the lock selection code 13 and set its value in the latch 9
I do.

Next, in the vertical or horizontal video period,
Minimum value held in the latch 9 by the replacement signal 12
Is selected by the selector 11, and the phase
Lock pulse (4fsc) 2 is given to the AD converter 16
You.

[0016] Thus, according to the above embodiment, an effect that can be phase-locked to the burst signal of the input clock pulse (4 fsc) 2 for use in A D converter 16 with high precision.

FIG . 4 is a detailed circuit example of a clock selection unit in the digital chroma signal phase control device.
0 passes through the delay gate 29 through a different number of stages, connects to the input of the selector 30, and outputs pulses (4
fsc), the clock pulse 2 selected by the clock selection code 13 is selectively output.

In the above embodiment, the addition circuit 5 is used in FIG. 1, but an average value calculation circuit or a cumulative sum calculation circuit may be used instead of the addition circuit 5. In this case, the phase detection accuracy can be further increased.

[0019]

According to the present invention as is clear from the above examples, the burst signal (fsc) absolute value circuit and adder circuits for 2 data adds the data at twice the sampling frequency (2 fsc) of the burst signal and its provided the minimum value detecting unit and the selecting section for creating select different clock pulses selector and phase for selecting one of the minimum value holding to keep the latch and the minimum value detecting section outputs a for calculating the minimum value of the addition result Therefore, it is possible to select a clock pulse (4fsc) that minimizes the calculation result, and as a result, there is an effect that the phase can be accurately synchronized with the input chroma burst signal.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a digital chroma signal phase control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of the entire digital chroma demodulator using the present invention.

FIG. 3 is a detailed circuit diagram of a minimum value detection unit according to the first embodiment of the present invention.

FIG. 4 is a detailed circuit diagram of a clock selection unit according to the first embodiment of the present invention.

FIG. 5 is a schematic block diagram of a conventional chroma demodulator;

FIG. 6 shows a digital clock according to the first embodiment of the present invention.
Waveform diagram showing operation of phase control unit

FIG. 7 is a schematic block diagram of a conventional chroma demodulator;

[Explanation of symbols]

 Reference Signs List 1 digital chroma signal 2 selection clock pulse (4 fsc) 3 clock 4 fsc 4 chroma absolute value circuit 5 addition circuit 6 addition result 7 minimum value detection unit 8 minimum code 9 latch 10 code 11 selector 12 switching signal 13 clock selection code 14 clock Selector 15 Chroma signal 16 AD converter 17 Buffer 18 Color difference signal (RY) 19 Buffer 20 Color difference signal (BY) 21 Digital chroma signal phase control circuit 22 Burst PLL 23 Clock pulse generation circuit 24 Latch 25 Latch 26 Counter 27 selector 28 comparator 29 delay gate 30 selector 31 burst PLL 32 clock generation circuit 33 quadrature two-phase modulation

Claims (3)

(57) [Claims] 1. A burst signal of an input chroma signal
Create a different clock pulse of the synchronized phase, Blanc
From the clock pulses with different phases during the King period
A clock selection unit for selecting each clock pulse corresponding to the clock selection code, created by the clock selector
Chroma absolute value circuit for calculating the absolute value of the digitized said <br/> burst signal to each of said clock pulses by using the respective clock pulses, the absolute value at twice the sampling frequency of the burst signal Sampled data
An adder circuit for adding the data, calculate the each clock pulse
The minimum value and the maximum
A minimum value detector for detecting a code corresponding to the fine said minimum value, clock selection code a code corresponding to said minimum value
Latch to hold as and video except blanking period
During the period, the clock selection code held in the latch
The clock selected by the clock selection unit based on the clock
Digitally converts the input chroma signal using pulses
Digital chroma demodulator having AD converter for converting
Place. 2. A pre-SL addition circuit, characterized in that the data from the absolute value circuit is an arithmetic circuit for calculating an average value by adding the N data at the sampling frequency 請
A digital chroma demodulation circuit according to claim 1. 3. A pre-SL addition circuit, the digital chroma demodulation circuit, wherein the is an arithmetic circuit for calculating the cumulative sum of the N data in the sampling frequency data from the absolute value circuit.