JP3251053B2 - Data communication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system, and more particularly to a parallel processing in which two bus controllers are provided and one bus controller accesses a main memory while another bus controller accesses a local memory. The present invention relates to a data communication system in which data transfer is speeded up by transferring a little more than half of the amount of data to be transferred to a bus controller which is activated first and transferring the data.

[0002]

2. Description of the Related Art For example, in a high-speed LAN communication device, a large amount of data transfer is performed in the device, and the data transfer is performed in the following configuration.

FIG. 6 shows a configuration diagram of a conventional LAN control device. When data stored in a main memory 2 is transmitted, the data is temporarily stored in a local memory 7 of the LAN control device, and an interface (not shown) is used. Via the transmission line 9 to transfer data to the transfer destination.

[0004] From the main memory 2 to the local memory 7
In the data transfer to the main memory 2, the bus controller 6 issues a DMA interrupt, secures the system bus 3 and the local bus 8, accesses the main memory 2 to read data, and reads data from the main memory 2 in the next cycle. A series of data having a data length bc to be transmitted has been transferred by repeating the data transfer processing by DMA for writing data to the local memory 7 several times.

In FIG. 1, 1 is a main CPU, 4 is a control microprocessor, and 5 is a ROM. When the data sent from the transmission line 9 is received by the main memory 2, the data is transferred from the local memory 7 to the main memory 2 in the opposite direction, and the received data is stored.

[0006]

In the configuration of the conventional LAN controller shown in FIG. 6, while the bus controller 6 accesses the main memory 2, the local memory 7 idles and waits. Conversely, while the bus controller 6 accesses the local memory 7, the main memory 2
Since the side is idle and waiting, data transfer takes a long time, and there is a drawback that efficient data transfer is not performed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks by providing two bus controllers, wherein one bus controller accesses the main memory while the other controller accesses the local memory. The purpose of the present invention is to provide a data communication method that speeds up data transfer processing by allowing the bus controller that starts first to handle data transfer slightly more than half of the transfer data length. And

[0008]

To achieve the above object, a data communication system according to the present invention comprises a main memory connected to a system bus, a local memory connected to a local bus, a main memory and a system. A data communication system for transmitting and receiving data from the main memory to the transmission path and from the transmission path to the main memory via the local memory; The bus controller is composed of two bus controllers, and when one of the bus controllers accesses the main memory via the system bus, the other accesses the local memory via the local bus, and The bus controller that is started is the bus controller that is started later None slightly responsible many configuration data to be transferred compared to the side, is characterized in that so as to shorten the time required for the transfer processing of the data.

[0009]

Since there are two bus controllers, while one bus controller is reading data from the main memory, the other bus controller can write data to the local memory, and the bus controller activated earlier By slightly increasing the data transfer amount on the side, the end of the DMA data transfer ends almost simultaneously, and there is no difference between the end of the DMA transfer and the data transfer speed is improved.

[0010]

FIG. 1 is a block diagram of an embodiment of a data communication system according to the present invention, and FIG. 2 is an explanatory diagram of data transfer sharing according to the present invention.

In FIG. 1, reference numerals 1 to 5, 7 to 9 correspond to those in FIG. 6, 6-1 represents a # 1 bus controller, and 6-2 represents a # 2 bus controller. #
1 bus controller 6-1 and # 2 bus controller 6
2 is such that either one can occupy the system bus 3 and one of them can also occupy the local bus 8.

Therefore, when the # 1 bus controller 6-1 and the # 2 bus controller 6-2 occupy the system bus 3 and the local bus 8, the # 1 bus controller 6-1 accesses the main memory 2. The process of reading data and the process of the # 2 bus controller 6-2 accessing the local memory 7 and writing data can be executed in parallel.

As shown in FIG. 2, when data with a start address of X and a data length of bc stored in the main memory 2 is transmitted on the transmission line 9, it is activated first. For example, the # 1 bus controller 6-1 is responsible for data transfer of an amount of bc / 2 + α, which is more than half the data length bc / 2, and is started later.
-2 is set to take charge of data transfer of bc / 2-α. α is the # 1 bus controller 6-1 and #
This is the amount of data that the 2-bus controller 6-2 can read or write in one cycle.

# 1 bus controller 6-1 to be activated first
Performs read access to the main memory 2 at the start address X of the transferred data, and temporarily stores the read data in a buffer (not shown) of the # 1 bus controller 6-1. In the next cycle, the # 1 bus controller 6-1 writes the data once stored in the buffer to a predetermined address of the local memory 7.

The # 2 bus controller 6-2, which is activated later than the # 1 bus controller 6-1, performs a write process on the local memory 7 by the # 1 bus controller 6-1. The data stored at the start address Y (Y = X + bc / 2 + α) of the transfer data assigned to the # 2 bus controller 6-2 is read, and the read data is read by the # 2 bus controller 6-2. The data is temporarily stored in a buffer (not shown).

Then, in the next cycle, the # 1 bus controller 6-1 sends the next address X + 1 from the main memory 2.
The # 2 bus controller 6-2 reads the data stored in the # 2 bus controller 6-2.
The data once stored in the second buffer is written to a predetermined address of the local memory 7.

Hereinafter, similarly, the # 1 bus controller 6-1
In the # 2 bus controller 6-2, when one of the bus controllers is reading the transfer data from the main memory 2, the other bus controller writes the transfer data to the local memory 7 in parallel.

A feature of the present invention is that, as described above, the data transfer amount of the # 1 bus controller 6-1 activated first is not １ ／ of the transfer data length bc but bc / 2 + α, and This is a point slightly larger than the data transfer of the activated # 2 bus controller 6-2.

Now, the # 1 bus controllers 6-1 and # 2
When the bus controller 6-2 is set so as to take charge of data transfer equally as shown in FIG. 4, the # 2 bus controller 6-2 which is started later, as shown in FIG. , The previously activated # 1 bus controller 6-1
The DMA starts several steps later than the start, and the # 1 bus controller 6-1 activated earlier ends the DMA earlier. That is, a shift in the DMA end timing occurs.

Thus, the # 1 bus controllers 6-1 and # 1
The difference between the DMA end timing of the 2-bus controller 6-2 and the DMA end interrupt of the # 1 bus controller 6-1 and the DMA end interrupt of the # 2 bus controller 6-2 is caused twice. From the viewpoint of the main CPU 1, the data transfer interrupt by the bus controller is completed by the two DMA end interrupts.

On the other hand, in the present invention, the DMA termination of the # 1 bus controller 6-1 and the # 2 bus controller
The deviation from the end of the # 2 DMA is resolved, and the end of the DMA of the # 1 bus controller 6-1 can be regarded as the end of the DMA of the # 2 bus controller 6-2. Therefore # 1
With one DMA end interrupt on the bus controller 6-1 side, the data transfer processing by the two bus controllers # 1 bus controller 6-1 and # 2 bus controller 6-2 can be completed.

Accordingly, the actual number of steps in the DMA termination processing is reduced, and as a result, the data transfer speed is increased due to a reduction in the DMA termination processing time. The transfer data stored in the local memory 7 is loaded on the transmission line 9 via an interface (not shown) and transmitted to the transfer destination.

Next, the manner of processing at the end of data transfer by the bus controller will be described with reference to the flowchart of FIG. When a DMA end interrupt is issued from the # 1 bus controller 6-1 or the # 2 bus controller 6-2 (step 1), the main CPU 1 determines whether or not the # 1 bus controller 6-1 has completed its DMA processing. Confirm (step 2). When the DMA processing of the # 1 bus controller 6-1 has been completed, the main CPU 1
The interruption of the bus controller 6-1 is detected (step 3), and the flag indicating that the DMA has been completed is turned on (step 4).

In step 2, # 1 bus controller 6-1
Has not completed its DMA processing yet,
PU1 checks whether or not the # 2 bus controller 6-2 has completed its DMA processing (step 5). #
When the DMA processing of the 2-bus controller 6-2 has been completed, the main CPU 1 detects an interrupt on the # 2 bus controller 6-2 side (step 6) and turns on a flag indicating that the DMA has been completed (step 7). ).

In step 5, # 2 bus controller 6-2
Does not finish its DMA processing,
The main CPU 1 returns from the interrupt processing assuming that the A end interrupt has arrived, and waits for another interrupt (step 8).

On the other hand, when the # 1 bus controller 6-1 or the # 2 bus controller 6-2 normally issues a DMA interrupt to the main CPU 1, the # 1 bus controller 6-1 side indicates the DMA completion flag. Is turned on (step 9). When the flag indicating that the DMA has been completed on the # 1 bus controller 6-1 is on, the main CPU 1 checks whether the flag indicating that the DMA has been completed on the # 2 bus controller 6-2 is on (step 10). When the DMA completion flag on the side of the # 2 bus controller 6-2 is on, the main CPU 1 executes the two # 1 and # 2 bus controllers 6-2.
Assuming that the data transfer by 1, 6-2 has been completed (step 11), the process returns from the interrupt due to the data transfer (step 12), and returns to the original program before the interrupt.
Execute the contents of the program.

In step 9, # 1 bus controller 6-1
If the DMA end flag on the side of the # 2 bus controller 6-2 is not on, the process returns to step S5.

In this way, a single DMA end interrupt #
Since the end of each of the DMA processes of the # 1 and # 2 bus controllers 6-1 and 6-2 is confirmed, the actual steps of the DMA end process are reduced, and the DMA end process time is shortened.

In the above description, the data transfer from the main memory 2 to the local memory 7 has been described. However, data is stored from the transmission line 9 to the local memory 7, and the data stored in the local memory 7 is transferred to the main memory 2. Similar processing is performed for data transfer.

Therefore, both the transmission and reception operations are accelerated for the above-described reasons, and data communication with a high data transfer speed can be performed.

[0031]

As described above, according to the present invention, 2
Since two bus controllers are provided and the bus controller that is activated first is assigned a slightly larger amount of data to be transferred than the bus controller that is activated later, data transfer is performed. As compared with the case where the data is shared in half, the DMA termination processing time is reduced, and therefore, the data communication system in which the data transfer speeds up.

[Brief description of the drawings]

FIG. 1 shows a configuration of an embodiment of a data communication system according to the present invention.

FIG. 2 is an explanatory diagram of data transfer sharing according to the present invention.

FIG. 3 is a flowchart of an embodiment of the present invention at the end of data transfer.

FIG. 4 is an explanatory diagram of data transfer sharing when transfer data is shared equally.

FIG. 5 is an explanatory diagram of the end of a DMA process.

FIG. 6 is a configuration diagram of a conventional LAN control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main CPU 2 Main memory 3 System bus 6 Bus controller 6-1 # 1 bus controller 6-2 # 2 bus controller 7 Local memory 8 Local bus 9 Transmission line

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mayumi Kawahara 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-1-316855 (JP, A) JP-A-4-38554 (JP, A) JP-A-4-57141 (JP, A) JP-A-4-245357 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 13/08 H04L 12 / 40

Claims (1)

(57) [Claims] A main memory connected to a system bus; a local memory connected to a local bus; and a bus controller for controlling connection between the main memory and the system bus, and between the local memory and the local bus. In a data communication system for transmitting and receiving data from a main memory to a transmission path and from a transmission path to the main memory via the local memory, the bus controller is composed of two bus controllers, and one of the two bus controllers is a main bus controller. When accessing the memory, the other accesses the local memory, and the bus controller activated first receives more than half the amount of data to be transferred compared to the bus controller activated later. To reduce the time required for data transfer processing. A data communication method characterized by: