JP3246779B2 - Failure information collection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure information collecting method for reliably collecting failure information in a line control unit constituting a switching device in a function-distributed exchange.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing an embodiment of the present invention. Since it is a diagram useful for explaining the prior art, the prior art will be described first with reference to FIG. FIG.
1 shows a packet switching device as a function-distributed switch as a whole.

In FIG. 1, 1 is a maintenance operation control unit, 2 is a system bus of system 0, 3 is a system bus of system 1 (one of which is active and the other is spare), and 4 is a communication line. A spare switching circuit for switching 15-i to the spare line controller 40, 5-i (where i = 1, 2, 3
.. N) is a line control unit. Since there are a plurality of line control units having the same circuit configuration, one of them is represented by a symbol 5-i as a representative.

[0004] In addition, in the line control unit 5-i, 6-i
Is a local bus, 7-i is a processor, 8-i is a memory, 9-i is a system bus transfer control unit, 10-i is a system bus separation circuit for the 0 system bus 2, 1
1-i is a system bus separation circuit for the system bus 3 of the first system, and 12-i is a character assembly / disassembly circuit. 13-i is a failure information storage unit provided according to the present invention, and will be described later in detail.

[0005] The circuit operation will be briefly described. Communication line 15
From -i, bit serial data enters the character assembling / disassembling circuit 12-i, where it is assembled into a character, and is sequentially stored in the memory 8-i. Memory 8
Next, the data stored in -i is subjected to protocol processing by the processor 7-i. At this time, it is determined which line control unit should be exchanged and output by looking at the header, and the system bus transfer control unit 9-i Via the redundant one of the system buses 2 and 3, the character goes to another line control unit determined above, and from there to the communication line of the target route as data. By leaving, the packet switching process is performed.

[0006] The maintenance operation control unit 1 does not participate in the normal packet switching process, but functions when the operator performs maintenance of the system or diagnoses a failure of the system.

[0007]

In the conventional packet switching apparatus as described above, the failure management of each line control unit is performed by a maintenance operation control unit which performs maintenance management of the entire packet switching apparatus. In such a packet switching device, when a failure or the like in the line control unit occurs, the processor in the line control unit starts the failure management program, collects the failure information, and notifies the maintenance operation control unit.

[0008] However, depending on the type of the fault that occurs in the line control unit, the operation of the processor is completely stopped. However, when the fault occurs instantaneously and the processor tries to collect the fault information, it recovers. However, there is a problem that the operation of the processor becomes abnormal and collection becomes impossible, so that failure information cannot be collected sufficiently.

In addition, since the operation of stopping packet communication after a failure has been performed by a program operation, it takes several milliseconds to stop the operation, and depending on the failure, erroneous packet data may be transmitted to another line corresponding unit or There was also a risk of being sent to the communication line.

An object of the present invention is to solve the above-mentioned drawbacks and problems of the prior art, and to reliably collect failure information regardless of the fact that the processor stops operating or becomes abnormal. It is an object of the present invention to provide a failure information collecting method which can be performed sufficiently and has no danger of erroneous packet data being transmitted to another line corresponding unit or a communication line due to a failure.

[0011]

In order to achieve the above object, according to the present invention, hardware for collecting fault information is provided, instead of collecting fault information by software using a processor, thereby collecting fault information. I did it.

That is, in the present invention, a plurality of line control units each accommodating a communication line and transmitting and receiving packets,
In a distributed exchange comprising a system bus interconnecting the plurality of line controllers and a maintenance operation controller connected to the system bus,

In each of the line control units, when a failure occurs in any of the components constituting the line control unit, a failure occurrence detecting means for detecting the occurrence of the failure, and a failure occurrence is detected by the detecting means. At the time, disconnecting means for disconnecting the line control unit from the communication line and the system bus, and then, latch means for taking in and latching the presence / absence of failure occurrence output from each component configuring the line control unit, Was provided.

[0014]

When the maintenance operation control unit detects a line control unit in which a failure has occurred by some method, the maintenance operation control unit accesses the line control unit and obtains information on the presence / absence of the occurrence of the failure which is captured in the latch means. Read and reset the latch means.

As described above, according to the present invention, at the moment when a failure occurs in the line control unit, the cause of the failure and information necessary for failure analysis are held, and the failure information is read until the maintenance operation control unit reads out various failure information. The maintenance operation control unit analyzes the cause of the failure at the time of the failure because the line control unit that caused the failure is disconnected from the system bus and the communication line at the moment of the failure. The advantage is that the cause of the failure is reliably held, and the transfer of erroneous data due to the occurrence of the failure can be prevented.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention as described above, and is a main configuration diagram of a packet switching apparatus.

As shown in FIG. 1, a packet switching apparatus as one embodiment of the present invention includes a maintenance operation control unit 1, system buses 2 and 3 for system 0 and system 1, respectively, and a spare communication line. A spare switching circuit 4 for switching to a line control unit;

A plurality of line control units 5-i (where i =
1, 2, 3,... N) and the local bus 6 in the line control unit.
i, a processor 7-i in the line control unit, a memory 8-i in the line control unit, a system bus transfer control unit 9-i in the line control unit, and a system bus disconnection with respect to the 0-system bus 2 in the line control unit. A circuit 10-i, a system bus disconnection circuit 11-i for the system bus 3 of the first system in the line control unit,

Character assembling / disassembling circuit 12 in the line controller
-I, a failure information storage unit 13-i for monitoring the presence or absence of a failure in the line control unit and, if there is a failure, holding an internal state of the line control unit; a character assembling / disassembling circuit 12-i; And a communication line 15-i connected to the line control unit, and a spare line control unit 40.

The line control unit 5-i conforms to the X.264 standard recommended by CCITT (International Telegraph and Telephone Consultative Committee). 25, which accommodates a communication line 15-i according to a control procedure or the like.
The processor 7-i, the memory 8-i, etc. 25 Protocol processing according to a control procedure or the like is performed.

The protocol to be controlled is an example, and the same applies to the frame relay and the LAPD protocol recommended by CCITT and the like. The character assembling / disassembling circuit 12-i assembles the serial data from the communication line 15-i into characters (byte data) so that the processor 7-i in the line control unit 5-i can process the serial data, and stores this into the memory 8- Stored in i.

Conversely, according to an instruction from the processor 7-i, the data stored in the memory 8-i is converted into serial data for transmission to the communication line 15-i. The data subjected to the protocol processing by the processor 7-i or the like is sent to the system bus transfer control unit 9-i, and the data is transferred to the active system bus, that is, either the system bus 2 or 3 of the system 0 or system 1. Via the line control unit which accommodates the communication line heading for the communication partner.

Here, the system bus disconnecting circuit 10-
The gates of i and 11-i are closed only for the circuit going to the working system bus, so that connection with the working system bus can be made.

Here, in the line control unit 5-i, hardware (components constituting the line control unit, that is, a processor, a memory, a character assembling / disassembling circuit, a local bus, a system bus transfer control unit, etc.) and a line failure The operation when communication cannot be continued due to a bug in software built in the control unit will be described below.

A character assembling / disassembling circuit 12-i for assembling bit serial data from the communication line 15-i into a character (byte data) is connected to the local bus 6-i, a bus stack during direct memory access (DMA), and a processor 7-. Bus stack and internal operation error when i accesses local bus 6-i, parity error in memory 8-i, system bus transfer controller 9-i is performing direct memory access (DMA) to local bus 6-i In the case where a serious failure of the software built in the bus stack and the line control unit occurs in, for example, a case where it is impossible to get out of the loop state, the processor 7-i cannot continue the operation, and the communication processing is not performed. The operation stops.

In this case, the failure information storage unit 13-i always keeps the local bus 6-i on hold and the processor 7-i.
Operating state, parity error occurrence state of the memory 8-i,
The operation state of the system bus transfer control section 9-i, the operation state of the character assembling / disassembling circuit 12-i, and the like are monitored. If the communication processing cannot be continued as described above, the cause of the failure is determined at the moment when the failure occurs. The information necessary for the failure analysis, such as the sequence number inside each circuit, the contents of the address and data accessing the local bus, the type of the circuit accessing the local bus, etc., is stored in the failure information storage unit 13. -Store in i internal register.

When this state occurs, the failure information storage unit 13-i instructs the system bus disconnection circuit 10-i or 11-i to disconnect from the system bus at the same time when a failure occurs, and at the same time, performs communication. Similarly, it instructs the line disconnecting circuit 14-i to disconnect from the communication line. In this case, an abort pattern is transmitted to the communication line.

For the failure state of the line control unit 5-i,
It can be known that the maintenance operation control unit 1 performs a periodic health check, or that the maintenance operation control unit 1 receives an interrupt notification from the line control unit 5-i. In this case, the maintenance operation control unit 1
An instruction is given to the standby switching circuit 4 for switching the communication line 15-i to the standby line control unit 40 via a route (not shown), and communication is resumed.

The maintenance operation control unit 1 operates as a spare line control unit 40.
Communication is disabled until the communication line 15-i is switched. However, since the maintenance operation control unit 1 automatically performs these processes as described above, the communication disabled time should be extremely short, several hundred ms. Can be. During the period in which communication is disabled, an abort pattern is transmitted to the communication line 15-i. Since communication data is retransmitted after the communication is recovered by the procedure 25, the degree of influence on the subscriber can be extremely reduced.

The operation of the circuit in the case where a failure of the line control unit 5-i occurs and the maintenance operation control unit 1 reads out the failure information will be described below.

The line control unit 5-i in which the failure has occurred is in an out-of-service (OS) state disconnected from the system bus 2 or 3 and the communication line 15-i. The maintenance line controller 1 issues a command to the system bus disconnecting circuit 10-i or 11-i to issue a connection instruction between the system bus 2 or 3 in a standby state not used for communication service and the line controller 5-i. Instruct connection.

The maintenance operation control unit 1 includes a standby system bus and a system bus transfer control unit 9-i in the line control unit.
The failure information and the like stored in the failure information storage unit 13-i are read out via. When the maintenance operation control unit 1 reads out the contents of all registers (described later) in the failure information storage unit 13-i, the contents of the registers are automatically reset. Since the contents of the register are not cleared by a normal reset operation, failure information can be read out unless the power of the line control unit is turned off. If it is impossible to read out the register storing the failure information at all, it can be determined that the failure has occurred in the system transfer control unit 9-i.

FIG. 2 shows the fault information storage unit 13 shown in FIG.
It is a block diagram which shows the detail of -i. In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same components. In addition, 101 is a system bus error monitoring circuit, 102 is an OR circuit, 103 is a differentiating circuit, 104 is a disconnection signal latch unit composed of a flip-flop, and 105 is a failure information storage internal register group (comprising a large number of flip-flops). is there.

In FIG. 2, the character assembling / disassembling circuit 12
-I, a bus stack signal from i, a monitoring result information signal from the system bus error monitoring circuit 101, a processor 7-i
Instruction, bus stack signal, parity error signal from memory 8-i, system bus 6
A status signal indicating the presence or absence of a fault, such as a bus request signal, address and data from i, a sequence number from the system bus transfer control unit 9-i, is connected to the differentiating circuit 103 via the OR circuit 102, and It is connected to each register constituting the information storage internal register group 105.

Therefore, if a change occurs in any one of the status signals indicating the presence / absence of a fault (that is, when a fault occurs), a differential output is output from the differentiating circuit 103, which triggers, At this time, all the status signals indicating the presence or absence of the failure are taken into the registers constituting the failure information storage internal register group 105.

On the other hand, the differential output from the differentiating circuit 103 is
The communication line disconnection circuit 14-i and the system bus disconnection circuit 10 are latched by the disconnection signal latch unit 104.
-I or 11-i is instructed to disconnect. As a result, the line control unit in which the fault has occurred is immediately disconnected from the communication line or the system bus, and a status signal indicating whether or not a fault has occurred in each unit at that time is held in the register.

As described above, the maintenance operation control unit 1 can know the line control unit in which the fault has occurred by any method. As described above, the maintenance operation control unit 1 transmits the failure information storage unit 13-i via the standby system bus and the system bus transfer control unit 9-i in the line control unit.
All of the registers (failure information storage internal registers 10
Read out the contents of 5).

That is, the maintenance operation control unit 1 sends a failure information reading signal to the failure information storage internal register group 105 via the standby system bus and the system bus transfer control unit 9-i in the line control unit, and The contents of all the registers making up the register group 105 are read by a route not shown. Since the failure information reading signal is also supplied to the reset circuit 106, the reset circuit 10
By the operation of 6, all the contents of the failure information storage internal register group 105 are reset.

[0039]

As described above, according to the present invention,
Even in the event of a failure in the line control unit where communication processing cannot be continued, the cause information of the failure is retained at the moment when the failure occurs, making it possible to accurately grasp the failure information. At the moment when a failure occurs, the line control unit is disconnected from the system bus and the communication line, so that transmission of communication data that has been disturbed by a failure or the like can be prevented, and until the maintenance operation control unit reads the failure information. Since the failure information is not reset, the cause of the failure can be reliably analyzed by the maintenance operation control unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating details of a failure information storage unit 13-i in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Maintenance operation control part, 2 ... 0 system bus, 3 ... 1 system bus, 4 ... Standby switching circuit, 5-i ... i-th line control part, 6-i ... i-th line control part Bus, 7-i ... processor in i-th line control unit, 8
-I ... memory in the i-th line controller, 9-i ... system bus transfer controller in the i-th line controller, 10-i ...
a system bus disconnection circuit for the system bus 0 in the i-th line control unit; 11-i... a system bus disconnection circuit for the system bus 1 in the i-th line control unit; 12-i... a character in the i-th line control unit Assembling / disassembling circuit, 13-i... Failure information accumulating unit in i-th line control unit, 14-i... I-th communication line disconnecting circuit, 15
-I ... the communication line connected to the i-th line control unit, 40
... A spare line control unit.

Continuing from the front page (73) Patent holder 000005223 Fujitsu Limited 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Zenichi Yashiro 1-1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone (72) Inventor Satoshi Shinohara 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Atsushi Kawai 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Within the department (72) Inventor Shigeru Tanaka 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Kiminori Nagoshi 1015 Kamodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Co., Ltd. (56) References JP-A-1-2844043 (JP, A) JP-A-5-136850 (JP, A) JP-A-61-292445 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name ) H04L 12/56 H04L 29/14 H04M 3/00 H04Q 11/04

Claims (1)

(57) [Claims] 1. A plurality of line controllers each accommodating a communication line and transmitting / receiving packets, a system bus interconnecting the plurality of line controllers, and a system bus connected to the system bus. And a maintenance operation control unit. In each of the line control units, when any of the components constituting the line control unit has a fault, a fault occurrence detecting means for detecting the fault. Disconnection means for disconnecting the line control unit from the communication line and the system bus when the detection of the failure occurrence by the detection means, and thereafter, the failure occurrence output from each component configuring the line control unit. And latch means for taking in and latching the presence / absence information, and when the maintenance operation control unit detects a faulty line control unit, Access to fault information collection method which is characterized in that so as to reset the latch means with reading the presence information of the failure that is captured in the latch means.