JP3246547B2 - Semiconductor device having defect detection function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of detecting a stress or a defect generated due to an assembling process and a thermal stress after assembling.

[0002]

2. Description of the Related Art FIG. 4 shows a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 63-76340 as an example of a conventional semiconductor device having a defect detection function.

[0003] This semiconductor device has an integrated circuit chip 20.
A conductor layer 21 for defect detection formed of a diffusion layer wiring or polycrystalline silicon formed along the outer edge of the integrated circuit chip 20; and aluminum pads 22 and 23 for detection connected to the conductor wiring 21 for defect detection. , Consists of

If there is a defect 24 such as a crack or chip at a level to be removed on the outer peripheral portion of the integrated circuit chip 20, a defect detection conductor wiring 21 is also provided at the position where the defect 24 exists. The conductor wiring for defect detection 2
The open / short circuit 1 allows the defect 24 to be detected.

[0005]

However, the semiconductor device shown in FIG. 4 has a problem that it is impossible to detect a defect caused by a stress due to a thermal stress after a resin sealing step or an assembling step. Had.

The reason is as follows. In the semiconductor device shown in FIG. 4, the conductor wiring 21 for defect detection is made of a fragile hard material such as polycrystalline silicon or a diffusion layer. For this reason, if a crack occurs, the defect detection conductor wiring 21 is disconnected, so that the disconnection of the defect detection conductor wiring 21 can be detected as a defect. However, even if the defect-detecting conductor wiring 21 is displaced due to the stress, the defect-detecting conductor wiring 21 does not reach the disconnection, so that the deviation of the defect-detecting conductor wiring 21 cannot be detected as a defect. .

As described above, in the conventional semiconductor device, it is impossible to detect the presence of a defect caused by thermal stress.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of a conventional semiconductor device, and has been developed for an integrated circuit chip caused by thermal stress after a resin sealing step or an assembling step. It is an object of the present invention to provide a semiconductor device capable of detecting a stress to be removed.

[0009]

To achieve the above object, according to the present invention, there is provided a semiconductor device having a function of detecting a defect generated in a semiconductor chip, comprising: At least one defect-detecting conductor wiring formed on the uppermost layer of the multi-layer wiring structure and a layer immediately below the conductor wiring disposed at a minimum design interval that can be patterned from the defect-detecting conductor wiring ; A pad connected to the conductor wiring for detection; and a pad connected to the conductor wiring, wherein the conductor wiring is at least one of the left and right sides of the conductor wiring for defect detection in the uppermost layer of the multilayer wiring structure. And in a layer directly below the uppermost layer of the multilayer wiring structure, substantially below the conductor wiring for defect detection, and formed in a layer immediately below the uppermost layer of the multilayer wiring structure. The width of the conductor wire, to provide a semiconductor device is more than the sum of the width of the defect detection conductor lines of the conductor wiring formed on the uppermost layer of the multilayer wiring structure. A second aspect of the present invention is a semiconductor device having a function of detecting a defect that has occurred in a semiconductor chip, wherein the semiconductor device has at least one conductor line for defect detection formed on the uppermost layer of the multilayer wiring structure, In the upper layer and the layer immediately below,
A conductor wiring arranged at a minimum design interval that can be patterned from the defect detection conductor wiring, a pad connected to the defect detection conductor wiring, and a pad connected to the conductor wiring, the conductor wiring comprising: In the uppermost layer of the multilayer wiring structure, formed on at least one of the left and right sides of the defect detection conductor wiring, and in a layer immediately below the uppermost layer of the multilayer wiring structure, substantially below the defect detection conductor wiring. The width of the conductor wiring formed in the layer immediately below the uppermost layer of the multilayer wiring structure is arranged on both sides of the conductor wiring formed in the uppermost layer of the multilayer wiring structure and the conductor wiring for defect detection. A semiconductor device that is longer than the entire length of the semiconductor device.

[0010] The conductor wiring for defect detection and the conductor wiring are arranged with a minimum design space capable of patterning. Therefore, when the semiconductor device is deformed by the stress caused by the thermal stress after the resin sealing step or the assembling step, at the same time, the defect detection conductor wiring is distorted or Due to the displacement, the conductor wiring for defect detection comes into contact with the adjacent conductor wiring. The contact between the conductor wiring for defect detection and the conductor wiring can be easily detected via the pads formed to be connected to each other. As described above, according to the present semiconductor device, it is very easy to find out that a defect has occurred in the semiconductor device due to the stress caused by the thermal stress. As described in claim 3, the conductor wiring for defect detection and the conductor wiring are preferably arranged in parallel.

The conductor wiring for defect detection and the conductor wiring can be arranged at an arbitrary interval as long as they do not contact each other, and the interval in this case does not necessarily have to be constant. However, when the distance between the conductors is fixed, that is, when the conductor wiring for defect detection and the conductor wiring are arranged in parallel, the influence of the deformation of the semiconductor device on the conductor wiring for defect detection becomes constant. It is preferable because it can be used.

The conductor wiring is formed on at least one of the left and right sides of the defect-detecting conductor wiring in the uppermost layer of the multilayer wiring structure, and in the layer immediately below the uppermost layer of the multilayer wiring structure, the defect detection is performed. It is formed substantially below the conductor wiring for use.

The arrangement of the conductor wiring with respect to the conductor wiring for defect detection is arbitrary, but it is most preferable to arrange the conductor wiring on both the left and right sides and below the conductor wiring for defect detection. With this arrangement, the conductor wiring for defect detection surrounds the conductor wiring from three sides, so that even if the conductor wiring for defect detection is deformed in any direction, it will come into contact with any conductor wiring, The accuracy of stress detection can be improved.

It is not always necessary to dispose the conductor wiring on both the left and right sides of the defect detection conductor wiring, and the conductor wiring may be disposed only on one of the left and right sides.

The width of the conductor wiring formed on the layer immediately below the uppermost layer of the multilayer wiring structure is the sum of the width of the conductor wiring formed on the uppermost layer of the multilayer wiring structure and the width of the conductor wiring for defect detection. This is set as above. Alternatively, the width of the conductor wiring formed in the layer immediately below the uppermost layer of the multilayer wiring structure is arranged on both sides of the conductor wiring formed in the uppermost layer of the multilayer wiring structure and the conductor wiring for defect detection. It is set to be longer than the total length between things.

[0016]

As described above, by setting the width of the conductor wiring formed in the layer immediately below the uppermost layer of the multilayer wiring structure, when the defect-detecting conductor wiring is deformed downward, the structure of the multilayer wiring structure is reduced. The conductor wiring formed in the layer immediately below the uppermost layer and the conductor wiring for defect detection can be reliably brought into contact with each other, and the occurrence of stress can be detected.

According to a fourth aspect of the present invention, the conductor wiring formed on the uppermost layer of the multilayer wiring structure and the conductor wiring formed on the layer immediately below the uppermost layer of the multilayer wiring structure have through holes. It is preferable that the electric current is conducted through the electric field.

As described in claim 5, for example, the conductor wiring for defect detection and the conductor wiring can be formed along the outer edge of the semiconductor device.

By arranging the conductor wiring for defect detection and the conductor wiring in this manner, it is possible to detect the occurrence of stress near the outer edge of the semiconductor device.

Also, as described in claim 6,
The defect-detecting conductor wiring and the conductor wiring may be formed to have a shape extending from the center of the semiconductor device toward the outer edge of the semiconductor device.

For example, as described in claim 7, the conductor wiring for defect detection and the conductor wiring can be formed to extend in four directions from the center of the semiconductor device toward the outer edge of the semiconductor device.

By arranging the conductor wiring for defect detection and the conductor wiring as in claim 6 or 7, it is possible to detect the occurrence of stress at the center of the semiconductor device.

[0024]

As described in claim 8, the conductor wiring for defect detection and the conductor wiring are preferably made of metal. In particular, as described in claim 9, an alloy, copper, aluminum or gold is preferable.

[0026]

1 and 2 are a sectional view and a plan view, respectively, of a first embodiment of a semiconductor device according to the present invention.

As shown in FIG. 1, a semiconductor chip 1 according to the present embodiment includes a silicon substrate 2 and a plurality of silicon oxide films 3 as interlayer insulating films formed on the silicon substrate 2.
a, 3b, 3c, 3d, a polyimide film 4 as a passivation film formed on the surface of the uppermost silicon oxide film 3, and a sealing resin 5 covering the surface of the semiconductor device 1.
And

As shown in FIG. 2, the region inside the semiconductor chip 1 forms an IC region 6, and a semiconductor device region 8 is formed between the IC region 6 and a cut surface 7 of the semiconductor chip 1.
(See FIG. 1).

As shown in FIG. 1, in the semiconductor device region 8, the uppermost silicon oxide film 3a has a stress detection aluminum wiring 9 as a defect detection conductor wiring and a first aluminum wiring as a conductor wiring. 10 and a second aluminum wiring 11 as a conductor wiring are formed. Further, the silicon oxide film 3b immediately below the uppermost silicon oxide film 3a includes:
A third aluminum wiring 12 is formed as a conductive wiring. The aluminum wiring for stress detection 9, the first aluminum wiring 10, the second aluminum wiring 11, and the third aluminum wiring 12 are arranged in parallel with each other.

The aluminum wiring 9 for stress detection and the first aluminum wiring 10 and the second aluminum wiring 11 on both the left and right sides thereof are arranged with an interval of the minimum design dimension that can be patterned. The third aluminum wiring 12 has a width L larger than the distance S between the outer circumference of the first aluminum wiring 10 and the outer circumference of the second aluminum wiring 11 (L> S).

Although the width L of the third aluminum wiring 12 is set to be larger than the distance S in the present embodiment, it may be set to be equal (L = S).

As shown in FIG. 2, the aluminum wiring 9 for stress detection and the first to third aluminum wirings 10, 11, 12 are arranged in a rectangular shape along the outer edge of the semiconductor chip 1, and The wiring 9 is bent at one end toward the inside of the semiconductor chip 1 and is connected to the stress detection pad 13. Similarly, the third aluminum wiring 10 is bent near the bending point of the aluminum wiring 9 for stress detection, and is connected to the pad 14 for stress detection. The two stress detection pads 13 and 14 are arranged close to each other as shown in FIG.

Although not clearly shown in FIGS. 1 and 2, the first aluminum wiring 10, the second aluminum wiring 11, and the third aluminum wiring 12 are mutually connected through a through hole 15 (see FIG. 2). It is connected. Therefore, the first aluminum wiring 1
0, the second aluminum wiring 11 and the third aluminum wiring 12 are also connected to the stress detection pad 14 via the stress detection aluminum wiring 9.

The operation and function of the semiconductor device according to the present embodiment having the above configuration will be described below.

Considering the state after resin sealing, the sealing resin 5
And the polyimide film 4 have different coefficients of thermal expansion due to the difference in material. Similarly, the polyimide film 4 and the silicon oxide film 3a have different coefficients of thermal expansion due to the difference in material. For this reason, when thermal stress is applied, thermal stress is generated at the interface between them.

If the thermal stress is large, cracks occur in the polyimide film 4 and the silicon oxide film 3a, and as a result, the stress detecting aluminum wiring 9 moves to the left or right or downward, and the first to third aluminum Short-circuit with any of the wirings 10, 11, and 12. As described above, when the stress detection aluminum wiring 9 is short-circuited to any one of the first to third aluminum wirings 10, 11, and 12, the electrical characteristics of the two stress detection pads 13 and 14 change. By monitoring the electrical characteristics of the pads 13 and 14 at all times, the aluminum wiring 9 for stress detection and the first to third aluminum wirings 10, 11, 1
2 can be detected.

Further, it is possible to determine whether or not the magnitude of the generated thermal stress is at a level that is inconvenient for the semiconductor chip 1 according to the degree of change in the electrical characteristics of the stress detection pads 13 and 14. it can.

As described above, according to the present embodiment, it is possible to easily detect the stress to be removed from the semiconductor chip, which is caused by the thermal stress after the resin sealing step or the assembling step.

Further, since the stress is detected using only the uppermost layer of the interlayer insulating film and the second layer from the top, there is no restriction on the layout of the normal element operation region.

As shown in FIG. 1, the aluminum wiring 9 for stress detection is insulated from the first to third aluminum wirings 10, 11, and 12, so that the semiconductor chip 1 according to this embodiment is Wiring 9 and first to third aluminum wiring 10,
It can be considered that capacitors 11 and 12 are used as electrode plates. After the resin sealing step and after the assembling step, as described above, the stress at the interface of each layer fluctuates due to the thermal stress, and the amount of movement of the stress detection aluminum wiring 9 fluctuates according to the magnitude of the stress. The capacity of this capacitor varies depending on the magnitude of the stress. Therefore, by detecting the change in the capacitance of the capacitor, the change in the stress can be known.

In particular, when the capacitance becomes 0, the stress detecting aluminum wiring 9 and the first to third aluminum wiring 1
Since 0, 11, and 12 are short-circuited, it can be determined whether or not the magnitude of the stress becomes a problem for the semiconductor chip 1.

FIG. 3 shows a second embodiment of the semiconductor device according to the present invention.

In this embodiment, the aluminum wiring 9 for stress detection and the first to third aluminum wirings 10, 11, 12 are formed so as to extend in a cross shape from the center of the semiconductor chip 1 to the outer edge in all directions. Have been.

By forming the aluminum wiring 9 for stress detection and the first to third aluminum wirings 10, 11, and 12 in this manner, it is possible to detect the stress generated at the center of the semiconductor chip 1 during resin sealing. it can. The method for detecting the stress is the same as that in the first embodiment.

In the present embodiment, the aluminum wiring 9 for stress detection and the first to third aluminum wirings 10, 11, and 1 are used.
Although 2 was formed in a cross shape, the shape is not limited thereto. Regardless of the shape, if the stress detection aluminum wiring 9 and the first to third aluminum wirings 10, 11, and 12 are formed so as to pass through the central portion of the semiconductor chip 1, a resin sealing occurs. It is possible to detect the stress at the center of the semiconductor chip 1.

Further, in the first and second embodiments, the conductor wiring for defect detection and the conductor wiring are all formed of aluminum, but the material of the conductor wiring for defect detection and the conductor wiring is not limited to aluminum. . Other metals than aluminum can be used. In that case, copper or gold is particularly preferable. Alternatively, it is also possible to use alloys of various metals.

[0047]

According to the semiconductor device of the present invention, it is possible to easily determine whether or not the magnitude of the stress due to the thermal stress after the resin sealing step or the assembling step becomes a defect for the semiconductor chip. it can.

The reason is that the conductor wiring for defect detection of the present semiconductor device is in the vicinity of the uppermost layer of the semiconductor device, so that it is easily affected by the stress due to the thermal stress after the resin sealing step or the assembling step. .

Also, since the conductor wiring for defect detection and the conductor wiring are connected to the respective pads, it is possible to easily detect the electrical characteristics of the conductor wiring for defect detection and the conductor wiring via these pads. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device shown in FIG.

FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a plan view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Silicon substrate 3a, 3b, 3c, 3d Silicon oxide film 4 Polyimide film 5 Resin 6 IC area 7 Cut-out surface 8 Semiconductor device area 9 Aluminum wiring for stress detection 10 First aluminum wiring 11 Second aluminum wiring 12 Third Aluminum wiring 13 Pad for stress detection 14 Pad for stress detection 15 Through hole 20 Integrated circuit chip 21 Conductor wiring for defect detection 22, 23 Detection aluminum pad 24 Defect

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-7-235578 (JP, A) JP-A-61-67942 (JP, A) JP-A-11-211586 (JP, A) JP-A-10-107 90349 (JP, A) Japanese Utility Model 3-1439 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/66 H01L 21/822 H01L 27/04

Claims (9)

(57) [Claims] 1. A semiconductor device having a function of detecting a defect generated in a semiconductor chip, comprising: at least one conductor wire for defect detection formed on an uppermost layer of a multilayer wiring structure; and an uppermost layer of the multilayer wiring structure. And the layer immediately below it,
A conductor wiring arranged at a minimum design interval that can be patterned from the conductor wiring for defect detection, a pad connected to the conductor wiring for defect detection, and a pad connected to the conductor wiring. The conductor wiring is in the uppermost layer of the multilayer wiring structure,
It is formed on at least one of the left and right sides of the defect detection conductor wiring, and in a layer immediately below the uppermost layer of the multilayer wiring structure, is formed substantially below the defect detection conductor wiring, The width of the conductor wiring formed in the layer immediately below the uppermost layer of the multilayer wiring structure is a sum of the width of the conductor wiring formed in the uppermost layer of the multilayer wiring structure and the width of the conductor wiring for defect detection. The above is a semiconductor device. 2. A semiconductor device having a function of detecting a defect generated in a semiconductor chip, comprising: at least one conductor wire for defect detection formed on an uppermost layer of a multilayer wiring structure; and an uppermost layer of the multilayer wiring structure. And the layer immediately below it,
A conductor wiring arranged at a minimum design interval that can be patterned from the conductor wiring for defect detection, a pad connected to the conductor wiring for defect detection, and a pad connected to the conductor wiring. The conductor wiring is in the uppermost layer of the multilayer wiring structure,
It is formed on at least one of the left and right sides of the defect detection conductor wiring, and in a layer immediately below the uppermost layer of the multilayer wiring structure, is formed substantially below the defect detection conductor wiring, The width of the conductor wiring formed in the layer immediately below the uppermost layer of the multilayer wiring structure is arranged on both sides of the conductor wiring formed in the uppermost layer of the multilayer wiring structure and the conductor wiring for defect detection. Semiconductor devices that are longer than the total length between 3. The semiconductor device according to claim 1, wherein the conductor wiring for defect detection and the conductor wiring are arranged in parallel. 4. The conductor wiring formed on the uppermost layer of the multilayer wiring structure and the conductor wiring formed on the layer immediately below the uppermost layer of the multilayer wiring structure are electrically connected via a through hole. The semiconductor device according to claim 1, wherein: 5. The semiconductor device according to claim 1, wherein the conductor wiring for defect detection and the conductor wiring are formed along an outer edge of the semiconductor device. 6. The semiconductor wiring according to claim 1, wherein the conductor wiring for defect detection and the conductor wiring are formed to extend from a center of the semiconductor device toward an outer edge of the semiconductor device. The semiconductor device according to claim 1. 7. The semiconductor device according to claim 6, wherein the defect detection conductor wiring and the conductor wiring extend in four directions from a center of the semiconductor device toward an outer edge of the semiconductor device. 8. The semiconductor device according to claim 1, wherein the conductor wiring for defect detection and the conductor wiring are made of metal. 9. The semiconductor device according to claim 8, wherein the conductor wiring for defect detection and the conductor wiring are made of an alloy, copper, aluminum, or gold.