JP3245903B2 - Semiconductor peripheral devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor peripheral device, and more particularly to a semiconductor peripheral device used in a microcomputer system.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, a semiconductor peripheral device 11b of this type includes a microprocessor 13 constituting a microcomputer system and an external data processor.
In order to exchange 8-bit data via the bus 8 and the internal input / output buffer 4, a register file 1 having registers A to N for storing the data, an IORD and IOWR signals from the microprocessor 13, and a decoder 12 And an AND gate 9 that inputs control signals S9a and S9b, which are logically output, to the control terminal of the input / output buffer 4 to control the operation state.

When designing a microcomputer system using the semiconductor peripheral device 11b, it is common to take into account data of electrical characteristics guaranteed by the manufacturer. One of the electrical characteristics is an access time from when the chip select signal CS is activated to when data is read or written correctly.

[0004] Since semiconductor manufacturers vary actual access times due to variations in manufacturing conditions, fluctuations in power supply voltage, ambient temperature, and the like, fixed conditions are set to determine access times. For example, access time is 150 ns
In the case of a product of the standard, the ability includes an access time of 120 ns. However, a system design combining the microprocessor 13 and the semiconductor peripheral device 11b includes:
The design value of 150 ns guaranteed by the manufacturer is used.

[0005]

When a microcomputer system is designed using this conventional semiconductor peripheral device, a guaranteed access time value of a device product is used. For example, there are two types of peripheral devices having different accelerator times, one of which guarantees an access time of 80 ns, the other of which guarantees an access time of 100 ns, and a 90 ns wait from a bus cycle of the CPU at the interface with the CPU. , It is assumed that an access time of 190 ns is required for one clock of wait.

In this case, the hardware designer has to
Either a design using a peripheral device of s with a wait of 0 or a design using a peripheral device of 100 ns with a wait of 1 clock is selected. In the former case, the cost is high, and in the latter case, the performance of the system is degraded, and both are not optimal system designs. Here, assuming that the capability of the peripheral device whose access time of 100 ns is guaranteed is 90 ns or less, a reasonable system design is to design with a weight of 0 using the peripheral device of 90 ns.

[0007]

According to the present invention, a semiconductor peripheral device stores data in a register selected by an address selector via an input / output buffer whose data write and read functions are controlled by an external control signal. It has a register file, a semiconductor peripheral device to exchange the data with the microprocessor via an external data bus, the control signal inputted to the control signal
Monitor the internal signal based on the signal and change to a predetermined state
And a data valid timing generation circuit for outputting a data valid timing signal from an external monitor signal terminal as soon as the data is detected .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention.
The semiconductor peripheral device 11 of the present embodiment includes an additional bit 3 added corresponding to each of the registers A to N of the register file 1 and an input / output buffer 5 for the additional bit for input / output.
And an output bit signal S5 and a three-input AND signal S9a, which is one of the control signals, input a two-input AND signal S10a to the gate of the transistor and output a data valid timing signal SVD to the monitor terminal VD. A data valid timing generation circuit 10 having an input AND gate 10a is added to the conventional semiconductor peripheral device 11b of FIG.

Next, referring to FIG.
The operation of writing data to and reading data from will be described. First, the write operation will be described. When the address information SA is input to the selector 2 from the address bus 7 and the chip select signal CS becomes “L” level, a predetermined register I in the register file 1 is selected.
Then, the write data SW is written to the register I from the data bus 8 through the input / output buffer 4.

Further, when the above-mentioned register I is selected, the corresponding additional bit 3 is also selected, and data "1" is written there through the additional bit input / output buffer 5. Further, the line L connecting the additional bit 3 and the additional bit input / output buffer 5 is "1" after being charged.
It is discharged to "0".

Next, the read operation will be described. The register selecting operation in the register file 1 is performed in the same manner as the writing of the data SW, and is output to the data bus 8 through the input / output buffer 4. When the above-mentioned register I is selected, the corresponding additional bit 3 of the data valid timing generation circuit 10 is also selected, and the additional bit signal S5 corresponding to the register I is changed from “0” through the additional bit input / output buffer 5. Changes to "1".

When the bit signal S5 changes to "1", the transistor 6 is turned on by the two-input AND signal S10a of the two-input AND gate 10a, and the monitor terminal VD is set to "L".
The level of the monitor terminal VD, which is driven to the level, can be monitored by the external determination unit 14 to detect that the read data SR on the data bus 8 has become valid. The transistor 6 is an open-drain buffer, and connects the VD line of the similar semiconductor peripheral device 11 to a wired
It's possible to make an Owa.

FIG. 3 is a block diagram of a second embodiment of the present invention. In the semiconductor peripheral device of the present embodiment, the control signal S9a output from the three-input AND 9a of CS, IORD, IOWR of the AND gate 9 is passed through a delay circuit 10a which is a data valid timing generation circuit 10A as shown in FIG.
As shown in (5), the transistor 6 is driven by sending only a predetermined delay time td, and the data bus 8 is monitored from the monitor terminal VD by the determination unit 14.

[0014]

As described above, according to the present invention, when data is read from a semiconductor peripheral device, a signal indicating that the data is valid is output, so that hardware design ignoring access time can be performed. Become. Therefore, an optimal system can be constructed in terms of cost and performance, and there is an effect of eliminating waste.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of reading data shown for explaining the operation of the block in FIG. 1;

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a timing chart of reading data shown for explaining the operation of the block in FIG. 2;

FIG. 5 is a block diagram of an example of a semiconductor peripheral device used in a conventional microcomputer system.

[Explanation of symbols]

 Reference Signs List 1 register file 2 selector 3 additional bit 4 input / output buffer 5 additional bit input / output buffer 6 transistor 7 address bus 8 data bus 9 AND gate 9a 3 input AND gate 10, 10A data valid timing generation circuit 10a 2 input AND gate 11, 11a Semiconductor peripheral device 14 Judgment unit S5 Additional bit output signal S9a 3-input AND signal S9b, 10a 2-input signal SA address information SR read data SW write data

Claims (3)

(57) [Claims] An input / output buffer whose data write and read functions are controlled by an external control signal has a register file to be stored in a register selected by an address selector. in the semiconductor peripheral devices, inputs the control signal the for exchanging the data with the microprocessor via
Monitor the internal signal based on the control signal at all times to achieve a predetermined state
And a data valid timing generation circuit for outputting a data valid timing signal from an external monitor signal terminal as soon as a change in the data is detected . 2. The register file comprising :
These registers have additional bits and the data valid
The timing generation circuit controls the control signal and the selected register.
The AND signal with the signal indicating the additional bit data of
As soon as a change to the specified state is detected,
2. The semiconductor peripheral device according to claim 1, wherein the semiconductor peripheral device outputs a lid timing signal . 3. The data valid timing generation circuit includes a delay circuit for delaying a control signal by a predetermined time.
The output signal of the delay circuit is constantly monitored to change to a predetermined state.
Data validation timing signal as soon as
2. The semiconductor peripheral device according to claim 1, wherein the output is performed .