JP3245124B2 - Field effect transistor having vertical gate sidewalls and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to metal oxide semiconductor field effect transistors (MOSFETs), and more particularly to MOSFETs having improved gate oxides and vertical sidewalls.

[0002]

2. Description of the Related Art The size, shape and quality of a polysilicon gate of a MOSFET are the same as those of a conventional MOSFET.
Of particular importance for future miniaturized MOSFETs.

In order to increase the degree of integration of memory chips and logic devices beyond what is currently possible, the size of the gates used in these chips and devices is further reduced, and the accuracy in forming these gates is improved. Must.

FIG. 1 schematically shows basic elements of a conventional MOSFET 10. Such an FET 10 is typically formed in a silicon substrate 11 with a doped source region 14 and a doped drain region 12 arranged to the left and right of a polysilicon gate pillar 13.
The gate pillar 13 is separated by an oxide layer 15 from a channel 17 located between the source region 14 and the drain region 12. Under the polysilicon gate 13, an oxide layer 15 functions as the gate oxide. In conventional FETs, the area under the gate oxide is thicker. This is because a portion of the oxide layer 15 not covered by the polysilicon gate is eroded during the polysilicon RIE, as described below. The junction 18 between the source channel and the drain channel is
Note that it is not definitive. The dopant concentration decreases as it approaches the actual channel. That is, the junction 18 between the source and the channel and between the drain and the channel is not reliably defined. This is mainly due to the sloped sidewalls 16 of the gate 13 that allow the dopant to reach the silicon substrate near the gate edge (overlapping the gate) when the source and drain regions 14 and 12 are implanted from above. I do. This increases the source and drain resistance, increases the overlap capacitance, and incorrectly defines the effective channel length, thereby reducing device performance.

[0005] Current technology uses silicon reactive ion etching (RIE) and photoresist to define the polysilicon gate of MOSFETs, including complementary metal oxide semiconductor (CMOS) FETs. RI
By the E process, two requirements must be satisfied. The polysilicon gate must have completely vertical sidewalls, and furthermore, the RIE process must stop there without destroying the gate oxide 15 at the bottom of the polysilicon gate 13. No. Usually, the gate oxide 15 is very thin (in the range of several nanometers), and becomes thinner as the size of the FET is reduced.

When processing the entire wafer, the thickness of the polysilicon layer to be the polysilicon gate of all MOSFETs on the wafer changes due to etching. To ensure that all polysilicon gates are correctly defined, all polysilicon gates, including those formed on relatively thick wafers, are reduced to a thin gate oxide 15. The etching time must be adjusted so that it is etched. However, this intentional over-etching locally reduces the thickness of the gate oxide 15 adjacent to the polysilicon gate 13 (as shown schematically in FIG. 1). This is because the selectivity in the polysilicon etching step is not sufficiently high. (Note that high selectivity means that only the material to be etched is eroded in the etching process, for example, polysilicon in this example, and the gate oxide is not eroded. Polysilicon RI
In the E etching step, not only the polysilicon but also the oxide layer 15 is eroded. Due to the low selectivity, the thickness of the gate oxide 15 adjacent to the polysilicon gate 13 is less than the thickness of the original oxide layer, as shown schematically in FIG. 1 (see below the polysilicon gate 13). ).

As selectivity is improved, the unwanted orientation of the polysilicon gate due to the reduced etch direction is caused by the currently used RIE etching of polysilicon. Is the essence of In other words, using conventional polysilicon RIE to form a polysilicon gate,
The sidewall slope increases or the thin oxide layer 15 erodes, resulting in a change in the overall thickness of the wafer. The RIE of the polysilicon can be adjusted to improve the selectivity between polysilicon and oxide, in which case the RIE
Increases the isotropic nature of the etching, and as a result, the sidewalls are further inclined.

As described above, when miniaturizing a MOSFET, the gate oxide must be thin. Obviously, the thinner the gate oxide, the less acceptable the overetch. In other words, etch selectivity must be improved for polysilicon gate miniaturization. For example, the gate oxide of a sub-0.1 micron CMOSFET has a thickness of 3 nm.
Is less than. Any over-etching will reduce the performance of the device.

[0009] The gate length L _G of the conventional transistor, briefly mentioned above, it is defined by photolithography and a series of RIE process. Since the resolution of photolithography is proportional to the wavelength of the exposure light, the gate length is about 1
Limited to 50 nm. Conventional optical lithography cannot be used to make smaller gates.

The current state of the art is capable of producing 250 nm wide features by irradiating light of 248 nm wavelength. Currently, light-based methods are a bottleneck when trying to obtain structures with feature dimensions smaller than 150 nm. State-of-the-art optical lithography systems for manufacturing current DRAMs are very expensive.
The future direction of the semiconductor industry is 180
nm, the latest technology of 70 nm in 2011 is required.

Alternative methods, such as X-ray lithography,
Moving to ever smaller feature sizes is attractive, but requires a significant investment. Therefore,
Techniques that are compatible with many existing processes are of intrinsic value.

At present, there is no known manufacturing method for realizing a MOSFET having vertical (non-sloped) sidewalls. Furthermore, the prior art is not suitable for miniaturizing FETs having a perfect gate oxide with a thickness of less than 5 nm.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOSFET with a precisely defined channel length, minimum source and drain resistance, and minimal overlap capacitance.

Another object of the present invention is to provide a miniaturized MOS.
An object of the present invention is to provide an FET, particularly a MOSFET having a size of less than 0.1 μm.

It is another object of the present invention to provide a method of manufacturing a MOSFET having a precisely defined channel length, a minimum source and drain resistance, and a minimum overlap capacitance.

Another object of the present invention is to provide a miniaturized MOS.
It is an object of the present invention to provide a method for manufacturing FETs, especially MOSFETs with dimensions less than 0.1 μm.

Another object of the present invention is to provide a precisely defined
An object of the present invention is to provide a method for manufacturing a MOSFET having a channel length of less than 150 nm.

Another object of the present invention is to provide a MOS transistor having a minimum source and drain resistance and a minimum overlap capacitance.
An object of the present invention is to provide a method for manufacturing an FET.

[0019]

The above objects are attained by the novel method of manufacturing a FET according to the present invention. Forming a dielectric stack having at least one pad oxide layer on the semiconductor structure; and having the same lateral dimensions and shape on the dielectric stack as the gate pillars to be formed. Defining an etch window having: a. Defining a gate hole on the dielectric stack by transferring the etch window to the dielectric stack using reactive ion etching (RIE). Depositing a gate conductor to fill the gate hole; removing a gate conductor covering a portion of the dielectric stack around the gate hole; removing at least a portion of the dielectric stack And a step of performing.

The above object has been achieved by another novel FE according to the present invention.
This is also achieved by the method of manufacturing T. The method includes the steps of: forming a dielectric stack on the semiconductor structure; defining an etch window on the dielectric stack; etching using reactive ion etching (RIE). Defining a gate hole on the dielectric stack by transferring the window to the dielectric stack; depositing a sidewall layer; leaving sidewall spacers inside the gate hole, thereby leaving the gate Removing the sidewall layer from the horizontal plane so as to reduce the lateral dimension of the hole; attaching a gate conductor to fill the gate hole; and removing the portion of the semiconductor structure around the gate hole. Removing the overlying gate conductor; removing at least a portion of the dielectric stack; and removing the sidewall spacer.

The method of the present invention uses a conventional MOS or CM
It replaces the portion of the OS process step typically used to define the gate conductor by the above sequence of steps.

The above process can be modified in various ways as addressed in the detailed description.

Advantages will become apparent from the detailed description and drawings. However, part of the advantage is that the sidewalls of the gate pillar are vertical. Another advantage of the present invention is that Si
The thickness of the O ₂ pad oxide is uniform, that is, the thickness of the pad oxide on the source and drain upper surfaces is uniform and does not change throughout the wafer. This ensures that there is no variation in the depth of the junction between the source and the drain throughout the entire wafer. In conventional devices where the thickness of the pad oxide varies, the depth of the source / drain junction is not uniform. This is particularly important with extended joints. Advantages will become apparent from the detailed description and drawings. Using a traditional photolithography process,
One advantage is that gate pillars can be formed that are smaller than lithographically possible. The vertical side walls of the gate pillars are another advantage.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION In the present specification, an n ⁺ -type or p ⁺ -type doped semiconductor means a highly doped semiconductor. These usually have a dopant concentration of at least 10 ¹⁸ to 10 ²² / cm ³ .

As used herein, the term MOSFET refers to any type of MOSFET, including CMOS, NMOS, PMOSFET, and the like. Further, a transistor includes a case where there is no oxide functioning as an isolation layer between a gate pillar and a channel. Instead of conventional oxides, any type of insulating layer can be used, such as a nitride layer.

It is the polysilicon gate that is emphasized in the following description. Instead of polysilicon, any type of material suitable for the gate conductor may be used. For example, tungsten can be used instead of polysilicon. Similarly, a stacked structure of polysilicon and silicide can be used as the gate. Instead of polysilicon, the gate holes may be "filled" with amorphous silicon, as shown below. Thereafter, the amorphous silicon can be converted to polysilicon by continuing the heat treatment.

FIG. 2 shows an FET 20 according to the present invention. Book
The FET is formed in the semiconductor substrate 21. This board
For example, a silicon substrate. In this embodiment, the drain
The region 22 and the source region 24⁺By doping
Is defined. Suitable dopant for n-type doping
Is, for example, P, As or Sb. p-type source
B, In or Ga is used for the region and the drain region.
Can be used. The polysilicon gate 23 is thin
Not SiO_TwoIt is provided on the upper surface of the gate oxide 28. Gate structure
The surface around the structure is usually before the shallow isolation trench is defined.
Covered by the rest of the pad oxide layer that adheres
(Not shown in FIG. 2). Same as FIG.
Used for contact with gate, source and drain
No electrodes are shown. As shown in the figure,
The sidewall 26 of the silicon gate 23 is vertical. Saw
Junction 29 between source and channel and between drain and channel
(Interface between source and channel and between drain and channel
Are also precisely defined, source and drain regions
When implanting the region, the dopants
Insulated because there are no sloping gate sidewalls that can enter the area
Have been. The interface 29 is substantially vertical. Accordingly
The effective channel length is mainly due to the minimal overlap
Is defined by the length of the gate pillar 26. Paraphrase
If this mask window is the length of the pillar gate
And transferred to the dielectric stack that defines the width
Gate mask window dimensions and channel length
Is specified. Due to the vertical side walls of the gate, heavy
Is minimized, resulting in source and drain resistance,
And the overlap capacitance is reduced. In addition, games
G length L _GIs possible with conventional photolithography technology
Shorter than the ones. In this specification, such a gate is referred to as a sub-gate.
Called a lithographic gate. Sub lithography
FETs with a back gate have at least one lateral
Direction dimension (gate length or gate width)
Feature size possible by dynamic lithography
A transistor having a gate conductor smaller than the normal.
That is, the gate length and / or gate width
It refers to those having a thickness of 150 nm or less.

Another advantage of the structure of the present invention is that S
The thickness of the iO ₂ pad oxide 25 is uniform on the upper surfaces of the source region 24 and the drain region 22, that is, the thickness of the pad oxide does not change throughout the wafer. Further, the thin gate oxide 28 is formed independently of the pad oxide 25 and is not exposed to the polysilicon RIE process as when using conventional MOS fabrication methods.

According to the present invention, gate holes are formed by transferring a mask window to a dielectric stack. Next, after forming the sidewall layer, the sidewall spacer is removed from the horizontal plane so as to remain inside the gate hole. Width minus the thickness of the sidewall spacer from the gate hole defines a width of the gate length L _G and the gate-pillars to be formed. The vertical side walls of the gate minimize overlap, which results in source and drain resistance,
And the overlap capacitance is reduced.

The manufacturing method according to the present invention will be described in detail with reference to a series of steps (FIGS. 3 to 16). These steps need not necessarily be performed in the order shown and described. The manufacturing method according to the invention is particularly suitable for forming FETs with very thin gate oxides (<5 nm).

In the following example, the method of manufacturing an FET according to the present invention starts with a substrate 30. This substrate is covered with a pad oxide layer 35 and a nitride layer 31. The substrate 30
For example, a silicon substrate may be used. An 8 nm thick SiO ₂ layer 35 can be used as pad oxide. The thickness of the pad oxide layer is usually 5 nm to 20 nm. The oxide layer 35 is formed by rapid thermal processing (RTP) or furnace processing.

The nitride layer 31 may be made of Si ₃ N ₄ and may have a thickness of about 90 nm. This nitride layer 31 can be formed using, for example, high-temperature low-pressure chemical vapor deposition (LPCVD). Other deposition methods can be used, such as plasma enhanced chemical vapor deposition (PECVD). Similarly, a nitride may be sputtered.

Next, a single photoresist layer 32 is spin-coated on the nitride layer 31. The resist layer 32 is then patterned by conventional lithography to define an etch window 33 for a subsequent etching step, as shown in FIG. Instead of using a single layer of photoresist, a multi-layer resist,
Other masks can be used, for example, a hard baked mask. The dimensions of the etch window 33 are changed to the next shallow trench isolation (ST
I) Determine the lateral dimensions of the trench. Such S
TI (also referred to as field oxide isolation) usually uses MOS and CMOS for isolation between adjacent transistors.
Used in technology. Instead of STI, LOCOS (local oxidation of silicon) or polybuffer LOCOS can be used.

As shown in FIG. 5, the resist pattern is now transferred to the underlying stack using a suitable etching technique. This step is not essential. The depth D _STI of the STI trench 34 may be 100 nm or more. Before filling the STI trench with a suitable isolation material, a thin oxide layer 46 may be thermally grown inside the trench 34. This is particularly recommended if the trench 34 is to be filled with an attached oxide, tetraethyl orthosilicate (TEOS). The attached TEOS usually has a surface state at an interface with the silicon substrate 30. Such a surface condition is not desirable.

In this example, after removing the resist 32 and forming a thin thermal oxide 46, as shown in FIG. 6, the TEOS 3 is filled so that the STI trench 34 is filled to the bottom.
6 is attached. TEOS 36 can be deposited using, for example, a low pressure chemical vapor deposition (LPCVD) process. Many other materials are also associated with the associated transistor (FIG. 3).
(Not shown in FIG. 16) can be used instead of TEOS as long as sufficient isolation is guaranteed.

An advantage of TEOS is that it provides a very good stop layer for any subsequent chemical mechanical polishing (CMP) planarization process.

As shown schematically in FIG. 7, the top surface of the structure is now planarized using, for example, CMP. In the present embodiment, the excess TEOS 36 is removed by CMP,
Polishing stops at nitride layer 31. Thereby, the upper surface 37 of the layer 31 becomes completely flat. After CMP, the thickness of this nitride layer 31 will decrease slightly to about 75 nm.

In a subsequent step (see FIG. 8), a dielectric stack is completed on top of the pad oxide layer 35 by adding layers on top of the planarized surface 37. In this example, the dielectric stack comprises: a Si ₃ N ₄ nitride layer 31 (thickness reduced to about 75 nm); a Si ₃ N ₄ nitride layer 38 (thickness of about 50 nm); a TEOS layer 39 (thickness of about 60 nm). ).

Like nitrides, TEOS can be produced, for example, by LPC
It can be deposited using a VD process. For reasons of compatibility with existing device technology, materials such as silicon or nitride and respective oxides are preferred.

Because TEOS can be precisely etched by RIE, it is best suited for the top layer of a dielectric stack. TEOS etched by RIE has a smooth surface. This is because the resist pattern is exactly T
Transferred to EOS, it acts as an excellent hard mask for subsequent RIE etching. Note, however, that TEOS is removed when etching the pad oxide at the bottom of the gate hole, as described with reference to FIG. Similarly, the dielectric stack may consist of one type of polymer or several polymer layers. Any other dielectric stack can be used, as long as it is guaranteed that the stack is etched to form gate holes with vertical sidewalls. 9 and 1
As described with reference to FIG. 0, it is important that an etchant with a high degree of selectivity can be used for etching a gate hole. The dielectric stack, and the layer or layers that comprise it, must be compatible with existing device technology.

As described with reference to FIG. 18, the dielectric stack may be composed only of nitride. Such a nitride-only stack can be etched without attacking silicon and pad oxide.

In this embodiment, the dielectric stack is formed on top of a semiconductor structure already composed of specific layers and structural elements, such as STI or LOCOS trenches. Note that the dielectric stack can be formed on any type of semiconductor structure, including simple substrates, pre-processed substrates, semiconductor devices with other circuits, and the like.

In this specification, the expression “gate pillar” is used to represent a gate structure protruding from a semiconductor structure. The pillars may have any size and shape as long as the side walls are vertical, that is, perpendicular to the semiconductor structure.

In the following steps, photolithography is used to determine the lateral dimensions (gate length L _GATE and gate width L _WIDTH ) and the shape of the gate pillar to be formed. This process has many different ways to determine the lateral dimensions of the gate pillars,
This step is not shown. Basically, resist
An etch window 40 is provided in the mask 48 which is substantially equal to the lateral dimension of the gate pillar whose dimension is to be formed (see FIG. 9). Note that the length of the etch window 40 ultimately determines the length of the gate hole, which determines the gate length L _GATE . This gate length L _GATE
Determines the effective channel length.

Next, formation of a gate hole will be described. The RIE process for forming a gate hole
An etch window 40 provided in a resist 48 (this dielectric stack comprises a nitride layer 31, a nitride layer 3 in this example).
8 and TEOS layer 39) are used to transfer the dielectric stack.
The RIE process for forming gate holes can be optimized to ensure that the various layers of the dielectric stack are properly etched. Several RIE steps optimized to etch each layer of the dielectric stack can be performed. For example, when etching the TEOS layer 39, selectivity to nitride is appropriately selected. A selectivity to nitride of 3: 1 or better is suitable, which means that TEOS etches three times faster than nitride. The RIE process can form excellent vertical sidewalls throughout the dielectric stack. Etch window 40 is TEO
After being precisely transferred to the S layer 39, a second RIE step is performed. This second RIE step is designed to have high selectivity to the pad oxide 35. A selectivity between nitride and pad oxide of 5: 1 or more is suitable. 1
A selectivity of 0: 1 or more is preferred.

In this example, the RIE step for forming the gate is designed to etch the nitride layers 38 and 31 of the dielectric stack and stop at the pad oxide layer 35, as shown in FIG. ing. This second RIE step is the final RIE step in a series of individually optimized RIE steps. It is important that the selectivity to pad oxide be 5: 1 or better. This is because otherwise, the pad oxide 35 is severely eroded and its thickness is reduced.

After forming gate hole 40, a portion of the dielectric stack may be removed (as described below) or processing may continue without removing any of these layers. In this example, processing is continued after the TEOS layer 39 is removed. In this case, the depth D _GATE of the gate hole 40 is
This is almost the same as the sum D _STACK of the thicknesses of the layers 31 and 38 (see FIGS. 10 and 8). The depth D _GATE determines the height of the gate pillar 41 containing the gate oxide to be formed. Pillars that function as gates are usually 100
nm, specifically 100 nm to 200 nm
It is. Future CMOSFET gate length is 150nm
Or it could be shorter. Such a short gate (150 nm or less, also referred to as a sublithographic gate) can be easily formed by using the method of the present invention. The width of the conventional gate electrode (from the paper)
It is 2 μm to 50 μm. The gate width can also be sub-lithographic if desired.

After the gate holes 40 have been defined by RIE, a thin sidewall layer 60 is deposited, as shown in FIG. Pad oxide 35 should not be removed prior to depositing sidewall layer 60 (see FIG. 10). This layer 60 can be a nitride layer that closely matches the vertical sidewalls of the gate hole 40. Such a nitride layer can be precisely controlled.

Next, the following etching step is performed to remove the side wall layer 60 from the horizontal plane. Blanket RIE
(Or other methods) can be used. Sidewall layer 60
Since the thickness of the horizontal portion is slightly smaller than the thickness of the vertical portion (the portion covering the side wall of the gate hole 40),
These horizontal parts can be removed without eroding much of the vertical parts. When this etching step is completed, as shown in FIG. 12, a sidewall spacer 61 having a precisely defined thickness remains. This sidewall spacer 61 reduces the length of the gate hole 40. Minus twice the thickness of the sidewall layer 60 from the length of the gate hole determines the length L _G of the gate 41 to be formed.

After the gate hole 40 has been defined in the dielectric stack, the remainder of the pad oxide 35 can be removed from the bottom of the gate hole 40. This can be done using an HF dip. HF is oxide 35 and T
It is optimal because it erodes EOS39. HF does not erode the silicon substrate 30. Before removing the TEOS layer 39 and pad oxide from the bottom of the gate hole 40, the resist is removed. After completely removing the TEOS layer 39 and the pad oxide 35, as shown in FIG. 10, a precisely defined gate oxide 49 can be formed, as shown in FIG. The thickness and quality of the gate oxide 49 is independent of the thickness and quality of the pad oxide layer 35.
The gate oxide may be thicker than the pad oxide if necessary.

Prior to forming gate oxide 49, a sacrificial oxide layer (not shown) may be formed at the bottom of gate hole 40. Thereafter, the sacrificial oxide layer is removed by etching, and the structure is heated. This series of short steps repairs the potentially damaged silicon substrate 30 at the bottom of the gate hole 40 (due to RIE for gate formation).

In an alternative embodiment, the RIE step for gate hole formation can be designed such that the pad oxide layer 35 is etched as well as the dielectric stack. In this case, the selectivity to silicon in the second RIE step needs to be appropriate. This would otherwise result in the silicon substrate 3 at the bottom of the gate hole 40
This is because 0 is removed by etching. Once the silicon substrate 30 at the bottom of the gate hole 40 is exposed, the gate oxide layer 49 can be formed by oxidation as described above. Before forming the gate oxide layer 49, a sacrificial oxide layer can be grown as described above. This is of high importance here because the damage of the silicon by RIE is worst. The thickness of the sacrificial oxide layer may be about 2 nm. Next, a sidewall of nitride is formed, so that the sidewall spacer 61 remains on the vertical surface of the gate hole. After this step, the sacrificial oxide layer is removed (etched) and the gate oxide layer 49 is oxidized as described above.
To form

Next, as shown in FIG.
1 is deposited in the gate hole 40 and on the top layer 38 of the dielectric stack. This is important to ensure that the polysilicon 41 completely fills the gate hole 40. Polysilicon can be deposited by LPCVD (eg, about 650 ° C.). As described above, amorphous silicon may be attached instead of polysilicon. Thereafter, the amorphous silicon can be converted to polysilicon.

The polysilicon may or may not be doped. The dopant may be introduced when depositing the polysilicon or later. An advantage of the present invention is that the polysilicon gate need not be doped when implanting the source and drain regions. The polysilicon gate is
It can be silicide (polycide) in any of the subsequent fabrication steps and, if deemed appropriate, a cap dielectric can be deposited for protection during the subsequent fabrication steps.

As mentioned above, any material suitable for a gate conductor can be "filled" in the gate hole 40. The present invention is not limited to polysilicon gates.

After the material 41 functioning as a gate conductor is attached, a planarization step can be performed. The optimal process is CMP. After planarization, the top layer 38 of the dielectric stack is exposed, as shown in FIG.

Last but not least, the dielectric stack must be removed. Nitride layers 38 and 31 can be stripped using heated phosphoric acid. When the dielectric stack is completely removed, protruding gate pillars 41 having vertical sidewalls 42 are exposed, as shown in FIG.

During the subsequent steps, if not already done, the source region 43 and the drain region 44 can be defined by implanting appropriate dopants, as shown in FIG. A channel 45 (located below the gate pillar 41 and between the drain region 44 and the source region 43) is thus defined. As already described, the channel length is approximately equal to the gate length because the interface between the source and the channel and between the drain and the channel is steep and separated (correctly defined) and has minimal overlap. . Gate length L _G can be made shorter than that specified by using the conventional process. By the above-described series of steps according to the present invention, a gate having a sublithographic length can be formed.

Instead of the standard source and drain regions obtained by implantation, a source / drain junction diffused by outward diffusion from a polysilicon layer formed on the region to be doped may be formed. In this way, the very shallow junction required for short channel FETs can be obtained. One example is "Source-drain For
mation for CMOS Transistors Formed by Outdiffusion
From Polysilicon, ”IBM Technical Disclosure Bulletin, No. 2, 1991 7
Month, p. 287-290.

To complete the FET, an electrode must be provided. Suitable electrodes are conductive materials, particularly those deposited by vapor deposition and etching, or other methods.
It is formed of a metal such as u, Al, Mo, Ta, Ti, Cu, or ITO (indium tin oxide). further,
A metallization pattern is formed to interconnect adjacent FETs.

The above embodiment and alternative embodiments can be modified in various ways as described below.

For example, the region doped n ⁺
It can be replaced with a p ⁺ doped region. The dimensions and shapes of the doped regions can vary. The substrate can be a p-doped or n-doped silicon substrate, silicon-on-insulator (SO
I) The substrate may be used. For example, a well implant can be used to define a p-type doped region in an n-type doped substrate. As a result, an n-type FET (also referred to as an n-channel FET or NMOS) is formed in the p-type doped region, and the p-type FET is formed.
ET (also called p-channel FET or PMOS)
It can be formed directly on a mold-doped substrate.
In CMOS technology, p-well or n-well diffusion can be performed before forming source and drain regions.

[0063] Both NMOSFETs and PMOSFETs can be formed by the method of the present invention. MOSFETs of different channel types and structures can be formed in one and the same substrate.

As shown in FIG. 15, instead of removing the entire dielectric stack to obtain the protruding gate pillar 41, it is also possible to remove only a part of the dielectric stack as shown in FIG. it can. For example, it is possible to remove only layers 39 and 38. That is, in this case, the nitride layer 31 is not removed. In order to be able to form a drain implant and a source implant, holes 50 can be formed in the nitride layer 31 as shown in FIG. These holes 5
Via 0, dopants can be implanted into regions 51 in substrate 30. After defining the source and drain regions (not shown), source and drain contacts can be formed in holes 50.

Referring to FIG. 18, another alternative embodiment will be described. This alternative embodiment is characterized in that the dielectric stack consists only of nitride (layers 61 and 63). There is no TEOS layer. In this case, gate hole 6
4 (D _GATE ) is the thickness of the dielectric stack (D _GATE ).
_STACK ) and the height of the formed gate pillar (H _GATE ).

In standard FETs, the thickness of the pad oxide on the top of the source and drain regions is not uniform due to the RIE of the polysilicon normally used to define the gate pillars. Since the source and drain regions are implanted through a non-uniform pad oxide layer,
The depths of the source region and the drain region change throughout the wafer. Another advantage of the method according to the invention is that the uniformity is high over the entire wafer and good control of the cross-sectional shape and dimensions of the gate is ensured.

The method according to the invention has the potential to produce devices smaller than 0.5 μm. Note that for devices less than 0.1 μm, gate length L is less than 0.1 μm.

The method of the present invention is suitable for manufacturing a highly integrated multi-gigabit DRAM.

The FET according to the present invention can be used in various circuits, such as high-performance logic, power-down logic, or high-density storage devices, including the multi-gigabit DRAM described above. The FET of the present invention can be easily combined with other components, for example, capacitors, resistors, diodes, memory cells, and the like. FE of the present invention
Because T is small and easy to manufacture, it is also suitable for use in connection with organic displays and liquid crystal displays (LCDs).

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) A drain region and a source region adjacent to the channel region, a thin gate oxide located on the channel region, and a gate conductor located on the gate oxide, wherein the gate conductor has vertical side walls, and A metal oxide semiconductor field effect transistor (MOSFET) having a junction between a source region and a channel region and not joining the drain region and the channel region. (2) The transistor according to (1), wherein the gate oxide is a thermally grown gate oxide. (3) The transistor according to (1), wherein the gate conductor is polysilicon. (4) The transistor according to (1), wherein the gate conductor is tungsten. (5) The transistor according to (1), which is a sub-0.1 micron device having a gate length L of less than 0.1 μm. (6) The transistor according to (1), wherein the thickness of the gate oxide is in the range of several nanometers. (7) The MOSFET is a PMOS, NMOS, or C
The transistor according to the above (1), which is a MOS transistor. (8) The transistor according to (1), wherein the channel region includes undoped silicon. (9) The transistor according to (1), wherein the channel region is silicon doped with B, In, or any combination thereof. (10) The above (1), wherein the channel region is silicon doped with P, As, Sb, or any combination thereof.
A transistor according to claim 1. (11) The transistor according to (1), wherein a boundary surface between the source region and the channel region and a boundary surface between the drain region and the channel region are clearly defined. (12) The transistor according to (1), wherein the slope of the boundary surface between the source region and the channel region and between the drain region and the channel region is steep. (13) The transistor according to (1), wherein the effective gate length is defined by the length of the gate conductor. (14) forming a dielectric stack having at least one pad oxide layer on the semiconductor structure; and forming an etch stack on the dielectric stack having the same lateral dimensions and shape as the gate pillar to be formed. Defining a window; defining a gate hole in the dielectric stack by transferring the etch window to the dielectric stack using reactive ion etching (RIE); Depositing the gate conductor to fill the gate stack, removing the gate conductor covering a portion of the dielectric stack around the gate hole, and opening the dielectric stack such that the gate pillar having vertical sidewalls is opened. Removing at least a part of a metal oxide semiconductor field effect transistor (MOSFET)
Manufacturing method. (15) The dielectric stack comprises a nitride layer, preferably Si
The process according to (14) containing ₄ N ₃ layers. (16) The method according to (14), wherein the dielectric stack includes a tetraethyl orthosilicate (TEOS) layer. (17) The method according to (14), wherein the thickness of the pad oxide is 5 nm to 20 nm. (18) The manufacturing method according to the above (14), wherein the etch window is defined using photolithography subsequent to the resist. (19) The method of (14) above, wherein the etch window is transferred to the dielectric stack using a series of reactive ion etching (RIE) steps. (20) The method according to (14), wherein after the step of defining the gate hole in the dielectric stack, the pad oxide layer at the bottom of the gate hole is removed. (21) The method according to (14), wherein a thin gate oxide is formed at the bottom of the gate hole. (22) The manufacturing method according to the above (14), wherein the gate conductor contains polysilicon or tungsten. (23) Chemical mechanical polishing (CM) to remove the gate conductor covering the portion of the dielectric stack around the gate hole
The production method according to (14), wherein P) is used. (24) The method according to (14), wherein after forming the gate pillar, the entire dielectric stack is removed. (25) The manufacturing method according to the above (14), which is a sub-0.1 micron device having a gate length L of less than 0.1 μm. (26) When the metal oxide semiconductor field effect transistor is P
The manufacturing method according to the above (14), which is a MOS, NMOS, or CMOS transistor. (27) The method according to (14), wherein the source and drain regions are formed by implanting a dopant, and the source and drain regions are not respectively joined to a channel located below an edge of the gate pillar. (28) The manufacturing method according to the above (14), wherein the effective gate length is defined by the length of the gate pillar. (29) The method according to (14), further including the step of forming a sacrificial oxide at the bottom of the gate hole, the step of removing the sacrificial oxide by etching, and the step of heating the metal oxide semiconductor field effect transistor. )). (30) forming a dielectric stack on the semiconductor structure, defining an etch window on the dielectric stack, and forming the etch window on the dielectric stack using reactive ion etching (RIE). Transferring to the stack defines a gate hole in the dielectric stack, deposits a sidewall layer, and leaves sidewall spacers inside the gate hole, thereby reducing the lateral dimension of the gate hole. Removing the sidewall layer from the horizontal plane to reduce the thickness, depositing the gate conductor to fill the gate hole, removing the gate conductor outside the gate hole, and removing at least the dielectric stack. A metal oxide semiconductor field effect transistor (MOSFET) including a step of removing a part and a step of removing a sidewall spacer. Production method. (31) The dielectric stack comprises a nitride layer, preferably Si
The process according to the above (30) containing ₄ N ₃ layers. (32) The method according to (30), wherein the dielectric stack includes a tetraethyl orthosilicate (TEOS) layer. (33) The above (30), wherein the dielectric stack comprises a polymer.
The production method described in 1. (34) The manufacturing method according to (30), wherein the etch window is defined using photolithography subsequent to the resist. (35) The method of (30) above, wherein the etch window is transferred to the dielectric stack using a series of reactive ion etching (RIE) steps. (36) The method of (30) above, wherein each step of a series of reactive ion etching (RIE) steps is optimized for each layer of the dielectric stack that is assumed to be etched. (37) The method of (30), wherein a series of reactive ion etching (RIE) steps are optimized to etch gate holes with vertical sidewalls throughout the dielectric stack. (38) The manufacturing method according to the above (30), wherein a thin gate oxide is formed at the bottom of the gate hole after removing the side wall layer from the horizontal plane. (39) The method according to (30), wherein the gate conductor contains polysilicon or tungsten. (40) Chemical mechanical polishing (CM) to remove the gate conductor covering the portion of the dielectric stack around the gate hole
The production method according to (30), wherein P) is used. (41) The method according to (30), wherein after forming the gate pillar, the entire dielectric stack is removed. (42) The manufacturing method according to the above (30), wherein the side wall spacer is removed separately from the dielectric stack. (43) The transistor has a gate length (L _G ) of 150 n
The method according to the above (30), wherein the device is smaller than m. (44) transistors, the manufacturing method according to the gate length (L _G) above (30) which is a device of the sub-lithographic. (45) The method according to (30), wherein the MOSFET is a PMOS, NMOS, or CMOS transistor. (46) The manufacturing method according to (30), wherein the source and drain regions are formed by implanting a dopant, and the source and drain regions are not respectively connected to the channel located below the edge of the gate pillar. (47) the effective gate length, the production method according to (30) defined by the length of the gate (L _G). (48) The method according to (30), further including the step of forming a sacrificial oxide at the bottom of the gate hole, the step of removing the sacrificial oxide by etching, and the step of heating the metal oxide semiconductor field effect transistor. )). (49) The method according to (30), wherein a pad oxide layer is formed on the semiconductor structure, and then an etch window is defined on the dielectric stack.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a basic structure of a conventional MOSFET.

FIG. 2 is a schematic sectional view showing a basic structure of a MOSFET according to the present invention.

FIG. 3 shows a substrate coated with pad oxide and nitride layers.

FIG. 4 is a diagram showing a manufacturing intermediate process after patterning a photoresist for etching STI or LOCOS isolation.

FIG. 5 illustrates an intermediate manufacturing step after using photoresist as an etch mask for etching the STI trench.

FIG. 6 is a diagram showing an intermediate manufacturing step after filling a TEOS layer in an STI trench.

FIG. 7 is a view showing a manufacturing intermediate step after removing TEOS and a part of the nitride layer by planarization.

FIG. 8 is a diagram showing an intermediate manufacturing step after an additional layer is formed.

FIG. 9 is a diagram showing a manufacturing intermediate step after a photoresist layer is added, patterning is performed by lithography, and gate holes having vertical side walls are formed.

FIG. 10: The resist is removed, and T at the bottom of the gate hole is removed.
FIG. 4 is an enlarged view showing the gate holes after etching the EOS and pad oxide layers.

FIG. 11 is a view showing a manufacturing intermediate step after a sidewall layer is attached.

FIG. 12 is a view showing an intermediate manufacturing process in which a side wall layer is removed from a horizontal plane, and a side wall spacer is left at a bottom of a gate hole.

FIG. 13 is a diagram showing an intermediate manufacturing step after the gate hole is filled with polysilicon. Note that a thin gate oxide layer is formed at the bottom of the gate hole before the gate hole is filled.

FIG. 14 shows the state after the polysilicon is removed by planarization.
It is a figure which shows a manufacturing intermediate process.

FIG. 15 illustrates the intermediate manufacturing steps after removing the dielectric stack consisting of several layers so that the polysilicon gate pillars with vertical sidewalls remain.

FIG. 16 illustrates an intermediate manufacturing step after dopants have been introduced to define source and drain regions.

FIG. 17 is a schematic sectional view showing another embodiment according to the present invention.

FIG. 18 is a schematic sectional view showing still another embodiment according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 MOSFET 11 Silicon substrate 12 Drain region 13 Gate pillar 14 Source region 15 Oxide layer 16 Gate side wall 17 Channel 18 Drain-channel junction 20 FET 21 Semiconductor substrate 22 Drain region 23 Polysilicon gate 24 Source region 25 Pad oxide Layer 26 Sidewall 29 Drain-Channel Junction 30 Substrate 31 Nitride Layer 32 Photoresist 33 Etch Window 35 Pad Oxide Layer 36 TEOS 37 Top of Layer 31 38 Nitride Layer 39 TEOS Layer 40 Gate Hole 41 Polysilicon 43 Source 44 Drain 46 Oxide layer 49 Gate oxide 50 Hole 64 Gate hole

──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Stuart M. Burns United States 06840 Brookfield, Dogwood Lane, Connecticut 6 (72) Inventor Hussein I Hanaphy United States 10598 Goldens Bridge, New York Apache Apache Circle P.O. Box 243 (72) Inventor Ewan Taull United States 10506 New York Bedford Finch Lane 11 (72) Inventor William Sea Will United States 06830 Greenwich, Connecticut Old Field Point Road 11 Apartment 1-B (56) References JP-A-6-169082 (JP, A) JP-A-8-306672 (JP A) JP-A-7-263679 (JP, A) JP-A-9-321285 (JP, A) JP-A-9-121050 (JP, A) JP-A-2-25072 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/3065 H01L 21/8238 H01L 27/092

Claims (19)

(57) [Claims] A nitride layer on a semiconductor structure and a nitride layer on the nitride layer
Forming a dielectric stack including a tetraethylorthosilicate (TEOS) layer; and using reactive ion etching (RIE) to form the dielectric stack.
Form a resist on the dielectric stack on the TEOS layer
Transferring the formed etch window; and etching the TEOS layer at least three times faster than the nitride layer.
Reactive ion etching with a ring selectivity (RI
E) transferring the etch window transferred to the TEOS to the dielectric stack using E)
Defining a gate hole in the dielectric stack; depositing a sidewall layer; leaving sidewall spacers inside the gate hole to reduce lateral dimensions of the gate hole. Removing the sidewall layer from a horizontal surface; attaching a gate conductor to fill the gate hole; removing a gate conductor outside the gate hole; and at least one of the dielectric stacks. removing a portion, seen including a step of removing the sidewall spacers, the gate hole defined in said nitride layer, said dielectric
In the process of defining gate holes in the body stack
The etch window transferred to the TEOS layer
Has substantially vertical sidewalls due to precise transfer
A method for manufacturing a metal oxide semiconductor field effect transistor (MOSFET). 2. The method according to claim 1, wherein the dielectric stack comprises a nitride layer, preferably a Si4N3 layer. 3. The method of claim 1, wherein said dielectric stack comprises a polymer. 4. The method of claim 1, wherein the etch window is defined using photolithography following the resist. 5. A series of reactive ion etching (RI)
The method of claim 1, wherein an etch window is transferred to the dielectric stack using step E). 6. A series of reactive ion etching (RI)
2. The method of claim 1, wherein each step of E) is optimized for each layer of the dielectric stack that is assumed to be etched.
The production method described in 1. 7. A series of reactive ion etching (RI)
The method of claim 1, wherein E) is optimized to etch the gate hole having vertical sidewalls throughout the dielectric stack. 8. The method of claim 1, wherein after removing the sidewall layer from a horizontal plane, a thin gate oxide is formed at the bottom of the gate hole. 9. The method according to claim 1, wherein said gate conductor includes polysilicon or tungsten. 10. The method of claim 11, wherein chemical mechanical polishing (CMP) is used to remove a gate conductor covering a portion of the dielectric stack around the gate hole. 11. The method according to claim 1, wherein after forming the gate pillar, the entire dielectric stack is removed. 12. The method of claim 1, wherein said sidewall spacer is removed separately from said dielectric stack. 13. The transistor according to claim 1, wherein said transistor has a gate length (L _G ).
The production method according to claim 1, wherein is a device having a diameter of less than 150 nm. 14. The transistor according to claim 1, wherein said transistor has a gate length (L _G ).
2. The method of claim 1, wherein is a sub-0.1 micron device. 15. The semiconductor device according to claim 15, wherein said MOSFET is a PMOS, NMO
The manufacturing method according to claim 1, wherein the manufacturing method is S or a CMOS transistor. 16. The method of claim 1, wherein the source and drain regions are formed by implanting dopants, and wherein each of the source and drain regions is not joined to a channel located below a gate pillar edge. 17. The method according to claim 1, wherein an effective gate length is defined by a length (L _G ) of the gate conductor. 18. The method according to claim 18, further comprising: forming a sacrificial oxide at the bottom of the gate hole; removing the sacrificial oxide by etching; and heating the metal oxide semiconductor field effect transistor. The production method according to claim 11, comprising: 19. The method of claim 1, wherein a pad oxide layer is formed on the semiconductor structure and then defines an etch window on the dielectric stack.