JP3241329B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a semiconductor element having a double gate electrode structure and a transistor element are formed close to a semiconductor substrate. It is.

[0002]

2. Description of the Related Art A MOS type semiconductor device having a built-in nonvolatile memory element having a double gate electrode structure can easily write data electrically. An operation program can be easily written. As a result, when a system using a microcomputer is developed, the time required for system development can be significantly reduced. A MOS type semiconductor device incorporating the above-described nonvolatile memory element that produces such an effect includes: a nonvolatile memory element having a double gate electrode on a semiconductor substrate;
It is formed by arranging a large number of MOS transistor elements constituting a peripheral circuit of the memory element in close proximity.

FIG. 2 is a process diagram showing a method of manufacturing a conventional MOS type semiconductor device in which a nonvolatile memory element having a double gate electrode and a MOS transistor element are formed close to each other. Hereinafter, a conventional method for manufacturing the MOS type semiconductor device will be described with reference to FIG. (A) of FIG.
First, a thick silicon oxide film 104 is selectively formed on a P-type silicon substrate 102 as shown in FIG. This thick oxide film 104 is for separating between adjacent MOS transistor elements, between adjacent nonvolatile memory elements, and between the MOS transistor element and the nonvolatile memory element.

Next, as shown in FIG. 2B, a pattern of the floating gate electrode 108 constituting the nonvolatile memory element is formed in the nonvolatile memory element forming region 106 by a polycrystalline silicon film. It is formed on a P-type silicon substrate via an oxide film 104 having a thickness optimal for the characteristics of the memory element. In the MOS transistor formation region 110, as shown in FIG. 2C, the pattern of the gate electrode 112 of the MOS transistor element constituting the peripheral circuit of the nonvolatile memory element is formed by a polycrystalline silicon film.
It is formed on a P-type silicon substrate 102 via an oxide film 104 having a film thickness optimal for MOS transistor characteristics.

[0005] Next, as shown in FIG. 2 (D), the periphery of the gate electrode 112 and the like are masked by a photoresist 114, and arsenic is implanted into both sides of the floating gate electrode 108 by ion implantation to form a nonvolatile memory. N-type diffusion layer 116 having a concentration optimal for the characteristic memory characteristics is formed. After that, the photoresist 114 is removed. Subsequently, as shown in FIG. 2E, a control gate electrode 118 constituting a nonvolatile memory element is formed on the floating gate electrode 108 via an insulating film.
Arsenic is implanted into both sides of the gate electrode 112 by ion implantation, and the MO is formed.
An N-type diffusion layer 122 having a concentration optimal for S transistor characteristics is formed. After that, the photoresist 120 is removed.

Next, the non-volatile memory element formation region 106
2 and an MOS transistor element formation region 110, an interlayer film 124 is formed over the entire region, and as shown in FIG.
2, an N-type diffusion layer 116 from the surface of the interlayer film 124,
A connection hole 126 leading to 122 is formed. Then, FIG.
As shown in (G) of FIG.
By forming a patterned metal wiring layer 128 connected to the type diffusion layers 116 and 122, a MOS type semiconductor device incorporating a nonvolatile memory element having a double gate electrode structure is completed.

[0007]

However, in such a conventional method of manufacturing a semiconductor device, the control gate electrode 118 and the metal wiring layer 12 constituting the nonvolatile memory element are not provided.
Since each element such as 8 is simply formed individually and sequentially, the number of steps is large, and the number of required masks is large because different masks are used for each element forming step. As a result, not only the problem that the manufacturing cost is increased, but also the problem that the period required for product development becomes longer because the trial production and the like take time.
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the number of steps and the number of masks are reduced.

[0008]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor element having a double gate electrode structure and a transistor element are formed close to a semiconductor substrate. A gate electrode forming step of forming a floating gate electrode forming the semiconductor element and a gate electrode forming the transistor element in close proximity to each other via a semiconductor oxide film on the semiconductor substrate;
Forming a first impurity diffusion layer region having a conductivity type different from that of the semiconductor substrate on the surface of the semiconductor substrate on both sides of the gate electrode of the transistor element; and forming an interlayer on the semiconductor substrate. After depositing the membrane,
Removing the interlayer film and the semiconductor oxide film around the floating gate electrode, and diffusing the first impurity diffusion from the surface of the interlayer film into the semiconductor oxide film and the interlayer film on the first impurity diffusion layer region; An interlayer film forming step of forming a connection hole communicating with a layer region; an insulating film forming step of forming an insulating film over the entire surface of the semiconductor element and the transistor element forming area; and a surface of the semiconductor substrate on both sides of the floating gate electrode Forming a second impurity diffusion layer region having a conductivity type different from that of the semiconductor substrate, and partially removing the insulating film above the second impurity diffusion layer region. Exposing the second impurity diffusion layer region, and removing the insulating film on the first impurity diffusion layer region formed in a deep portion of the connection hole, thereby removing the first impurity diffusion layer region. An insulating film removing step of exposing, forming a control gate electrode on the floating gate electrode via the insulating film, and forming the first and second impurity diffusion layers at exposed portions of the first and second impurity diffusion layer regions. Forming a metal wiring layer respectively connected to the impurity diffusion layer region on the interlayer film and the insulating film.

In the method of manufacturing a semiconductor device according to the present invention, first, in a gate electrode forming step, a floating gate electrode forming a semiconductor element and a gate electrode forming a transistor element are interposed on a semiconductor substrate via a semiconductor oxide film. And in the first impurity diffusion layer region forming step,
A first impurity diffusion layer region of a conductivity type different from that of the semiconductor substrate is formed on the surface of the semiconductor substrate on both sides of the gate electrode of the transistor element. Then, in the interlayer film forming step, after the interlayer film is deposited on the semiconductor substrate, the interlayer film and the semiconductor oxide film around the floating gate electrode are removed, and the semiconductor oxide film and the semiconductor oxide film on the first impurity diffusion layer region are removed. A connection hole is formed in the interlayer film from the surface of the interlayer film to the first impurity diffusion layer region. Subsequently, in the insulating film forming step, an insulating film is formed on the entire surface of the formation region of the semiconductor element and the transistor element, and in the second impurity diffusion layer region forming step, a semiconductor substrate is formed on both sides of the floating gate electrode. Form second impurity diffusion layer regions of different conductivity types. Then, in the insulating film removing step, the insulating film is partially removed at a position above the second impurity diffusion layer region to expose the second impurity diffusion layer region, and formed in the deep portion of the connection hole. The insulating film on the first impurity diffusion layer region is removed to expose the first impurity diffusion layer region. Thereafter, in a control gate electrode forming step, a control gate electrode is formed on the floating gate electrode via an insulating film, and the first and second impurity diffusion regions are exposed at the exposed portions of the first and second impurity diffusion layer regions. A metal wiring layer connected to each of the layer regions is formed on the interlayer film and the insulating film.

As described above, in the method of manufacturing a semiconductor device according to the present invention, after the interlayer film is deposited on the semiconductor substrate in the interlayer film forming step, the interlayer film around the floating gate electrode is removed to expose the floating gate electrode. Then, a control gate electrode and a metal wiring layer are simultaneously formed in a control gate electrode forming step through an insulating film forming step, a second impurity diffusion layer region forming step, and an insulating film removing step. Therefore, the control gate electrode and the metal wiring layer can be formed using only one mask, and the control gate electrode and the metal wiring layer can be formed simultaneously in one step. for that reason,
The number of required masks is reduced by one, and the number of required steps is also reduced by one. As a result, the manufacturing cost can be reduced, and the time required for product development can be shortened by shortening the time required for trial production.

A semiconductor device according to a method of manufacturing a semiconductor device according to the present invention is a semiconductor device in which a semiconductor element having a double gate electrode structure and a transistor element are formed close to each other on a semiconductor substrate. A floating gate electrode provided on the semiconductor substrate with a semiconductor oxide film interposed therebetween, and second and third floating gate electrodes formed on both sides of the floating gate electrode on the surface of the semiconductor substrate and having different conductivity types from the semiconductor substrate. An impurity diffusion layer region, an insulating film formed on the floating gate electrode and the second impurity diffusion layer region, and a control gate electrode formed on the floating gate electrode via the insulating film. And a metal wiring layer extending over the insulating film and connected to the second impurity diffusion layer region through an opening formed in the insulating film. A gate element disposed on the semiconductor substrate in the vicinity of the floating gate electrode via a semiconductor oxide film, and formed on both sides of the gate electrode on the surface of the semiconductor substrate, A first impurity diffusion layer region of a conductivity type different from that of the semiconductor substrate;
An interlayer film formed on the gate electrode and the first impurity diffusion layer region and a surface of the first impurity diffusion layer region from a surface of the interlayer film through an opening formed in the semiconductor oxide film; A connection hole and a metal wiring layer connected to the first impurity diffusion layer region through the connection hole and extending on the interlayer film.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process chart showing an example of a method for manufacturing a semiconductor device according to the present invention. Here, as an example, in order to manufacture a MOS type semiconductor device incorporating a nonvolatile memory element, a nonvolatile memory element having a double gate electrode on a semiconductor substrate and a MOS transistor element forming a peripheral circuit of the memory element Are formed close to each other.

First, as shown in FIG. 1 (A), 55 nm is formed on a P-type silicon substrate 2 (a semiconductor substrate according to the present invention).
A 0 nm thick oxide film 4 is selectively formed. The function of this oxide film 4 is the same as that of the conventional case described above. Next, as shown in FIG. 1B, the patterned floating gate electrode 6 of the nonvolatile memory element and the patterned gate electrode 8 of the MOS transistor element are respectively connected to the nonvolatile memory element forming region 10. Then, in the MOS transistor element formation region 12, a semiconductor oxide film 14 having a thickness of 8 nm is formed via a gate electrode formation process according to the present invention.

Subsequently, as shown in FIG.
Using the patterned photoresist 16 as a mask material, arsenic is implanted by ion implantation to form 2.5 × 10 ²⁰ cm
MO is added to the MOS transistor element formation region 12 having a concentration of ^-3.
The first N-type diffusion layer region 18 of the S transistor element is formed (first impurity diffusion layer region forming step according to the present invention). After that, the photoresist 16 is removed.

Further, after an interlayer film having a thickness of 1.0 μm is formed as a whole, the interlayer film around the floating gate electrode 6 and the semiconductor oxide film 14 are removed as shown in FIG. The connection hole 22 is formed in the semiconductor oxide film 14 and the interlayer film 20 on the first N-type diffusion layer region 18 exposing the gate electrode 6 and extending from the surface of the interlayer film 20 to the first N-type diffusion layer region 18. (Interlayer film forming step according to the present invention).
The thickness of the interlayer film 20 is sufficient to prevent the electrical characteristics of the MOS transistor element from deteriorating due to parasitic capacitance relating to a metal wiring layer to be formed later.

Subsequently, as shown in FIG.
An oxide film 24 (insulating film according to the present invention) having a thickness of 15 nm is entirely formed (insulating film forming step according to the present invention), and the second N-type diffusion layer region 2 in the nonvolatile memory element forming region 10 is formed.
6 is formed by ion-implanting arsenic so that the concentration becomes 1 × 10 ²⁰ cm ⁻³ (second impurity diffusion layer region forming step according to the present invention).

Further, as shown in FIG. 1F, a patterned photoresist 28 is formed in the non-volatile memory element forming region 10 and the oxide film 24 on the floating gate electrode 6 is left. The oxide film 24 is partially removed above the second N-type diffusion layer region 26 in the memory element formation region 10, and the first oxide film 24 formed in the deep portion of the connection hole 22 in the MOS transistor element formation region 12 is formed. N-type diffusion layer region 1
The oxide film 24 on the substrate 8 is removed (an insulating film removing step according to the present invention). As a result, the first and second N-type diffusion layer regions 18 and 26 are exposed at the respective locations where the oxide film 24 has been removed.
Finally, as shown in FIG. 1G, the oxide film 24 is formed on the floating gate electrode 6 in one process using one mask.
The control gate electrode 30 is formed through the first and second N-type diffusion layer regions 18 and 26,
And a metal wiring layer 32 connected to the second N-type diffusion layer regions 18 and 26 is formed on the interlayer film 20 and the oxide film 24 by patterning into a required pattern (formation of a control gate electrode according to the present invention). Process). Thus, a nonvolatile memory element 34 having a double gate electrode and a MOS transistor element 36 constituting a peripheral circuit of the memory element are completed.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the control gate electrode 30 and the metal wiring layer 32 can be formed using only one mask, and the control gate electrode 30 and the metal wiring layer can be formed. The layer 32 can be formed simultaneously in one step. Therefore, the number of required masks is reduced by one, and the number of required steps is also reduced by one. As a result, the manufacturing cost can be reduced, and the time required for product development can be shortened by shortening the time required for trial production. In the present embodiment, when the second N-type diffusion layer region 26 is formed in the non-volatile memory element formation region 10 after the oxide film 24 is formed, the connection is also made in the MOS transistor element formation region 12. Since arsenic ions are implanted into the first N-type diffusion layer region 18 through the holes 22, when the metal wiring layer 32 is formed later, the contact resistance between the metal wiring layer 32 and the first N-type diffusion layer region 18 is reduced. This is advantageous in improving the performance of the MOS transistor element 36.

In this embodiment, a step of removing the interlayer film 20 in the non-volatile memory element forming region is required, but a step of masking the MOS transistor element forming region with a photoresist, which is conventionally required, is unnecessary. Therefore, the number of steps does not increase at this point ((D) in FIG. 2). Further, in the present embodiment, a step of forming oxide film 24 is required.
In forming 8, a step of forming an insulating film interposed between the floating gate electrode 108 and the floating gate electrode 108 is necessary, so that the number of steps is not increased (FIG. 2E). Therefore, since the control gate electrode 30 and the metal wiring layer 32 can be simultaneously formed in one step as described above, the number of steps is reduced by one step as a whole.

In the present embodiment, the interlayer film 20 is removed in the non-volatile memory element formation region 10,
Since the interlayer film 20 is left in the S-transistor element formation region 12, the parasitic capacitance associated with the metal wiring layer 32 does not increase, so that the performance of the MOS transistor element 36 does not deteriorate.

In this embodiment, the floating gate electrode 6 of the nonvolatile memory element 34 and the MOS transistor element 36
The gate electrode 8 is formed at the same time, but these electrodes are individually formed to optimize the thickness of each oxide film and electrode, and to optimize the electrical characteristics of the nonvolatile memory element 34 and the MOS transistor element 36, respectively. It is also possible to set a value that can be used. When the interlayer film 20 is removed in the nonvolatile memory element formation region 10, a part of the
It is also possible to remove it while remaining on the mold diffusion layer region 26. In this case, similarly to the MOS transistor element formation region 12, a connection hole may be formed in the interlayer film 20 so that the second N-type diffusion layer region 26 and the metal wiring layer 32 can be connected.

[0022]

As described above, in the method of manufacturing a semiconductor device according to the present invention, first, in the gate electrode forming step,
On a semiconductor substrate, a floating gate electrode forming a semiconductor element and a gate electrode forming a transistor element are formed close to each other via a semiconductor oxide film, and in a first impurity diffusion layer region forming step, a transistor element is formed. A first conductive type different from the semiconductor substrate is provided on the surface of the semiconductor substrate on both sides of the gate electrode.
Is formed. Then, in the interlayer film forming step, after the interlayer film is deposited on the semiconductor substrate, the interlayer film and the semiconductor oxide film around the floating gate electrode are removed, and the semiconductor oxide film and the semiconductor oxide film on the first impurity diffusion layer region are removed. A connection hole is formed in the interlayer film from the surface of the interlayer film to the first impurity diffusion layer region. Subsequently, in the insulating film forming process,
An insulating film is formed on the entire surface of the formation region of the semiconductor element and the transistor element, and the second impurity diffusion layer region forming step forms a second impurity of a conductivity type different from that of the semiconductor substrate on the surface of the semiconductor substrate on both sides of the floating gate electrode. A diffusion layer region is formed. Then, in the insulating film removing step, the insulating film is partially removed at a position above the second impurity diffusion layer region to expose the second impurity diffusion layer region, and formed in the deep portion of the connection hole. The insulating film on the first impurity diffusion layer region is removed to expose the first impurity diffusion layer region. Then, in a control gate electrode forming step, a control gate electrode is formed on the floating gate electrode via an insulating film, and the first and second control gate electrodes are formed.
A metal wiring layer connected to the first and second impurity diffusion layer regions at the exposed portion of the impurity diffusion layer region is formed on the interlayer film and the insulating film.

As described above, in the method of manufacturing a semiconductor device according to the present invention, after the interlayer film is deposited on the semiconductor substrate in the interlayer film forming step, the interlayer film around the floating gate electrode is removed to expose the floating gate electrode. Then, a control gate electrode and a metal wiring layer are simultaneously formed in a control gate electrode forming step through an insulating film forming step, a second impurity diffusion layer region forming step, and an insulating film removing step. Therefore, the control gate electrode and the metal wiring layer can be formed using only one mask, and the control gate electrode and the metal wiring layer can be formed simultaneously in one step. for that reason,
The number of required masks is reduced by one, and the number of required steps is also reduced by one.

As a result, the manufacturing cost can be reduced, and the time required for product development can be shortened by shortening the time required for trial production.

[Brief description of the drawings]

FIG. 1 is a process chart showing an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a process chart showing a method for manufacturing a conventional MOS semiconductor device in which a nonvolatile memory element having a double gate electrode and a MOS transistor element are formed close to each other.

[Explanation of symbols]

2 ... P-type silicon substrate, 4 ... Oxide film, 6 ... Floating gate electrode, 8 ... Gate electrode, 10 ... Non-volatile memory element formation area, 12 ... MOS transistor element formation area, 14 ... Semiconductor Oxide film, 16 photoresist,
18 First N-type diffusion layer region 20 Interlayer film 22
... Connection hole, 24 oxide film, 26 second N-type diffusion layer region, 28 photoresist, 30 control gate electrode, 32 metal wiring layer, 34 nonvolatile memory element , 36... MOS transistor element, 102... Silicon substrate, 104... Oxide film, 106... Non-volatile memory element forming region 108,.
... MOS transistor formation region, 112 gate electrode, 114 photoresist, 116 N-type diffusion layer, 118 control gate electrode, 120 photoresist, 122 N-type diffusion layer, 124 Interlayer film, 12
6 ... connection hole, 128 ... metal wiring layer.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-239673 (JP, A) JP-A-10-107229 (JP, A) JP-A-10-74903 (JP, A) JP-A-8-108 213489 (JP, A) JP-A-8-195359 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] 1. A method for manufacturing a semiconductor device in which a semiconductor element having a double gate electrode structure and a transistor element are formed close to each other on a semiconductor substrate, wherein the semiconductor element is formed on the semiconductor substrate via a semiconductor oxide film. Forming a floating gate electrode forming a semiconductor element and a gate electrode forming the transistor element in close proximity to each other; and forming the semiconductor substrate on the surface of the semiconductor substrate on both sides of the gate electrode of the transistor element. A first impurity diffusion layer region forming step of forming a first impurity diffusion layer region of a different conductivity type; and after depositing an interlayer film on the semiconductor substrate, the interlayer film around the floating gate electrode and The semiconductor oxide film is removed, and the semiconductor oxide film and the interlayer film on the first impurity diffusion layer region are formed on the first impurity diffusion layer region from the surface of the interlayer film. An interlayer film forming step of forming a connection hole communicating with the impurity diffusion layer region; an insulating film forming step of forming an insulating film over the entire surface of the formation region of the semiconductor element and the transistor element; and the semiconductor on both sides of the floating gate electrode A second impurity diffusion layer region forming step of forming a second impurity diffusion layer region of a conductivity type different from that of the semiconductor substrate on the substrate surface; and partially forming the insulating film above the second impurity diffusion layer region. To expose the second impurity diffusion layer region,
An insulating film removing step of removing the insulating film on the first impurity diffusion layer region formed in a deep portion of the connection hole to expose the first impurity diffusion layer region; Forming a control gate electrode with the insulating film interposed therebetween, and forming a metal wiring layer connected to the first and second impurity diffusion layer regions at the exposed portions of the first and second impurity diffusion layer regions, respectively. Forming a control gate electrode formed on the interlayer film and the insulating film. 2. The semiconductor device according to claim 1, wherein in the step of forming the second impurity diffusion layer region, an impurity is implanted by an ion implantation method to form the second impurity diffusion layer region. Method. 3. The method according to claim 1, wherein the step of forming the second impurity diffusion layer region includes the step of forming the impurity in both the floating gate electrode and the first impurity diffusion layer region at the back of the connection hole. 3. The method for manufacturing a semiconductor device according to claim 2, wherein said semiconductor device is implanted. 4. The semiconductor substrate is a P-type silicon substrate.
The first and second impurity diffusion layer regions are N-type impurities.
2. The method according to claim 1, wherein the region is an object diffusion layer region . Wherein said semiconductor substrate is a P-type silicon substrate, especially that the first and second impurity diffusion layer region is Ri N-type impurity diffusion layer regions der, the impurity is arsenic
3. The method for manufacturing a semiconductor device according to claim 2 , wherein: 6. The semiconductor device according to claim 6, wherein the semiconductor device is a non-volatile memory device.
Wherein said transistor element is said non-volatile memory element.
Constructs MOS transistor elements that constitute the peripheral circuit of the child
2. The method for manufacturing a semiconductor device according to claim 1 , wherein