JP3240743B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging apparatus for performing a pixel shifting process.

[0002]

2. Description of the Related Art In recent years, in order to obtain a clear image with higher resolution, in an image pickup apparatus having three CCDs of R, G, B, it is common to shift the pixels of the CCDs. .

[0003] A conventional imaging device will be described below. FIG. 6 shows a block diagram of this conventional imaging apparatus. In FIG. 6, 1 is a CCD, 2 is an AD converter,
3 is an offset circuit, 4 is a DD conversion circuit, and 6 is a matrix.

[0004] The operation of the imaging apparatus configured as described above will be described below. First, the optical signal is converted into an electric signal by the CCD 1 and read out at a horizontal drive frequency N (Hz) as shown in FIG. At this time, the G signal is shifted from the other signals in a direction delayed by 1/2 pixel in the horizontal direction.
As shown in (1), the first data G0 of the G signal is located between the first data R0 and the second data R1 of the R signal. However, since each signal is read at the same phase of the horizontal drive frequency N (Hz), the G signal is read 1/2 pixel earlier than the original data phase as shown in FIG. 7C. Will be. Next, the digital signal is converted into a digital signal by the AD converter 2 at the same clock as the horizontal drive frequency N (Hz) of the CCD 1. Next, the offset circuit 3
Then, as shown in FIG. 7D, the R, G, and B signals are
(Hz) data, and the G signal data is delayed by one clock from the R and B data, so that the original R,
After returning to the phases of the G and B signals, they are input to the matrix 6. In the matrix 6, the R, G, and B signals are calculated, and a luminance signal Y is generated as shown in FIG.
The Y signal obtained by the matrix is applied to the DD conversion circuit 4. As shown in FIG. 8, the DD conversion circuit 4 includes a band-limiting filter (hereinafter, referred to as LPF) 4a for limiting the band of the input signal, and a thinning circuit 4b for thinning the output signal of the LPF 4a to an arbitrary rate. It is composed of The luminance signal Y is band-limited, and FIG.
An LPF output signal L as shown in FIG. The LPF output signal L is output by the thinning circuit 4b in the DD conversion circuit.
Every other pixel is decimated and converted to data at a rate of frequency N (Hz) to obtain a transmission luminance signal YOUT.

[0005]

However, in the above-mentioned conventional configuration, in order for the offset circuit 3 to return the phases of the R, G, and B signals to the original phase, each data is set to a clock rate of 2 × N (Hz). It is necessary to perform conversion, and therefore, the matrix 6 at the next stage and the DD conversion circuit 4 must also be operated with a clock of 2 × N (Hz). Therefore, when the horizontal driving frequency N (Hz) of the CCD is high, such as in a high-definition television, it is difficult to operate the circuit with a 2 × N (Hz) clock, and the circuit scale and power consumption are large. I was

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and reduces the circuit scale and the power consumption.
It is an object of the present invention to provide an imaging apparatus capable of easily realizing a pixel shift process in a method having a high CD horizontal drive frequency.

[0007]

In order to achieve this object, an image pickup apparatus according to the present invention is provided for red (R) and blue (B).
A CCD for R, G, B in which green (G) is spatially shifted by 1/2 pixel in the horizontal direction, and A for converting the CCD output to a digital signal at the CCD horizontal drive frequency N (Hz).
The R, G, and B signals output from the D converter and the AD converter are 2 ×
Convert to a clock rate of N (Hz) and convert the G signal to 2 × N
Circuit for delaying one clock at the (Hz) rate, and R, G, B signal bands of the 2 × N (Hz) rate of the output of the offset circuit are respectively band- limited by the band-limiting filter.
After limiting the area, thinning processing is performed, and the CCD horizontal drive frequency N
(Hz) or a DD conversion circuit for converting the rate to an arbitrary clock M (Hz).

[0008]

According to the present invention, the transmission luminance signal Y is obtained in a matrix after the data rates of the R, G, and B signals phase-matched by the offset circuit are converted by the DD conversion circuit. As a result, the matrix can be operated with a clock having the same frequency as the horizontal driving frequency N (Hz) of the CCD or an arbitrary frequency M (Hz). It is possible to provide an imaging device capable of easily realizing a pixel shifting process in a high frequency system.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an image pickup apparatus according to a first embodiment of the present invention. In FIG. 1, 1
Is a CCD, which converts an optical signal into an electric signal and converts the G signal into 1
/ 2 pixels are shifted. 2 is an AD converter, CCD
1 is converted to a digital signal, 3 is an offset circuit, which adjusts the phase of the R, G, B signals of the AD converter 2 and 4 is a DD conversion circuit, which performs DD conversion on the output of the offset circuit 3. However, the LPF configuration is different from the conventional example.

The operation of the image pickup apparatus of the present embodiment configured as described above will be described below.

First, among the R, G, and B signals read from the CCD 1 at the horizontal drive frequency N (Hz) shown in FIG. 2A, the first data G0 of the G signal is shifted by a pixel. As shown in FIG. 2 (b), the first data R of the R signal
Although located between the 0th and second data R1, each signal is read at the same phase of the horizontal drive frequency N (Hz), so that the G signal is the original data as shown in FIG. Is read out by 1/2 pixel earlier than the phase of.
Next, the horizontal drive frequency N of the CCD 1 is
(Hz) and is converted into a digital signal with the same clock.
Next, in the offset circuit 3, as shown in FIG.
The G and B signals are converted to a 2 × N (Hz) rate, and the G signal is delayed by one clock, thereby returning to the original phase of the R, G and B signals. Thereafter, the LPF is added to the DD conversion circuit 4. The LPF of the DD conversion circuit 4 is different from the configuration of the conventional example, and has a configuration for the following reason.

First, the operation processing in the conventional example is the operation shown in the equation (1) in the matrix, and the operation in the LPF is Z ^-X
The arithmetic processing when the characteristic represented by the equation (2) is obtained when the delay amount is equal to X clocks will be described with reference to FIG. Y = (R + G) / 2 (1) LPF = (1 + Z ^-1 + Z ^-2 ) / 3 (2) The Y signal is represented by Expressions (3) to (9) by Expression (1). The calculated value is as follows. Y0 = undefined (3) Y1 = (R0 + G0) / 2 (4) Y2 = (R1 + G0) / 2 (5) Y3 = (R1 + G1) / 2 (6) Y4 = (R2 + G1) / 2 (7) Y5 = (R2 + G2) / 2 (8) Y6 = (R3 + G2) / 2 (9) For the LPF, the equation (2) is used. 10)-
The calculated value is shown in Expression (16). L0 = undefined (10) L1 = undefined (11) L2 = (Y2 + Y1 + Y0) / 3 (12) L3 = (Y3 + Y2 + Y1) / 3 (13) L4 = (Y4 + Y3 + Y2) / 3 (14) L5 = (Y5 + Y4 + Y3) / 3 (15) L6 = (Y6 + Y5 + Y4) / 3 (16) Next, since a thinning process is performed in the DD conversion circuit,
The output YOUT of the DD conversion circuit has the values shown in Expressions (16) to (19). YOUT1 = L1 = undetermined (17) YOUT3 = L3 = (Y3 + Y2 + Y1) / 3 (18) YOUT5 = L5 = (Y5 + Y4 + Y3) / 3 (19) Equations (18) and (19) represent equations (18) and (19). By substituting the expressions (4) to (8), it can be transformed as shown in the expressions (20) and (21). YOUT3 = ((R1 + G1) + (R1 + G0) + (R0 + G0)) / 6 = ((2 × R1 + R0) + (G1 + 2 × G0) / 6 (20) YOUT5 = ((R2 + G2) + (R2 + G1) + ( R1 + G1) / 6 = ((2 × R2 + R1) + (G2 + 2 × G1)) / 6 (21) As described above, in the conventional example, 2 × N of matrix 6 output
After performing the LPF process on the (Hz) rate luminance signal, the transmission luminance signal including the R and G signal components as shown in Expressions (20) and (21) is obtained by performing the thinning processing. ing. From Expressions (20) and (21), if the R and G signal components included in the transmission luminance signal are represented by general expressions, they can be represented as Expressions (22), (23), and (24). it can. ^{YOUT = (R (2Z 0 +} Z -1) + G (Z 0 + 2Z -1)) / 6 ··· (22) RLPF = (2Z 0 + Z -1) / 3 ··· (23) GLPF = (Z 0 + 2Z ⁻¹ ) / 3 (24) As described above, in the present embodiment, D
Since the D conversion is performed, in order to make the calculation result after the matrix processing by Expression (1) the same as that of the conventional example, LPF processing by the characteristic expression of Expression (23) is performed for the R signal, and G signal Is the LPF according to the characteristic equation (24).
It is understood that the processing should be performed.

As described above, after performing separate LPF processing for each of the R signal and the G signal, DD conversion is performed on the transmission signal rate, and thereafter, the matrix processing is performed according to the equation (1) to obtain the transmission luminance signal YOUT. obtain.

As described above, according to the present embodiment, the offset circuit 3 and the DD conversion circuit 4 are provided at the preceding stage of the matrix processing. By using the characteristic equation shown in equation (24), matrix processing can be operated with a clock of N (Hz), so that the circuit scale and power consumption can be reduced, and the horizontal drive frequency of a CCD such as a high-definition television can be reduced. It is possible to provide an imaging device capable of easily realizing a pixel shifting process in a high method.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In FIG. 3, 1 is a CCD, 2 is an AD converter, and 5 is a DD conversion circuit with an offset function. FIG.
The difference is that all the circuits are operated only by the CCD horizontal drive frequency N (Hz).

The operation of the image pickup apparatus configured as described above will be described below. First, among the R, G, and B signals read out from the CCD 1 at the horizontal drive frequency N (Hz) shown in FIG. 4A, the first data G0 of the G signal is shifted by a pixel, as shown in FIG. R)
Although the signal is located between the first data R0 and the second data R1 of the signal, each signal has the same phase of the horizontal drive frequency N.
(C), the G signal is read out 1/2 pixel earlier than the original data phase as shown in FIG. 4 (c). Next, by the AD converter 2, C
It is converted into a digital signal by the same clock as the horizontal drive frequency N (Hz) of the CD1. Each signal converted to a digital signal is input to the DD conversion circuit 5 with an offset function. As shown in FIG. 5, the DD change circuit 5 with the offset function is configured by a band limiting filter 5a, and the LPF of the R signal has the configuration shown in Expression (23), and the G signal is shown in Expression (24). And N (Hz)
Works with Here, the LPF of the R and G signals is set to N (Hz).
The meaning of operating with will be described. Equation (2) showing the transmission luminance signal obtained after the matrix processing in the first embodiment
Looking at (0), it can be seen that the operation of the R signal is an operation of the signals R1 and R0, and the operation of the G signal is also an operation of the signals G0 and G1. Here, equations (25) and (26) show the calculation results when the LPF processing shown in equations (23) and (24) is performed while keeping the R and G signals at the N (Hz) rate. ^{RLPF = (2Z 0 + Z -1} ) / 3 = (2R1 + R0) / 3 ··· (25) GLPF = (Z 0 + 2Z -1) / 3 = (G1 + 2G0) / 3 ··· (26) formula (25) , (26) is then subjected to the matrix processing shown in equation (1). The result is as shown in equation (27), which is the same as the result shown in equation (20). YOUT = (R + G) / 2 = ((2 × R1 + R0) + (G1 + 2 × G0) / 6 (27) In this manner, the equation (2) is obtained while keeping the R signal at the N (Hz) rate.
The value obtained by performing the LPF processing according to 3) and performing the matrix processing on the result of similarly performing the LPF processing according to equation (24) for G is given by equation (2) in the first embodiment.
It can be seen that it is the same as the transmission luminance signal value shown in (0).
In other words, the function of performing the offset process after converting the R and G signals into the rate of 2 × N (Hz) in the first embodiment, and the equation (23) for the R signal for each of R and G , G signal, LP in equation (24)
Replace the DD conversion function by operating the LPF of R and G at N (Hz), such as obtaining the data of N (Hz) by thinning after performing the F process at the rate of 2 x N (Hz). It can be said that. As described in the first embodiment, the transmission luminance signal YOUT obtained by performing the matrix processing is the same signal as the conventional example.

As described above, according to the present embodiment, the DD conversion circuit 5 having an offset function for matrix processing is provided.
The configuration of the LPF is expressed by the characteristic equation (23) for the R signal,
For the G signal, the characteristic equation shown in equation (24) is used, and N
By operating with a (Hz) clock, both the offset function and the DD conversion function can be realized.
As a result, all the circuits from the CCD 1 to the matrix processing can be operated with the N (Hz) clock, so that the circuit scale and power consumption can be reduced, and the CCD has a high horizontal driving frequency such as high vision. It is possible to provide an imaging device capable of easily realizing the pixel shifting process. Here, the third-order LPF has been described,
It is clear that exactly the same result can be obtained when a higher-order LPF is used.

[0019]

As described above, according to the present invention, green (G) is spatially halved horizontally with respect to red (R) and blue (B).
R, G, B CCDs shifted by pixels and CCs
An AD converter for converting the D output into a digital signal at a CCD horizontal drive frequency N (Hz);
An offset circuit that processes each of the G and B signals with a 2 × N (Hz) clock, and adjusts the phase of each signal; and a 2 × N (Hz) rate R, G, and B signal band output from the offset circuit. The band is limited by a limiting filter, and the same as the CCD horizontal drive frequency N (Hz) or an arbitrary clock M (H
z) R, G, B
By obtaining a signal, it is possible to provide an imaging device which can reduce a circuit scale and power consumption, and can easily realize a pixel shift process in a system having a high horizontal drive frequency of a CCD such as a high-definition television.

Further, by providing the DD conversion circuit with the offset function, it is possible to provide an image pickup apparatus capable of realizing the pixel shift processing only by the driving frequency N (Hz) of the CCD.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment;

FIG. 3 is a block diagram illustrating a configuration of an imaging apparatus according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment;

FIG. 5 shows a D with an offset function according to the second embodiment.
The block diagram which shows the internal structure of a D conversion circuit.

FIG. 6 is a block diagram showing a configuration of an imaging device in a conventional example.

FIG. 7 is a timing chart for explaining the operation of the conventional example.

FIG. 8 is a block diagram showing an internal configuration of a DD conversion circuit in the conventional example.

[Explanation of symbols]

 Reference Signs List 1 CCD 2 AD converter 3 Offset circuit 4 DD conversion circuit 5 DD conversion circuit with offset function 6 Matrix

Claims (2)

(57) [Claims] 1. Red (R) and blue (B), green (G)
R, G, and B CCDs, which are spatially shifted by half a pixel in the horizontal direction, and outputs the CCD output by a horizontal drive frequency N (H
an AD converter for converting the digital signal at z), of the AD converter output R, G, B signals of 2 × N (H
z) and converts the G signal to 2 × N (H
z) an offset circuit for delaying one clock at a rate, and a 2 × N (Hz) rate R,
G, each band system by the band limiting filters and B signals band
After limiting, the thinning process is performed, and the CCD horizontal drive frequency N
(Hz) or a DD conversion circuit for converting the rate to an arbitrary clock M (Hz). 2. An R / G / B signal output from an AD converter is input instead of the offset circuit and the DD conversion circuit.
Characteristics of the band limiting filter of the DD conversion circuit for each signal
Has a different characteristic from that of N and operates at N (Hz)
Equipped with DD conversion circuit with offset function with filter
The imaging device according to claim 1.