JP3239543B2 - Phase comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) for extracting a clock from a data stream, which is used for optical communication and the like.
The present invention relates to a phase comparison circuit applied to, for example, hase locked loop.

[0002]

2. Description of the Related Art Conventionally, for example, NRZ (Non Return Zer
In a PLL that extracts a clock from a data stream of o (non-return zero), an edge is extracted from the data stream by a differentiator, and this signal is input to a phase comparison circuit.

FIG. 6 is a block diagram showing a conventional clock extraction and data retiming system. In FIG. 6, D _IN is input data consisting of an NRZ data stream, D _OUT is retimed output data, CLK
_OUT indicates an output clock signal, 1 indicates a differentiator, 2 indicates a PLL circuit, 3 indicates a flip-flop, and 4 indicates a delay circuit.

A differentiator 1 has a delay section DLY and an exclusive OR gate EXOR as main components, and a PLL circuit 2 has a phase comparison circuit PD, a low-pass filter LPF, and a voltage controlled oscillator VCO (Voltage Controlled Oscillator) as main components.

In such a configuration, the input data D _IN
Is extracted by the differentiator 1, converted into a rate twice as high as the input rate, and output to the phase comparison circuit PD of the PLL circuit 2. In the phase comparison circuit PD, the phase of the input data is compared with the extracted clock signal CLK of the voltage controlled oscillator VCO, and a signal corresponding to the phase difference between the two is input to the voltage controlled oscillator VCO via the low-pass filter LPF.
The voltage controlled oscillator VCO oscillates according to the input signal level, and generates a clock signal CLK synchronized with the input data.
Is extracted. The extracted clock signal CLK is output as a clock output CLK _{OUT and} is input to a clock input terminal of the flip-flop 3.

[0006] To the D input of the flip-flop 3, input data that has been delayed by the delay circuit 4 by the delay of the differentiator 1 is input. As a result, data D _OUT retimed by the extracted clock signal CLK is output from the Q output of the flip-flop 3.

[0007]

However, in the above-mentioned conventional system, since the output of the differentiator 1 is twice as high as the input data, a high bandwidth is required for the differentiator 1 and the phase comparator PD. This limited the operating frequency of the clock extraction system.

Further, in order to retime data with the extracted clock signal CLK, a delay circuit 4 for canceling a delay in the differentiator 1 is required.

The present invention has been made in view of such circumstances, and has as its object to eliminate the need for a differentiator for extracting data edges, to enable operation at a high frequency, and to use a delay circuit. It is another object of the present invention to provide a phase comparison circuit that can realize data retiming without using a phase comparator.

[0010]

According to the present invention, there is provided a latch circuit which receives common data by using a multi-phase clock signal having a single frequency and different phases as a trigger. A mismatch detection circuit that compares data captured by one clock signal in a circuit with data captured by clock signals before and after the clock signal to detect a mismatch between a data phase and a clock signal phase.
And the above one clock signal was taken as a trigger
Data and clock signal before this one clock signal
When the data acquired by triggering
Is a clock that captures data near the edge of the data.
Judgment that the signal phase is behind the data phase
Output a signal that advances the phase of the multiphase clock signal.
And use the one clock signal as a trigger to capture
Data and the clock signal after this one clock signal.
Does not match the data acquired using the signal as a trigger
To capture data near the edge of the data.
The signal phase is determined to be ahead of the data phase.
Signal to delay the phase of the multi-phase clock signal
And a circuit for outputting the same .

In the present invention, the one clock signal is set so as to take in data near an edge of the data.

[0012]

According to the present invention, in the latch circuit, common data is taken in for each clock signal, triggered by clock signals having different phases. Then, in the mismatch detection circuit, the data captured using one clock signal as a trigger and the data captured using two clock signals before and after the clock signal as triggers are compared, and the phase of the data and the clock are compared. Is detected whether or not the phase does not match. For example, if the data captured using one basic clock signal as a trigger and the data captured using the clock signal immediately before this one clock signal as a trigger do not match, the data near the data edge It is determined that the phase of one clock signal that captures the data is behind the phase of the data. In this case, a signal that advances the phase of the clock signal is output.

On the other hand, if the data captured using one basic clock signal as a trigger and the data captured using the next clock signal after the one clock signal as a trigger do not match, It is determined that the phase of one clock signal for capturing data near the edge of the data is ahead of the phase of the data. In this case,
A signal for delaying the phase of the clock signal is output.

[0014]

FIG. 1 is a circuit diagram showing an embodiment of a phase comparison circuit according to the present invention, and FIG. 2 is a timing chart showing input / output of each part in the circuit of FIG. This embodiment shows an example of a circuit for detecting a phase difference between an 8-phase clock signal and data. In FIG. 1, 10 is a latch circuit, 20 is a mismatch detection circuit, 30 is an up / down signal generation circuit,
0 indicates an up / down signal output circuit.

The latch circuit 10 is composed of eight D-type flip-flops FF1 to FF8 arranged in parallel, and eight-phase clock signals CK having different phases from each other.
The common input data D _IN is captured by using 0 to CK7 as a trigger.

Each of the flip-flops FF1 to FF8 has a D
Input data D consisting of a data stream whose input is NRZ
_The clock signal CK, as shown in FIG. 2, connected to the common input line of _IN and each CK input is 45 ° out of phase.
0 to CK7. Specifically, the CK input of the flip-flop FF1 is connected to the input line of the clock signal CK0,
CK input of the flip-flop FF3 to the input line of the clock signal CK2, the CK input of the flip-flop FF4 to the input line of the clock signal CK3, the flip-flop F
The CK input of F5 is connected to the input line of the clock signal CK4,
The CK input of the flip-flop FF6 is the clock signal CK.
5, the CK input of the flip-flop FF7 is connected to the input line of the clock signal CK6, and the CK input of the flip-flop FF8 is connected to the input line of the clock signal CK7.

The flip-flops FF1 to FF8 convert the common input data input to the D input to a phase of 45 °.
Data is fetched using different clock signals CK0 to CK7 as triggers, and data DT0 to DT7 are output from the Q output. The timing of each of the clock signals CK0 to CK7 at this time is, as shown in FIG.
2, 4, 6 are adjusted so as to take in data near the edges of the NRZ signal, and the clock signals CK1, 3, 5, 7 are taken in near the edges.

The non-coincidence detecting circuit 20 comprises two-input exclusive NOR gates EXNOR1 to EXNOR8.
The data fetched by the odd-numbered clock signals CK1, CK3, CK5 and CK7 is compared with the data fetched by the even-numbered clock signals CK0, 2, 4, and 6 before and after each of them. Detect mismatch.

One input of the exclusive NOR gate EXNOR1 is connected to the Q output of the flip-flop FF1 of the latch circuit 10, and the other input is connected to the Q output of the flip-flop FF2.
Connected to output. Exclusive NOR gate EXNOR2
Is input to the flip-flop FF of the latch circuit 10.
2 and the other input is connected to the Q output of flip-flop FF3. Exclusive NOR gate E
One input of XNOR3 is connected to the Q output of flip-flop FF3 of latch circuit 10, and the other input is connected to the Q output of flip-flop FF4. One input of the exclusive NOR gate EXNOR4 is connected to the Q output of the flip-flop FF4 of the latch circuit 10, and the other input is connected to the Q output of the flip-flop FF5. One input of the exclusive NOR gate EXNOR5 is connected to the Q output of the flip-flop FF5 of the latch circuit 10, and the other input is connected to the Q output of the flip-flop FF6. One input of the exclusive NOR gate EXNOR6 is connected to the Q output of the flip-flop FF6 of the latch circuit 10, and the other input is connected to the Q output of the flip-flop FF7. Exclusive NOR gate EXNOR
7 is connected to the flip-flop F of the latch circuit 10.
The other input is connected to the Q output of the flip-flop FF8. One input of the exclusive NOR gate EXNOR8 is connected to the Q output of the flip-flop FF8 of the latch circuit 10, and the other input is connected to the Q output of the flip-flop FF1.

These exclusive NOR gates EXNOR1 to EXNOR8
Of two data DT0 to DT7 captured by the clock signals CK0 to CK7 as triggers, comparing two data captured by clock signals adjacent to each other to detect whether or not the two data are mismatched. Outputs the low-level mismatch signals IN0 to IN7 to the up / down signal generation circuit 30. Each exclusive NOR gate EXNO
Low-level mismatch signal IN0 output from R1 to R8
ＩＮIN7 indicates the advance or delay of the data as described below.

That is, as described above, the clock signals CK0, CK2, CK4, and CK6 are adjusted so as to take in data near the edges of the NRZ signal and the clock signals CK1, CK3, CK5, and CK7 near the edges. Figure 2
As shown in the figure, when the NRZ data is inverted near the clock signal CK1, if the clock signal CK1 is faster than the data edge, the data DT1 fetched into the flip-flop FF2 by the clock signal CK1 becomes the clock signal CK.
2, the data DT2 captured in the flip-flop FF3
Will not match. Conversely, if the clock signal CK1 is later than the data edge, the data DT1 does not match the data DT0 captured by the flip-flop FF0 with the clock signal CK0. When the NRZ data is not inverted, the data DT0, DT1, and DT2 all match. Therefore, a mismatch between the data DT1 and the data DT2 detects the advance of the clock edge with respect to the data edge, and a mismatch between the data DT1 and the data DT0 detects a delay of the clock edge with respect to the data edge. NOR gate EXNOR1 or EXNOR2
Output low level mismatch signals IN0 and IN1. Exclusive NOR gate EXNOR1 or EXNOR2
Is valid until the clock signal CK2 rises, the data DT2 is determined, and after the low-level output is determined, the clock signal CK0 rises next time.

Similarly, NRZ near the clock signal CK3
When the data is inverted, if the clock signal CK3 is faster than the data edge, the data DT3 captured by the flip-flop FF4 with the clock signal CK3 does not match the data DT4 captured by the flip-flop FF5 with the clock signal CK4. Conversely, if the clock signal CK3 is later than the data edge, the data DT3 is
Data DT taken into flip-flop FF3 by K2
No match with 2. When the NRZ data is not inverted,
Data DT2, DT3, and DT4 all match. Therefore, the mismatch between the data DT3 and the data DT4 leads the clock edge to the data edge,
3 and the data DT2 indicate that a delay of the clock edge with respect to the data edge has been detected. At these times, the exclusive NOR gate EXNOR3 or EXNOR
4 output low-level mismatch signals IN2 and IN3. Exclusive NOR gate EXNOR3 or EXNOR
The low-level output of No. 4 is valid until the clock signal CK4 rises and the data DT4 is determined and the low-level output is determined and then the clock signal CK2 rises next.

When the NRZ data is inverted near the clock signal CK5, and the clock signal CK5 is faster than the data edge, the flip-flop F is used by the clock signal CK5.
The data DT5 captured in F6 is a clock signal CK6
The data does not match with the data DT6 taken into the flip-flop FF7. Conversely, if the clock signal CK5 is later than the data edge, the data DT5 will not match the data DT4 captured by the clock signal CK4 into the flip-flop FF5. When the NRZ data is not inverted, the data D
T4, DT5, and DT6 all match. Therefore,
A mismatch between the data DT5 and the data DT6 detects the advance of the clock edge with respect to the data edge, and a mismatch between the data DT5 and the data DT4 detects a delay with respect to the clock edge, and in these cases, the exclusive NOR gate EXNOR4 Alternatively, low level mismatch signals IN4 and IN5 are output from EXNOR5. The low level output of the exclusive NOR gate EXNOR5 or EXNOR6 is valid until the clock signal CK6 rises and the data DT6 is determined, and after the low level output is determined, the clock signal CK4 next rises.

When the NRZ data is inverted near the clock signal CK7, and the clock signal CK7 is faster than the data edge, the flip-flop F is used by the clock signal CK7.
The data DT7 taken into F8 is the clock signal CK0
And the data DT0 captured by the flip-flop FF1 does not match. Conversely, if the clock signal CK7 is later than the data edge, the data DT7 does not match the data DT6 captured by the flip-flop FF7 with the clock signal CK6. When the NRZ data is not inverted, the data D
T6, DT7, and DT0 all match. Therefore,
A mismatch between the data DT7 and the data DT0 indicates that the clock edge has advanced with respect to the data edge, and a mismatch between the data DT7 and the data DT6 has detected a delay with respect to the clock edge, and in these cases, the exclusive NOR gate EXNOR6 Alternatively, the low level mismatch signals IN6 and IN7 are output from EXNOR7. The low level output of the exclusive NOR gate EXNOR7 or EXNOR8 is valid until the clock signal CK0 rises and the data DT0 is determined, and after the low level output is determined, the clock signal CK6 rises next time.

The up / down signal generating circuit 30 comprises three-input NOR gates NOR1 to NOR8, and NOR gates NOR1, NOR3, NOR5 and NOR7 are provided with up signals UP1, UP3, UP5 and UP indicating detection of delay.
7 is output to the up / down signal output circuit 40, and NOR gates NOR2, NOR4, NOR6, NOR6 are generated.
8 is a down signal DN1, DN3, DN indicating the detection of advance.
5, DN7 to generate up / down signal output circuit 40
Output to

One input of the NOR gate NOR1 is connected to the output of the exclusive NOR gate EXNOR1 of the mismatch detecting circuit 20, and the other two inputs are connected to input lines of the clock signals CK0 and CK6, respectively. That is, as shown in FIG. 2, the NOR gate NOR1 has the output of the exclusive NOR gate EXNOR1 at the low level and the clock signal C
Only during a period when both K0 and CK6 are at a low level, an up signal UP1 indicating a mismatch detection due to a clock delay is output at a high level.

One input of the NOR gate NOR2 is connected to the output of the exclusive NOR gate EXNOR2 of the mismatch detecting circuit 20, and the other two inputs are connected to input lines of the clock signals CK0 and CK6, respectively. That is, as shown in FIG. 2, the output of the exclusive NOR gate EXNOR2 is at the low level, and the NOR gate NOR2 outputs the clock signal C.
Only during a period when both K0 and CK6 are at a low level, a down signal DN1 indicating a mismatch detection due to the advance of the clock is output at a high level.

One input of the NOR gate NOR3 is connected to the output of the exclusive NOR gate EXNOR3 of the mismatch detecting circuit 20, and the other two inputs are connected to the input lines of the clock signals CK0 and CK2, respectively. That is, as shown in FIG. 2, the NOR gate NOR3 has the output of the exclusive NOR gate EXNOR3 at low level and the clock signal C
Only during a period when both K0 and CK2 are at a low level, an up signal UP3 indicating a mismatch detection due to a clock delay is output at a high level.

One input of the NOR gate NOR4 is connected to the output of the exclusive NOR gate EXNOR4 of the mismatch detecting circuit 20, and the other two inputs are connected to the input lines of the clock signals CK0 and CK2, respectively. That is, as shown in FIG. 2, the output of the exclusive NOR gate EXNOR4 is at the low level, and the NOR gate NOR4 outputs the clock signal C
Only during a period when both K0 and CK2 are at a low level, a down signal DN3 indicating a mismatch detection due to the advance of the clock is output at a high level.

One input of the NOR gate NOR5 is connected to the output of the exclusive NOR gate EXNOR5 of the mismatch detecting circuit 20, and the other two inputs are connected to input lines of the clock signals CK2 and CK4, respectively. That is, as shown in FIG. 2, the output of the exclusive NOR gate EXNOR5 is at the low level, and the NOR gate NOR5 outputs the clock signal C
Only during a period when both K2 and CK4 are at a low level, an up signal UP5 indicating a mismatch detection due to a clock delay is output at a high level.

One input of the NOR gate NOR6 is connected to the output of the exclusive NOR gate EXNOR6 of the mismatch detecting circuit 20, and the other two inputs are connected to input lines of the clock signals CK2 and CK4, respectively. That is, as shown in FIG. 2, the NOR gate NOR6 outputs the clock signal C when the output of the exclusive NOR gate EXNOR6 is at a low level.
Only during a period when both K2 and CK4 are at a low level, a down signal DN5 indicating a mismatch detection due to the advance of the clock is output at a high level.

One input of the NOR gate NOR7 is connected to the output of the exclusive NOR gate EXNOR7 of the mismatch detecting circuit 20, and the other two inputs are connected to input lines of the clock signals CK4 and CK6, respectively. That is, as shown in FIG. 2, the NOR gate NOR7 has the output of the exclusive NOR gate EXNOR7 at the low level and the clock signal CK.
4 and CK6 output an up signal UP7 at a high level indicating a mismatch detection due to a clock delay only during a low level period.

One input of NOR gate NOR8 is connected to the output of exclusive NOR gate EXNOR8 of mismatch detecting circuit 20, and the other two inputs are clock signals CK4 and CK6.
Are connected respectively to the input lines. That is, as shown in FIG. 2, the NOR gate NOR8 has the output of the exclusive NOR gate EXNOR8 at the low level and the clock signal C
Only during the period when both K4 and CK6 are at the low level, the down signal DN7 indicating the mismatch detection due to the advance of the clock is output at the high level.

FIG. 3 shows the data DT1, DT3, DT5, DT7 fetched by the odd-numbered clock signals CK1, 3, 5, 7 described above and the even-numbered clocks before and after each of them. Signals CK0,2,4,6
Data DT0 and DT2, data DT2
And DT4, data DT4 and data DT6, DT
6 and DT0 to the mismatch detection circuit 20, the up signal UP1, the down signal DN1, the up signal UP3, the down signal DN3, and the up signal UP5.
And the relationship between the output levels of the down signal DN5, the up signal UP7 and the down signal DN7.

For example, as shown in FIG. 3A, data DT0 and data DT1 are at low level "L" (or high level "H"), and data DT2 is at high level "H" (or low level "L"). In the case of), the down signal DN1 for delaying the phase of the clock signal CK is set to a high level on the assumption that the data DT1 and the data DT2 have become inconsistent with each other earlier than the data edge of the clock signal CK1. On the other hand, when the data DT0 is at the low level “L” (or high level “H”) and the data D
When T1 and data DT2 are at the high level “H” (or low level “L”), it is determined that the clock signal CK1 is later than the data edge and the data DT1 and the data DT0 become inconsistent, and the phase of the clock signal CK is Is set to a high level. When all of the data DT0, DT1, and DT2 are at the low level "L" (or the high level "H"), it is assumed that the data does not invert and all match, and the up signal UP1 and the down signal DN1 are at the low level. Is set to

Further, as shown in FIG.
T2 and data DT3 are low level "L" (or high level "H"), and data DT4 is high level "H".
(Or the low level "L"), the clock signal CK3 outputs the data DT3 and the data D
Assuming that T4 does not match the clock signal CK
Down signal DN3 for delaying the phase is set to a high level. On the other hand, when the data DT2 is at the low level “L” (or high level “H”) and the data DT3 and data DT4 are at the high level “H” (or low level “L”), the clock signal CK3 is Assuming that the data DT3 and the data DT2 have become inconsistent later than the data edge, the up signal UP3 for advancing the phase of the clock signal CK is set to a high level. When all of the data DT2, DT3, and DT4 are at the low level "L" (or the high level "H"), it is determined that the data does not invert and all match, and the up signal U
P3 and the down signal DN3 are set to low level.

As shown in FIG. 3C, the data D
T4 and data DT5 are low level "L" (or high level "H"), and data DT6 is high level "H".
(Or the low level "L"), the clock signal CK5 outputs data DT5 and data D faster than the data edge.
Assuming that T6 does not match, the clock signal CK
Down signal DN5 for delaying the phase of is set to a high level. On the other hand, when the data DT4 is at the low level “L” (or high level “H”) and the data DT5 and DT6 are at the high level “H” (or low level “L”), the clock signal CK5 is Assuming that the data DT5 and the data DT4 have become inconsistent later than the data edge, the up signal UP5 for advancing the phase of the clock signal CK is set to a high level. When all of the data DT4, DT5 and DT6 are at the low level "L" (or the high level "H"), it is determined that the data is not inverted and all the data coincide, and the up signal U
P5 and the down signal DN5 are set to low level.

Further, as shown in FIG.
T6 and data DT7 are low level "L" (or high level "H"), and data DT0 is high level "H".
(Or the low level “L”), the clock signal CK7 outputs the data DT7 and the data D
Assuming that T0 does not match, the clock signal C
The down signal DN7 for delaying the phase of K is set to a high level. On the other hand, when the data DT6 is low level “L” (or high level “H”) and the data DT7
If the data DT0 is at the high level “H” (or low level “L”), it is determined that the clock signal CK7 is later than the data edge and the data DT7 and the data DT6 are not coincident, and the phase of the clock signal CK is changed. The up signal UP7 for proceeding is set to a high level.
If all of the data DT6, DT7 and DT0 are at the low level "L" (or the high level "H"), the data is not inverted and all of the data DT6, DT7 and DT0 match and the up signal UP7 and the down signal DN7 are at the low level. Is set to

The up / down signal output circuit 40 is composed of four input OR gates OR1 and OR2, and receives the output of the up / down signal generation circuit 30,
Up signal UP for advancing the phase of clock signal CK
Alternatively, a down signal DN for delaying the phase of the clock signal CK is output.

The four inputs of the OR gate OR1 are the NOR gates NOR1, NOR3, NOR3 of the up / down signal generation circuit 30.
The NOR gates NOR5, NOR3, NOR5, NOR5, NOR5, NOR5, NOR5, NOR5, NOR5, NOR5, NOR7, NOR5, NOR5, NOR5, NOR5, NOR7, NOR7, NOR5, NOR5, NOR7, and NOR7 output signals UP1, UP3, UP5, and UP7.

The four inputs of the OR gate OR2 are the NOR gates NOR2, NOR4 and NOR4 of the up / down signal generation circuit 30.
The outputs of the NOR gates NOR2, NOR4, NOR6 and NOR8 are connected to the outputs of NOR6 and NOR8, respectively, and the logical sum of the output signals DN2, DN4, DN6 and DN8 of the NOR gates NOR2 and NOR4 is output as a down signal DN.

The up signal UP and the down signal DN output from the up / down signal output circuit 40 are
For example, it is used to control a voltage controlled oscillator VCO via a charge pump and a loop filter.

As the voltage controlled oscillator VCO, for example, as shown in FIG.
ST4 is connected in a ring to form a ring oscillator,
One that directly outputs eight-phase clocks CK0 to CK7,
As shown in FIG. 5, an eight-phase clock signal CK0 to CK7 is obtained after a voltage controlled oscillator VCO using frequency dividers DV1 to DV4 each including a flip-flop having an output of the voltage controlled oscillator VCO as a clock input. Is adopted. When an up signal UP is output from the up / down signal output circuit 40, the voltage controlled oscillator VCO uses an eight-phase clock signal C by a control system (not shown).
The phases of K0 to CK7 are advanced together, and the down signal DN
Is output, the eight-phase clock signals CK0 to CK
K7 is delayed in phase.

The eight-phase clock signals CK0 to CK7 obtained as described above are input to the CK inputs of the flip-flops FF1 to FF8 of the latch circuit 10, whereby the clock signals CK1, 3, 5, 7 Is always NR
Locked near the edge of Z data, clock signal CK
0, 2, 4, and 6 correctly convert NRZ data to DT0, 2,
Can be imported to 4,8.

Next, the operation of the above configuration will be described. N
The RZ signal is input in parallel to the D inputs of the flip-flops FF1 to FF8 of the latch circuit 10 as input data D _IN . Clock signals CK0 having phases different by 45 ° are applied to CK inputs of the flip-flops FF1 to FF8, respectively.
To CK7 are input. As a result, in each of the flip-flops FF1 to FF8, data is taken in in response to the input of the clock signals CK0 to CK7, and the data DT0 to DT7 are output from the Q output to the mismatch detection circuit 20, respectively. It should be noted that the fetching of data in each of the flip-flops FF1 to FF8 is performed by the flip-flops FF1 and FF8.
The FF3, FF5, and FF7 take in the edge of the NRZ signal and the data at the center of the edge, and the flip-flops FF2, FF4, FF6, and FF8 take in the data near the edge of the NRZ signal.

For example, when the NRZ data is inverted near the rising edge of the clock signal CK1, if the clock signal CK1 is faster than the data edge, the clock signal C
Data DT taken into flip-flop FF2 by K1
1 is inconsistent with the data DT2 fetched into the flip-flop FF3 by the clock signal CK2, this is detected by the exclusive NOR gate EXNOR2 of the inconsistency detection circuit 20, and the low-level inconsistency signal IN1 is output to the up / down signal generation circuit 30. Is done.

The low-level mismatch signal IN1 input to the up / down signal generation circuit 30 is supplied to the NOR gate NOR.
2 is input. In the NOR gate NOR2, a pulse-shaped high-level down signal DN1 indicating mismatch detection due to advance is generated and output to the up / down signal output circuit 40 only when both the clock signals CK0 and CK6 are at the low level. In the up / down signal output circuit 40, the input high level down signal DN1 is output as the down signal DN via the OR gate OR2.

The down signal DN output from the up / down signal output circuit 40 is used to control the voltage controlled oscillator VCO via, for example, a charge pump and a loop filter. The phases of CK0 to CK7 are all delayed and the CK of each flip-flop FF1 to FF8 of the latch circuit 10 is delayed.
Entered in the input.

On the other hand, when the clock signal CK1 is NR
If it is later than the data edge of the Z signal, the data DT1
Becomes inconsistent with the data DT0 taken into the flip-flop FF0 by the clock signal CK0, this is detected by the exclusive NOR gate EXNOR1 of the mismatch detection circuit 20, and the low-level mismatch signal IN0 is output to the up / down signal generation circuit 30. .

The low-level mismatch signal IN0 input to the up / down signal generation circuit 30 is supplied to the NOR gate NOR.
1 is input. The NOR gate NOR1 generates a pulse-shaped high-level up signal UP1 indicating detection of a mismatch due to delay only during a period in which both the clock signals CK0 and CK6 are at a low level, and outputs the generated signal to the up / down signal output circuit 40. In the up / down signal output circuit 40, the input high level up signal UP1 is output as the up signal UP via the OR gate OR1.

The up signal DN output from the up / down signal output circuit 40 is used to control the voltage controlled oscillator VCO via, for example, a charge pump and a loop filter, and an eight-phase clock signal is supplied by a control system (not shown). The phases of CK0 to CK7 are made uniform and the CK of each flip-flop FF1 to FF8 of the latch circuit 10 is shifted.
Entered in the input.

As described above, the clock signals CK1,
3, 5, and 7 are always locked near the edges of the NRZ data, and the clock signals CK0, 2, 4, and 6 can correctly capture the NRZ data into DT0, 2, 4, and 8.

As described above, according to the present embodiment,
The input data D _IN common to the flip-flops FF1 to FF8 of the latch circuit 10 is received by using the clock signals CK0 to CK7 having phases different by 45 ° as triggers, and the exclusive NOR gates EXNOR1 to EXN0 of the mismatch detection circuit 20 are taken.
Clock signal CK to which an odd-numbered code is assigned by XNOR8
Since the data fetched at 1, 3, 5, and 7 are compared with the data fetched at clock signals CK0, CK, CK, CK0, CK2, and CK4 which have even numbers before and after each data, a mismatch between them is detected. Since there is no need to use a differentiator for extracting an edge as in the related art, a signal having a higher rate than data is not generated. Therefore, operation at a high frequency can be realized without being limited by the output of the differentiator. Further, the clock synchronized with the data using the phase comparison circuit can take in the data without adjustment, and the delay circuit becomes unnecessary. Furthermore, since it has a serial / parallel conversion function in its configuration, it is advantageous for data processing such as high-speed optical communication. In addition, if there is a multi-phase clock whose phase difference is managed, there is an advantage that a phase difference with a high-rate input signal can be detected with a low-frequency clock, which is suitable for a large-scale integrated circuit PLL.

In this embodiment, an eight-phase clock is used. However, the present invention is not limited to this, and it goes without saying that the present invention can be applied to clocks having a number of phases other than eight. The mismatch signal IN1 from the mismatch detection circuit 20
The timing of gating to IN8 can be changed, and a latch may be applied instead of applying a gate. Further, the voltage-controlled oscillator VCO can be controlled by adding a large number of mismatch detection results to analog.

[0055]

As described above, according to the present invention,
Since a differentiator for extracting data edges is not required, a signal having a higher rate than input data does not occur. Therefore, without being limited by the output of the differentiator,
Operation at a high frequency can be realized. Further, the clock synchronized with the data using the phase comparison circuit can take in the data without adjustment, and the delay circuit becomes unnecessary. Furthermore, if there is a multi-phase clock whose phase difference is managed, there is an advantage that a phase difference with a high-rate input signal can be detected with a low-frequency clock, which is suitable for a large-scale integrated circuit PLL.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a phase comparison circuit according to the present invention.

FIG. 2 is a timing chart showing input and output of each unit in the circuit of FIG.

FIG. 3 is a diagram illustrating input levels to a mismatch detection circuit of data captured by a clock signal with an odd number sign and data captured by a clock signal with an even number sign before and after each of them, and an up signal and a corresponding level; This shows the relationship with the output level of the down signal.
FIG. 4B is a diagram showing the relationship between the input levels of the mismatch detection circuits T0, DT1, and DT2 to the output levels of the up signal UP1 and the down signal DN1, and FIG.
DT4 input level to mismatch detection circuit and up signal U
FIG. 7C is a diagram showing the relationship between P3 and the output level of the down signal DN3, and FIG. 7C is a diagram showing the relationship between the input levels of the data DT4, DT5, and DT6 to the mismatch detection circuit and the output levels of the up signal UP5 and the down signal DN5. And (d) shows the relationship between the input levels of the data DT6, DT7, and DT0 to the mismatch detection circuit and the output levels of the up signal UP7 and the down signal DN7.

FIG. 4 is a diagram illustrating an example of a circuit that generates an eight-phase clock signal.

FIG. 5 is a diagram illustrating another example of a circuit that generates an eight-phase clock signal.

FIG. 6 is a configuration diagram showing a conventional clock extraction and data retiming system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Latch circuit FF1-FF8 ... Flip-flop 20 ... Mismatch detection circuit XENOR1-EXNOR8 ... Exclusive NOR gate 30 ... Up / down signal generation circuit NOR1-NOR8-NOR gate 40 ... Up / down signal output circuit OR1, OR2 ... OR gate

Continuation of front page (56) References JP-A-2-17038 (JP, A) JP-A-3-151737 (JP, A) JP-A-4-79632 (JP, A) JP-A-3-204251 (JP) JP-A-3-117129 (JP, A) JP-A-3-53629 (JP, A) JP-A-58-202680 (JP, A) JP-A-1-296734 (JP, A) 3-58546 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/085 H03K 5/26 H04L 7/02

Claims (2)

(57) [Claims] 1. A latch circuit for taking in common data triggered by multi-phase clock signals having one frequency and different phases from each other; A mismatch detection circuit for comparing the phase of the data with the phase of the clock signal by comparing the phase of the clock signal with the level of the data captured by the clock signal;
Clock signal and the clock signal before this one clock signal.
If there is a discrepancy with the data captured as Riga,
One clock signal that captures data near the data edge
Signal phase lags the data phase
Output a signal that advances the phase of the polyphase clock signal
And the above one clock signal was used as a trigger.
Data and one clock signal after this one clock signal
When the data acquired by triggering
Is a clock that captures data near the edge of the data.
Judgment that the signal phase is ahead of the data phase
Then, a signal that delays the phase of the multiphase clock signal is
Position phase comparator circuit having a circuit for outputting. 2. The phase comparison circuit according to claim 1, wherein said one clock signal is set to take in data near an edge of the data.