JP3236758B2 - CRC arithmetic unit for variable length data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRC arithmetic unit used for error detection when decoding compressed audio or the like using a high-efficiency code decoding system conforming to the MPEG standard. To shorten the processing speed of the entire decoding system.

[Prior art]

Recently, high-efficiency coding of moving images and voices for the purpose of application to large-capacity media has been attempted.
As an international standard, MPEG (Mov
ing Picture Experts Grou
p) method, which is described in detail in "Standards for Multimedia Coding" (edited by Hiroshi Yasuda, published by Maruzen Co., Ltd.).

[0002] A compressed audio system using a high-efficiency code decoding system of the MPEG standard (hereinafter referred to as MPEG-Audio).
Will be described. MPEG-Audio is a technique for compressing audio data to about 1/6 by combining various methods such as a masking effect and a minimum audible limit, instead of simply recording audio.

[0003] The masking effect is such that a small sound adjacent to a large sound in a frequency band is masked and cannot be heard. In addition, the minimum audible limit is that the sound cannot be recognized unless the sound is above a certain level, and the level differs depending on the frequency range. By deleting these inaudible portions of data, high-quality, high-level compression is possible, and such standards are defined by international standard audio compression technology (ISO-11172-).
3). However, in order to perform compression by the above method, it is necessary to handle data not only with time but also for each frequency, and a large amount of calculation is required at the time of compression and decompression. Therefore, specialized hardware is required for decoding in real time.

FIG. 2 is a block diagram of a general MPEG-Audio decoder. Decoders are roughly divided,
A bit separation unit for reading the configuration information of the compressed data,
It is composed of three blocks: an inverse quantization unit that performs inverse quantization from the compressed data, and a band synthesis unit that performs band synthesis from the inversely quantized data.

[0005] The bit separation unit performs a process called bit separation. More specifically, various kinds of information used at the time of dequantization and band synthesis, such as extraction of sample data from the data sent to the head of the compressed data, such as header information of information relating to audio sampling and sample data Bit Alloc to know the number of bits
SCFSI (Scale Factor) indicating the storage state of the application information and the Scale Factor information described later.
rSelect Information), Scale Facto indicating the volume when the sample data is reproduced
An operation for recognizing the r information is performed. Then, the CRC (Cyc
Like Redundancy Check) expected value is sent. The target of CRC is Header
Part of the information, BitAllocation information, S
This is information that affects reading of subsequent data such as CFSI information. In addition, the presence or absence of the CRC check can be selected, and the selection is performed by the Header section.

[0006] Next, the inverse quantization unit performs the Bit Alloc
The sample data is read based on the ation information, and the volume is calculated by the Scale Factor, and the calculation is performed for each of the 32 bands.

Finally, the processing in the band synthesizing section will be described. FIG. 3 is a diagram showing an example in which the inverse quantizer uses the calculated value of 32 and the previous 1024 samples to calculate the last 32 PCM sample data on the time axis.
9 is a calculation flowchart when performing band synthesis according to the SO recommendation. As shown in the figure, after inputting 32 sub-band data, V is generated by shifting the values up to the previous time (step 1). Then, ROM for data Vi
A matrix operation of the coefficients Nik and S is performed to calculate Vi (step 2). Further, U itself is operated to calculate U (step 3), and U is multiplied by a coefficient D to calculate Wi (step 4). Finally, perform Wi matrix operation,
Finally, calculation of 32 PCM data is performed (step 5).

As described above, when performing decoding processing in real time in the MPEG-Audio decoder, the processing speed of the entire system is a major problem. That is, in MPEG-Audio, data is processed in units of frames, so that in order to decode data sampled at 44.1 kHz specified in the standard in real time, the processing time per frame is about 26 ms. Only a very short time is acceptable. In the decoding process of MPEG-Audio, the band synthesis process is mainly composed of matrix operations.
The number of calculation processes is very large. However, this part is an essential part, and it is very difficult to shorten the processing. Therefore, it is realistic to increase the speed in the steps corresponding to the pre-processing such as the bit separation unit and the dequantization unit up to this stage.

In general, when considering these processing speed-up techniques, it is conceivable to change the processing order, parallelize the processing, or reduce the processing. However, when the processing content is determined by a recommendation such as MPEG, it is considered that a method of increasing the speed by parallelizing the processing is easy and effective. Therefore, the present invention provides a CRC in the bit separation unit.
MPEG-A
It is an object of the present invention to achieve real-time decoding of audio.

FIG. 4 is a diagram showing an example of a conventional CRC calculator. The CRC arithmetic unit is a method of sequentially inputting data in a so-called bit-by-bit manner, and includes 16 shift registers and three arithmetic units. When the input bit D is input, data is stored in R0. The data stored in R0 is shifted to R1. Similarly, the data of R1 is operated on D and shifted to R2, and the shift operation is sequentially performed in the same manner.

FIGS. 5 to 12 are diagrams showing the state of operation at each step when 8-bit data is sequentially input, and FIG. 4 shows the state at the start of operation. B15 to B in the figure
It is assumed that up to 0 represents the value stored in each register. Each of the logical operations 1 to 3 represents an XOR (exclusive OR). (In this specification, a logical operation is described as +)

FIG. 5 is a diagram showing the state at the time when the most significant bit of the D7 and CRC target data is input and the operation is completed. First, data is input and logical operation 1 (B15 + D
7 is calculated as A) is calculated. The result is the register R
0 is stored. The register R2 performs a logical operation on the value B1 held in the register R1 and the operation result A (to be B1 + A), and holds the result in the register R2.
Similarly, the register R15 performs a logical operation on the operation result A with the value B14 held by the register R14 (B14 +
A), the result is held in the register R15. Registers other than the above simply perform a shift operation and hold a value. When the calculation is performed in the same procedure, FIGS.
become that way. That is, bit data is sequentially input after all the shift registers are initialized with 1 as an initial state, and the values of all the shift registers when the final bit data is input represent a CRC value to be obtained.

[0013]

However, in the above method, the input must be performed on a bit-by-bit basis, which is a great limitation in processing. That is, MPEG-A
In the recommendation of audio, when performing the CRC operation, it is recommended that the operation be performed in such a manner that data is sequentially input for each bit, and the processing requires at least the number of steps corresponding to the bit length of the input data. . For example, when a CRC operation is performed using 256-bit input data, a process such as 256 steps is inevitably required. As a result, the processing load on the CRC protection information in the entire system is increased, and this is an obstacle particularly when decoding is performed in real time.

Therefore, in the present invention, the input is made parallel and the input data is made variable. The data to be subjected to the CRC calculation is Bit Allocation, SC
The bit length of such data is 8 bits in the header information section, and BitAllocation.
The part is either 4, 3, or 2 bits, and the SCFSI part is 2b
It. In other words, even when inputting in parallel,
If it is possible to determine and process the input of 8, 4, 3, or 2 bits, the CRC calculation can be performed while reading out the data.

That is, according to the present invention, even if data to be subjected to the CRC operation processing has various data lengths, the data is input in parallel and the processing is performed, thereby shortening the CRC operation time and reducing the entire system. It is an object of the present invention to improve processing efficiency and achieve real-time decoding processing and system miniaturization.

[0016]

Means for Solving the Problems The present invention is an apparatus for CRC calculation variable length data having various data length to be consecutively inputted, the output of the later result selection processing means is a previous calculation result And the value held in the register and the data input this time are stored in all kinds of bits.
And arithmetic processing to preparative length, and arithmetic processing means for outputting the respective bit values of the CRC in the respective bit length of the variable length data,
Each bit value output from the arithmetic processing means according to the bit length of the variable length data , or the value held in the register
And a comparison processing means for comparing the output of the register with a preset CRC expected value and outputting the result. Device.

[0017]

According to the present invention, the input of data to the CRC calculator is 1
While inputting multiple bits simultaneously instead of bit by bit,
Since the valid data to be input is not a fixed data length,
The currently input data length is identified, the internal processing is changed according to the data length, and the CRC calculation process is performed in one step for any data length.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a CRC operation device according to the present invention. As shown in the figure, the CRC operation device includes an operation processing unit 101, a result selection processing unit 102, a register 1
03, comprising the comparison processing means 104. In this embodiment, it is assumed that data of each effective bit length of 8, 4, 3, and 2 up to 8 bits is input.

The CRC arithmetic unit shown in FIG . 1 has input data having effective bit lengths of 2, 3, 4, and 8, and control signals of OEs 2, 3, 4, and 8 representing the effective bit length of the input data.
This is a device that performs an operation based on the input of the reset signal and the expected CRC value and outputs whether or not the CRC is correct. It is assumed that valid data is always input from the most significant bit as input data. The arithmetic processing means 101 performs an arithmetic operation without performing a shift operation on the three logical arithmetic operations shown in FIG. 4 which is a conventional CRC arithmetic unit, and outputs the result. It outputs a value corresponding to each bit of the bit length. FIG. 13 shows the results of the CRC operation shown in FIGS. 5 to 12 sequentially extracted up to eight steps, and FIG. 14 shows the first three steps extracted and expanded.

FIG. 15 is a logic circuit diagram of FIG. In the figure, Dn is the input data of each bit, Bn is the contents of the register at the start of each bit, Cn
aln_Stepn is a logical operation 1 in each step,
Represents a few outputs. As shown in these figures, the results of the logical operations 1, 2, and 3 are all determined by the register values at the start and the input values. Therefore, by using the gate circuit as shown in FIG. 15, the operations of steps 1 to 8 of each of the logical operations 1, 2, and 3 are performed, and combinations after the operations for three places and eight steps are created. In addition, since this creation can be performed by simple gating, an operation result is obtained immediately after input.

The result selection processing means 102 is the arithmetic processing means 1
The output value to the register is determined based on the operation result from 01 and the contents of the register as the previous operation result and the states of the OEs 2, 3, 4, 8, and the reset signal. That is, in the above-mentioned arithmetic processing means, the value corresponding to each bit of all kinds of bit lengths of the input data, which is the data once calculated up to eight steps, and the previous arithmetic result,
A valid bit value is selected and output by a control signal.

FIG. 16 shows two-step processing corresponding to the bit lengths of 2, 3, 4, and 8, FIG. 6, three-step processing, FIG. 7, four-step processing, and FIG. The values to be selected are tabulated based on FIG. 12, and OE2, OE3, OE4, OE8, no selection, R
It shows the output value of each register at the time of eset. If a reset signal has been input,
As a reset operation, all signal outputs are set to '1'. If neither signal is input, the current state is maintained, that is, the current register value is output. The result selection processing means 102 includes OE2, 3,
In order to output the values shown in FIG. 16 according to the signals 4, 8, and RESET, a selector circuit or the like can be specifically used.

Further, the register performs an operation of holding the value of the result selection processing means 102 for each cycle. Further, the comparison processing means 104 performs a logical operation as to whether or not the value obtained as a result of the arithmetic processing and held in the register matches the input CRC expected value, and outputs the result. And can be realized by a comparator circuit or the like.

The output value corresponding to the bit length of the arithmetic processing means 101 when data is input will be described below. Here, as input data, 4-bit data of “1010” from the upper bit in binary is input,
As the initial state of the register,
It is assumed that “0011001101010101” is set.

First, FIG. 17 shows a state in which a conventional shift operation is performed in a table format. When calculating sequentially from the lower bits of the register in the same procedure as in FIG.
R0 is 0 or 1, and the operation result is 1. R1 shifts the value to 1, R2 shifts the value to 1 and 0, and the result is 1. Thereafter, the shift operation is simply performed up to R14, R15 is 0 and 1, and the operation result is 1. 1
The operation result for the input of the bit is “1110011010101111” in order from the upper bit. Hereinafter, the value finally obtained by performing the calculation in the same procedure, that is, the calculation result of the CRC is “001101010”.
1100110 ".

Next, a description will be given below of a case where an operation using the present invention is performed. The finally obtained CRC values are R15 to R0, and the register values at the start of the calculation are B15 to B15.
0, input data D7 to D0. However, since the input data is 4 bits, it is assumed that the input data is input in order from the upper bit D7. A, B, C and D in the formulas are shown in FIGS.

Since the input data this time is 4 bits, the control signal of OE4 is valid.
The calculation is performed based on the state of. First, the calculation of the most significant bit of R15 is D + B11, and this expression is expanded as follows.

[0028]

(Equation 1)

R15 finally obtained from the above equation is 0
Becomes Next, R14 to R6 will be obtained. From FIG. 16, this part simply selects the held value of the register, so that the following equation is obtained.

[0030]

(Equation 2)

Next, R5 will be obtained from FIG. R5 is B1 + A as shown in the drawing.

[0032]

(Equation 3)

From the above equation, the final value of R5 is 1.
Similarly, R4 is obtained from FIG. R4 is B0 from FIG.
+ B, and this expression is expanded as follows.

[0034]

(Equation 4)

From the above equation, R4 = 0. Next, FIG.
R3 is determined from the equation. R3 is A + C from FIG. 16, and the expression is similarly expanded as follows.

[0036]

(Equation 5)

R3 finally obtained from the above equation is 0.
Becomes Similarly, from FIG. 16, R2 is B + D.

[0038]

(Equation 6)

The final R2 obtained from the above equation is 1
Becomes Similarly, R1 is C from FIG.
When the formula is expanded and calculated, it is as follows.

[0040]

(Equation 7)

From the above equation, R1 is 1. Finally R0
Is obtained from FIG. R0 is D in FIG. 16 and is as follows.

[0042]

(Equation 8)

From the above equation, the final R0 is 0. As a result of the above, the CRC value finally obtained is “0011010101100110”, which is the same value as the CRC value obtained when performing the conventional shift operation.

[0044]

According to the present invention, by inputting input data in parallel and performing arithmetic processing according to the bit length of the input data, it is possible to dramatically reduce the number of arithmetic steps conventionally required. By using this device, M
The processing of the entire PEG-Audio decoding system can be improved, which is extremely useful when performing real-time processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a CRC calculation device according to the present invention.

FIG. 2 is a block diagram illustrating a general MPEG-Audio decoder.

FIG. 3 is a flowchart showing a calculation when performing band synthesis according to the ISO recommendation.

FIG. 4 is an explanatory diagram showing a conventional CRC calculator.

FIG. 5 is an explanatory diagram showing an operation of a conventional CRC calculator.

FIG. 6 is an explanatory diagram showing the operation of a conventional CRC calculator.

FIG. 7 is an explanatory diagram showing an operation of a conventional CRC calculator.

FIG. 8 is an explanatory diagram showing the operation of a conventional CRC calculator.

FIG. 9 is an explanatory diagram showing an operation of a conventional CRC calculator.

FIG. 10 is an explanatory diagram showing the operation of a conventional CRC calculator.

FIG. 11 is an explanatory diagram showing the operation of a conventional CRC calculator.

FIG. 12 is an explanatory diagram showing the operation of a conventional CRC calculator.

13 is a diagram table showing a part of a CRC calculation result.

14 is a diagram table showing a part of a CRC calculation result.

FIG. 15 is a logic circuit diagram illustrating a part of a logic circuit that performs a CRC operation process.

16 is a diagram table showing a part of a CRC calculation result.

17 is a diagram table showing a part of a CRC calculation result.

[Explanation of symbols]

 101 arithmetic processing means 102 result selection processing means 103 register 104 comparison processing means

Claims (1)

(57) [Claims] 1. It has various data lengths inputted continuously.
The variable length data to a device for the CRC calculation, the last
Which is the operation result register for holding an output of the later result selection processing means, and a data input this time and the value held in the register and arithmetic processing for the bit length of all types,
And arithmetic processing means for outputting the respective bit values of the CRC in the respective bit length of the variable-length data, each bit value output from the processing means in accordance with the bit length of the variable-length data, there have
Is characterized by comprising: result selection processing means for selecting and outputting a value held in a register; and comparison processing means for comparing the output of the register with a preset CRC expected value and outputting the result. CRC operation device for variable-length data.