JP3235452B2 - High frequency integrated circuit device - Google Patents
High frequency integrated circuit deviceInfo
- Publication number
- JP3235452B2 JP3235452B2 JP06236896A JP6236896A JP3235452B2 JP 3235452 B2 JP3235452 B2 JP 3235452B2 JP 06236896 A JP06236896 A JP 06236896A JP 6236896 A JP6236896 A JP 6236896A JP 3235452 B2 JP3235452 B2 JP 3235452B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- integrated circuit
- frequency integrated
- multilayer substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、移動体通信などの
無線システムに用いられる高周波集積回路装置に関す
る。The present invention relates to the Ru <br/> relates to a high-frequency integrated circuit equipment used for wireless systems such as mobile communications.
【０００２】[0002]
【従来の技術】近年、携帯電話、自動車電話等の移動体
通信システムにおいては、小型でしかも低コストの電子
回路部品が強く要望されている。その中にあって従来、
主に実用に供されている高周波集積回路装置は単層の基
板の上にパッケージに封じられた半導体デバイスとチッ
プコンデンサ等のチップ部品が搭載された構成をとって
おり、さらに放熱板や、リード電極を装着したものとな
っている。しかしながら、このような構成においてはす
べての回路素子を単層の基板の表面に実装しており、大
きな基板面積が必要であるために大型化していた。ま
た、構造が複雑化しているためにコスト低減も困難にな
っていた。一方、昨今では主にセラミックを用いた多層
基板上に半導体チップを直接ボンディングし、かつ、チ
ップコンデンサ等のチップ部品を実装した形態の高周波
集積回路装置が登場し、その集積度の高さと高周波特性
の良さ、及び様々な機能を搭載可能な適応性の高さから
注目を集めている。しかしながら、このような多層基板
を用いた構造においても基板に搭載する部品が半導体チ
ップとチップコンデンサ等のチップ部品が共に基板の単
一の平面に搭載されているために実装工程が複雑化した
り、半田材の選択が困難になるといった問題があった。
また熱抵抗が低減できず、大電力用の回路を構成した場
合、放熱性が不足するといった問題が生じていた。2. Description of the Related Art In recent years, there has been a strong demand for small and low-cost electronic circuit components in mobile communication systems such as mobile phones and car phones. Conventionally in that,
High-frequency integrated circuit devices that are mainly used in practical applications have a configuration in which a semiconductor device enclosed in a package and chip components such as a chip capacitor are mounted on a single-layer substrate. It is equipped with electrodes. However, in such a configuration, all circuit elements are mounted on the surface of a single-layer substrate, and a large substrate area is required, resulting in an increase in size. In addition, cost reduction has been difficult due to the complicated structure. On the other hand, recently, a high-frequency integrated circuit device in which a semiconductor chip is directly bonded on a multilayer substrate mainly made of ceramic and chip components such as a chip capacitor are mounted has appeared. It has attracted attention because of its goodness and high adaptability that can be equipped with various functions. However, even in such a structure using a multilayer substrate, the mounting process becomes complicated because the components mounted on the substrate are both mounted on a single plane of the substrate, such as a semiconductor chip and a chip component such as a chip capacitor. There is a problem that it is difficult to select a solder material.
In addition, when the heat resistance cannot be reduced and a circuit for high power is configured, there has been a problem that heat dissipation is insufficient.
【０００３】以下、従来の第一の高周波集積回路装置の
例を図８を用いて説明する。図８において１はトランジ
スタ等の半導体チップ、２２は高周波整合回路、２４は
封止された半導体デバイス、２５は単層基板、２６は放
熱板、２７は電極リード、２８は半導体デバイス搭載
穴、２９はバイアス回路である。半導体チップ１は基板
上にダイスボンドされ、半導体チップと内部電極リード
とがワイヤーボンドで接続され、さらにパッケージ内に
封止されて半導体デバイス２４を構成している。この半
導体デバイス２４はバイアス回路２９及び高周波整合回
路２２を有する通常アルミナ（酸化アルミニウム）もし
くは樹脂でできた単層基板２５上に搭載されている。単
層基板２５の下には金属製のシールド板を兼ねる放熱板
２６が半田付けされており、半導体チップ１から発生し
た熱を放熱板２６を通してその下に半田付けされる実装
回路基板（図示せず）に放熱する。単層基板２５は比較
的熱伝導率の良いアルミナを用いても、約１８Ｗ／ｍＫ
の小さい熱伝導率しか有しないため、放熱を良くするた
めに基板を薄くする必要があった。このため多層基板化
することができず、回路要素を平面的にしか配置できな
かった。これが回路が大型化する原因になっていた。ま
た、さらに良好な放熱が必要な場合には、単層基板２５
に半導体デバイス搭載穴２８をあけて半導体デバイス２
４と放熱板２６が直接接触する構成にする必要があり、
コストアップの原因になっていた。また、電極リード２
７は単層基板２５からリードを引き出して構成してお
り、大型化するとともに実装面積が拡大していた。Hereinafter, an example of a first conventional high-frequency integrated circuit device will be described with reference to FIG. In FIG. 8, 1 is a semiconductor chip such as a transistor, 22 is a high-frequency matching circuit, 24 is a sealed semiconductor device, 25 is a single-layer substrate, 26 is a heat sink, 27 is an electrode lead, 28 is a semiconductor device mounting hole, 29 Is a bias circuit. The semiconductor chip 1 is die-bonded on a substrate, the semiconductor chip and internal electrode leads are connected by wire bonding, and further sealed in a package to form a semiconductor device 24. The semiconductor device 24 is mounted on a single-layer substrate 25 having a bias circuit 29 and a high-frequency matching circuit 22 and usually made of alumina (aluminum oxide) or resin. A radiator plate 26 also serving as a metal shield plate is soldered below the single-layer substrate 25, and the heat generated from the semiconductor chip 1 is soldered therebelow through the radiator plate 26 (not shown). Heat is dissipated. Even if the single-layer substrate 25 is made of alumina having a relatively good thermal conductivity, it is about 18 W / mK.
Therefore, it is necessary to make the substrate thin in order to improve heat radiation. For this reason, it was not possible to form a multilayer substrate, and circuit elements could only be arranged in a planar manner. This has caused the circuit to become large. In the case where better heat radiation is required, the single-layer substrate 25 may be used.
A semiconductor device mounting hole 28 in the semiconductor device 2
4 and the heat radiating plate 26 need to be in direct contact,
This was causing an increase in cost. In addition, electrode lead 2
Reference numeral 7 denotes a configuration in which leads are drawn out from the single-layer substrate 25, and the size is increased and the mounting area is increased.
【０００４】次に、従来の第二の高周波集積回路装置の
例を図９を用いて説明する。図９において１はトランジ
スタ等の半導体チップ、２はセラミック多層基板、３は
抵抗用コンデンサ等のチップ部品、４は端面電極、５は
高融点半田材、６は低融点半田材、７はポッティング樹
脂、８はボンディングワイヤーである。Next, an example of a second conventional high-frequency integrated circuit device will be described with reference to FIG. In FIG. 9, 1 is a semiconductor chip such as a transistor, 2 is a ceramic multilayer substrate, 3 is a chip component such as a resistor capacitor, 4 is an end face electrode, 5 is a high melting point solder material, 6 is a low melting point solder material, 7 is a potting resin. , 8 are bonding wires.
【０００５】図９の構造の高周波集積回路装置の製造方
法は、半導体チップ１を高融点半田材５にてセラミック
多層基板２上にダイスボンドし、その後半導体チップ１
とセラミック多層基板２の表面に形成された電極配線層
とをワイヤーでボンドを行い、ポッティング樹脂７を半
導体チップ１およびボンディングワイヤー８上に塗布
し、次に、低融点半田材６であるクリーム半田を半田マ
スクを用いて表面に選択的に塗布後、チップ部品３をマ
ウントして半田をリフローして完成させるという工程を
とる。In the method of manufacturing a high-frequency integrated circuit device having the structure shown in FIG. 9, a semiconductor chip 1 is die-bonded on a ceramic multilayer substrate 2 with a high-melting point solder material 5, and then the semiconductor chip 1
And the electrode wiring layer formed on the surface of the ceramic multilayer substrate 2 are bonded by wires, a potting resin 7 is applied on the semiconductor chip 1 and the bonding wires 8, and then a low melting point solder material 6, cream solder Is selectively applied to the surface using a solder mask, and then the chip component 3 is mounted, and the solder is reflowed to complete the process.
【０００６】このクリーム半田の塗布工程を図１０を用
いて説明する。９は半田マスク、１０はスキージ、１１
はエンボス部である。図１０に示すように低融点半田材
６であるクリーム半田は半田マスク９に設けられた穴に
スキージ１０で掃引されることにより充填され、半田マ
スク９を取り外すことにより所定の半田付けが必要なポ
イントに塗布されることになる。この半田マスク９は、
ボンディングされている半導体チップ１とボンディング
ワイヤー８とを塗布したポッティング樹脂を避けるため
にエンボス部１１が設けられている。このエンボス部１
１の周辺にはスキージ１０によるクリーム半田の塗布が
不可能であるためにエンボス部１１から離れたところに
しかチップ部品３が実装できないので実装密度が低いと
いう問題点があった。The process of applying the cream solder will be described with reference to FIG. 9 is a solder mask, 10 is a squeegee, 11
Is an embossed part. As shown in FIG. 10, cream solder, which is a low melting point solder material 6, is filled by being swept by a squeegee 10 into a hole provided in the solder mask 9, and a predetermined soldering is required by removing the solder mask 9. It will be applied to the point. This solder mask 9
An embossed portion 11 is provided to avoid a potting resin applied with the bonded semiconductor chip 1 and the bonding wire 8. This embossed part 1
In the vicinity of 1, there is a problem in that the application of cream solder by the squeegee 10 is not possible and the chip component 3 can be mounted only at a position away from the embossed portion 11, so that the mounting density is low.
【０００７】また、半導体チップ１から発生した熱はす
べてのセラミック多層基板２を通して下部に伝熱される
ため基板が厚いので熱抵抗が高く、大電力を消費する半
導体チップ１は高温状態になってしまうという問題点が
あった。Further, the heat generated from the semiconductor chip 1 is transferred to the lower portion through all the ceramic multilayer substrates 2 and thus the substrate is thick, so that the thermal resistance is high and the semiconductor chip 1 consuming a large amount of power is in a high temperature state. There was a problem.
【０００８】また、当該高周波集積回路装置が表面実装
部品として機器の基板に実装される際の半田付けのため
のリフロー工程により、低融点半田材６が溶けてチップ
部品が移動し、高周波特性が変化するという問題点があ
った。In addition, when the high-frequency integrated circuit device is mounted as a surface-mounted component on a substrate of a device, a reflow process for soldering melts the low-melting-point solder material 6 and moves the chip component. There was a problem of change.
【０００９】また、ドレインバイアス回路として用いら
れるフィルター回路は良好な特性を得るために低抵抗で
ある必要があるが、セラミック基板上の配線導体の抵抗
率は１０ｍΩ／□程度であるため、太い配線パターンで
形成すると、実装密度を低下させるという問題点があっ
た。A filter circuit used as a drain bias circuit needs to have low resistance in order to obtain good characteristics. However, since the resistivity of a wiring conductor on a ceramic substrate is about 10 mΩ / □, a thick wiring is required. When formed in a pattern, there is a problem that the mounting density is reduced.
【００１０】また、通常、高周波集積回路装置はシール
ドケースを用いる必要があるが、これが製造工程を複雑
にするという問題点があった。[0010] In general, a high frequency integrated circuit device needs to use a shield case, which has a problem that the manufacturing process is complicated.
【００１１】[0011]
【発明が解決しようとする課題】従来の第一の構成の高
周波集積回路装置では、実装密度が低く大型化してい
た。また構造が複雑で製造工程数が多くコストアップに
なっていた。また、従来の第二の構成の高周波集積回路
装置では、製造工程が複雑であると同時に実装密度が低
い。また熱抵抗が高く大電力用の集積回路の実現が困難
であった。また、高周波集積回路装置を実装する機器に
半田付けのリフローによる実装が困難であった。また、
製造工程の簡素化が困難であった。In the conventional high frequency integrated circuit device having the first configuration, the mounting density is low and the size is increased. In addition, the structure is complicated, the number of manufacturing steps is large, and the cost is increased. In the conventional high frequency integrated circuit device having the second configuration, the manufacturing process is complicated and the mounting density is low. Further, it has been difficult to realize an integrated circuit for high power because of its high thermal resistance. Further, it has been difficult to mount the high frequency integrated circuit device on a device on which the high frequency integrated circuit device is mounted by reflow soldering. Also,
It was difficult to simplify the manufacturing process.
【００１２】本発明は上記従来の問題点を解決するもの
で、製造工程が容易で実装密度が高く、熱抵抗が低く、
半田付けリフローによる機器基板への実装が容易で、製
造工程を簡素化できる高周波集積回路装置を提供するも
のである。The present invention solves the above-mentioned conventional problems. The manufacturing process is easy, the mounting density is high, the thermal resistance is low,
Easily mounted to the device substrate by soldering reflow, there is provided a high-frequency integrated circuit equipment that the manufacturing process can be simplified.
【００１３】[0013]
【課題を解決するための手段】この目的を達成するため
に本発明の高周波集積回路装置は下記のものである。To achieve this object, a high-frequency integrated circuit device according to the present invention is as follows.
【００１４】（１）表面に凹部を有し、表層と内層に回
路配線層が形成された多層基板を用い、その凹部中に半
導体チップを搭載するとともに多層基板の表面上にチッ
プ部品を搭載する。（２）多層基板の材料としてアルミ
ナもしくは窒化アルミニウムのセラミックを用いる。
（３）多層基板の材料として多結晶酸化フェニレン（Ｐ
ｏｌｙ−Ｐｈｅｎｙｌｅｎｅ Ｏｘｉｄｅ：ＰＰＣ）を
用いる。（４）半導体チップが搭載されたＰＰＣ基板に
貫通孔を設ける。（５）半導体チップが搭載された基板
に高温焼成のセラミックを他の基板に低温焼成のガラス
セラミックを用いる。（６）表層または内層に８００Ｍ
Hz以上の周波数で動作するフィルター回路もしくは高周
波整合回路を有する。（７）多層基板の表面に２段階形
状の凹部を設け、半導体チップが凹部底面に搭載され、
半導体チップと凹部中間面に設けられた回路配線層とが
ワイヤーでボンドされる。（８）半導体チップが凹部を
有する多層基板の凹部底面にフリップチップボンディン
グされている。（９）凹部の底面に配置された半導体チ
ップと回路配線層がワイヤーでボンディングされ、ワイ
ヤー高さの最高部が多層基板の最外表面より下側にあ
る。（１０）半導体チップ上に樹脂系の材料によりポッ
ティングされている。（１１）多層基板の表面上の配線
層のうち、半田付けを行うランド部分と、配線層の長さ
調整により、高周波の整合調整を行うマイクロストリッ
プライン部分以外の部分およびチップ部品に樹脂系もし
くはガラス系のコート材が塗布されている。（１２）セ
ラミック多層基板の表面上に実装したチップ部品の上に
樹脂系もしくはガラス系材料により厚く保護コートが行
なわれ表面が平坦化されている。（１３）さらにその保
護コート材の上に金属膜が塗布されている。（１４）凹
部裏面に放熱用電極を有する。（１５）ドレインバイア
ス用フィルターまたはコレクタバイアス用フィルターの
ストリップラインの幅が２００μｍ以上の幅の広い配線
パターンとして内層もしくは表層に設けられる。（１
６）セラミック多層基板に設けた凹部が実装する機器基
板面と対向する面側に設けて、凹部の深さと同じ厚みの
半導体チップが同凹部にフリップチップボンディングさ
れているものである。(1) A multilayer substrate having a concave portion on the surface and a circuit wiring layer formed on the surface layer and the inner layer is used, and a semiconductor chip is mounted in the concave portion and a chip component is mounted on the surface of the multilayer substrate. . (2) A ceramic of alumina or aluminum nitride is used as a material of the multilayer substrate.
(3) Polycrystalline phenylene oxide (P
(Oly-Phenylene Oxide: PPC) is used. (4) A through hole is provided in a PPC board on which a semiconductor chip is mounted. (5) A high-temperature fired ceramic is used for a substrate on which a semiconductor chip is mounted, and a low-temperature fired glass ceramic is used for another substrate. (6) 800M for surface or inner layer
It has a filter circuit or a high-frequency matching circuit that operates at a frequency higher than Hz. (7) A two-stage recess is provided on the surface of the multilayer substrate, and the semiconductor chip is mounted on the bottom of the recess.
The semiconductor chip and the circuit wiring layer provided on the intermediate surface of the concave portion are bonded by wires. (8) The semiconductor chip is flip-chip bonded to the bottom surface of the concave portion of the multilayer substrate having the concave portion. (9) The semiconductor chip and the circuit wiring layer disposed on the bottom surface of the concave portion are bonded by wires, and the highest part of the wire height is below the outermost surface of the multilayer substrate. (10) Potted with a resin material on the semiconductor chip. (11) Of the wiring layer on the surface of the multilayer substrate, a resin part or a chip part other than a land part where soldering is performed and a part other than a microstrip line part where high frequency matching adjustment is performed by adjusting the length of the wiring layer. A glass coating material is applied. (12) The chip component mounted on the surface of the ceramic multilayer substrate is thickly coated with a resin or glass material to provide a protective coating, and the surface is planarized. (13) Further, a metal film is applied on the protective coating material. (14) A heat radiation electrode is provided on the back surface of the concave portion. (15) The strip line of the drain bias filter or the collector bias filter is provided on the inner layer or the surface layer as a wide wiring pattern having a width of 200 μm or more. (1
6) A semiconductor chip having the same thickness as the depth of the concave portion is provided on the surface of the ceramic multilayer substrate opposite to the surface of the device substrate on which the concave portion is mounted, and is flip-chip bonded to the concave portion.
【００１５】また、本発明の高周波集積回路装置の製造
方法は下記のものである。（１７）凹部に半導体チップ
を２１５℃以上の融点の半田材にてダイスボンドし、ワ
イヤーボンドを行なった後、前記半田材以下の融点を持
つクリーム半田でチップ部品をマウントして半田付けを
行う。（１８）クリーム半田を用いてチップ部品をマウ
ントして半田付けを行なった後に、凹部に半導体チップ
を窒化ホウ素もしくは銀を含む樹脂系のペーストを用い
てダイスボンドし、ワイヤーボンディングを行う。The method of manufacturing the high-frequency integrated circuit device according to the present invention is as follows. (17) A semiconductor chip is die-bonded to the concave portion with a solder material having a melting point of 215 ° C. or more, wire-bonded, and then the chip component is mounted with cream solder having a melting point of the solder material or less, and soldering is performed. . (18) After mounting the chip component using cream solder and performing soldering, the semiconductor chip is die-bonded to the concave portion using a resin-based paste containing boron nitride or silver, and wire bonding is performed.
【００１６】[0016]
【発明の実施の形態】本発明の請求項１に記載の発明
は、表層と内層とからなる多層基板と、電界効果トラン
ジスタと、ドレインバイアス回路と、高周波整合回路
と、ゲートバアス回路と、を備えた高周波集積回路装置
であって、前記多層基板は、表面に凹部を有し、該凹部
中には前記電界効果トランジスタからなる半導体チップ
が搭載され、かつ、前記凹部以外の部分の前記表層には
前記整合回路をなすマイクロストリップラインとチップ
部品とが搭載されており、前記ドレインバイアス回路に
用いるフィルタ回路は、前記多層基板の前記内層に設け
られ、かつ、２００μｍ以上の幅を有する配線パターン
からなり、これにより高周波集積回路装置を立体的な回
路構成にすることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a multi-layer substrate having a surface layer and an inner layer, and a field effect transistor.
Distister, drain bias circuit and high frequency matching circuit
-Frequency integrated circuit device provided with a gate bias circuit
Wherein the multilayer substrate has a concave portion on the surface, and the concave portion
Inside the semiconductor chip comprising the field effect transistor
Is mounted, and on the surface layer other than the concave portion is
Microstrip line and chip forming the matching circuit
Components are mounted on the drain bias circuit.
The filter circuit to be used is provided in the inner layer of the multilayer substrate.
Wiring pattern having a width of 200 μm or more
Made, This ensures that the high-frequency integrated circuit device can be a three-dimensional circuit structure.
【００１７】[0017]
【００１８】[0018]
【００１９】以下に、本発明における高周波集積回路装
置の実施の形態について、図面を参照しながら説明す
る。An embodiment of a high-frequency integrated circuit device according to the present invention will be described below with reference to the drawings.
【００２０】（実施の形態１） 図１は本発明の第一の実施の形態における高周波集積回
路装置の断面図である。また、図２は同じく本発明の第
一の実施の形態における高周波集積回路装置の等価回路
の概略図である。Embodiment 1 FIG. 1 is a sectional view of a high-frequency integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of an equivalent circuit of the high-frequency integrated circuit device according to the first embodiment of the present invention.
【００２１】図１において、１はトランジスタ等の半導
体チップ、２は表層および内層に回路配線層が形成され
たセラミック多層基板、３はチップコンデンサ等のチッ
プ部品、４は端面電極、５は高融点半田材、６は低融点
半田材、７はポッティング樹脂、８はボンディングワイ
ヤー、１２は凹部、１３は凹部底面、１４は２段階の凹
部に設けられた凹部中間面、１５は放熱用電極、１６は
保護コート材、１７は金属ケースである。また、図２に
おいて、２０は電界効果トランジスタ（ＦＥＴ）、２１
はドレインバイアス回路、２２は高周波整合回路、２３
はゲートバイアス回路である。図１に示された半導体チ
ップ１は図２に示されたＦＥＴ２０に対応し、ここでは
ガリウム砒素半導体チップを用いている。半導体チップ
１は、凹部底面１３に高融点半田材５によってボンディ
ングされており、かつ凹部中間面１４に設けられた回路
配線層のワイヤーボンディングパッドとの間でワイヤー
ボンディングされている。ドレインバイアス回路２１
（またはバイポーラトランジスタの吸着とはコレクタバ
イアス回路）に用いるフィルター回路はセラミック多層
基板２の表層もしくは内層に設けられているため、２０
０μｍ以上の幅を有する太い配線パターンとすることが
でき、実装密度を向上しながら配線幅を広げられる。こ
れにより配線抵抗はおよそ０．４Ω以下にできる。また
ドレインバイアス回路２１は高周波用フィルターとして
の役割を果たすように設計されているが、そのフィルタ
ーとしての特性は伝搬する高周波の波長に対する伝送線
路の長さで決まっている。例えば、伝送線路長を基本周
波数の波長の１／４にし、終端を高周波的に短絡する
と、基本周波数に対するインピーダンスは無限大である
一方で、２倍の周波数に対してはショート状態のインピ
ーダンスをもつ。したがって、このようなフィルターを
構成する場合、基本波の波長を低く設定すると伝送線路
長が長くなり、大型化するため実装密度が低下する。実
際、比誘電率１０のアルミナ基板を使用する場合には８
００ＭHzに対する１／４波長の伝送線路長は約３０mmと
なり、伝送線路幅を２００μｍ以上確保しながら、か
つ、集積回路の体積を０．５cc以下にすることを想定す
ると、基本周波数はこの８００ＭHzがほぼ下限となる。
このとき同時にフィルターとしての損失を１ｄＢ以下の
低損失に抑えることができる。セラミック多層基板２の
表層にはマイクロストリップライン（特性インピーダン
スに整合された配線層）とチップ部品３からなる高周波
整合回路２２が設けられている。ボンディングワイヤー
８の最高部はセラミック多層基板２の表面よりも十分下
にあり、かつ、半導体チップ１とボンディングワイヤー
８全体をも包含するポッティング樹脂７もセラミック多
層基板２の表面よりも下にある構造になっていて表面を
平坦化させている。この構造ゆえにチップ部品３を半田
付けする低融点半田材６であるクリーム半田は平坦な半
田マスクを用いて塗布することができ、その結果、半導
体チップ１の近傍にもチップ部品３を搭載することがで
き、実装密度が向上することによって高周波集積回路の
外形を小さくすることが可能となっている。この結果、
高周波集積回路装置の容積は、従来の単層の基板を用い
た場合０．４ccであったものが、０．２cc以下にでき、
１／２以下の体積にすることができた。さらにチップ部
品が装着されたセラミック多層基板２の表層（ただし半
田付け用ランド部分と整合調整用マイクロストリップラ
インの部分以外を除く。）およびポッティング樹脂７で
充填された凹部表面に保護コート材１６が形成されてい
る。また、凹部底面１３となるセラミックの多層基板２
の裏面に放熱用電極１５が形成されている。In FIG. 1, 1 is a semiconductor chip such as a transistor, 2 is a ceramic multilayer substrate having a circuit wiring layer formed on a surface layer and an inner layer, 3 is a chip component such as a chip capacitor, 4 is an end face electrode, and 5 is a high melting point. Solder material, 6 is a low melting point solder material, 7 is a potting resin, 8 is a bonding wire, 12 is a concave portion, 13 is a concave bottom surface, 14 is a concave intermediate surface provided in a two-step concave portion, 15 is a radiation electrode, 16 Is a protective coating material and 17 is a metal case. In FIG. 2, reference numeral 20 denotes a field effect transistor (FET);
Is a drain bias circuit, 22 is a high frequency matching circuit, 23
Is a gate bias circuit. The semiconductor chip 1 shown in FIG. 1 corresponds to the FET 20 shown in FIG. 2, and here uses a gallium arsenide semiconductor chip. The semiconductor chip 1 is bonded to the bottom surface 13 of the concave portion with the high melting point solder material 5 and wire-bonded to a wire bonding pad of a circuit wiring layer provided on the intermediate surface 14 of the concave portion. Drain bias circuit 21
Since the filter circuit used for (or the adsorption of the bipolar transistor is a collector bias circuit) is provided on the surface layer or inner layer of the ceramic multilayer substrate 2,
A thick wiring pattern having a width of 0 μm or more can be provided, and the wiring width can be increased while increasing the mounting density. As a result, the wiring resistance can be reduced to about 0.4Ω or less. The drain bias circuit 21 is designed to play a role as a high-frequency filter, and the characteristics of the filter are determined by the length of the transmission line with respect to the wavelength of the transmitted high-frequency. For example, if the transmission line length is set to 1/4 of the wavelength of the fundamental frequency and the terminal is short-circuited at a high frequency, the impedance for the fundamental frequency is infinite while the impedance for the double frequency has a short-circuited impedance. . Therefore, when configuring such a filter, if the wavelength of the fundamental wave is set low, the length of the transmission line becomes long, and the size of the filter is increased, so that the mounting density is reduced. Actually, when an alumina substrate having a relative dielectric constant of 10 is used, 8
The transmission line length of a quarter wavelength with respect to 00 MHz is about 30 mm. Assuming that the transmission line width is 200 μm or more and the volume of the integrated circuit is 0.5 cc or less, the fundamental frequency is almost 800 MHz. It is the lower limit.
At this time, the loss as a filter can be suppressed to a low loss of 1 dB or less. A high frequency matching circuit 22 including a microstrip line (a wiring layer matched to a characteristic impedance) and a chip component 3 is provided on a surface layer of the ceramic multilayer substrate 2. A structure in which the highest part of the bonding wire 8 is sufficiently below the surface of the ceramic multilayer substrate 2, and the potting resin 7 including the entire semiconductor chip 1 and the bonding wire 8 is also below the surface of the ceramic multilayer substrate 2. And the surface is flattened. Because of this structure, the cream solder, which is the low melting point solder material 6 for soldering the chip component 3, can be applied using a flat solder mask. As a result, the chip component 3 can be mounted near the semiconductor chip 1. As a result, the outer shape of the high-frequency integrated circuit can be reduced by improving the mounting density. As a result,
The volume of the high-frequency integrated circuit device can be reduced from 0.4 cc when a conventional single-layer substrate is used to 0.2 cc or less,
The volume could be reduced to ２ or less. Further, a protective coating material 16 is provided on the surface layer of the ceramic multilayer substrate 2 on which the chip components are mounted (except for the portions other than the soldering land portion and the alignment adjustment microstrip line) and the concave surface filled with the potting resin 7. Is formed. The ceramic multilayer substrate 2 serving as the concave bottom surface 13
The heat radiation electrode 15 is formed on the back surface of the substrate.
【００２２】次に、本発明の第一の実施の形態における
構造を得るその製造工程を説明する。まず２１５℃以上
の融点を有する半田材によって半導体チップ１をセラミ
ック多層基板２に設けられた凹部１２の底面１３にダイ
スボンドする。なお、セラミック多層基板２の表層と内
層には回路配線層が形成され、セラミック多層基板２の
凹部１２が形成されている面とは反対面にメッキにより
放熱用電極１５が形成されている。ダイスボンドに適し
た金錫系の半田材においてその融点の最低点がおよそ２
１５℃近傍にあるものを用いる。次に、半導体チップ１
と凹部中間面１４に形成された配線層との間にワイヤー
８でボンドを行ない、続いてポッティング樹脂７を用い
て半導体チップ１を封止する。そして、２１５℃以下の
融点を有する低融点半田材６をスクリーン印刷し、チッ
プ部品３をマウントしたのち、低融点半田材６をリフロ
ーしてチップ部品３を固定する。さらに表面に保護コー
ト材１６を塗布し、金属ケース１７のキャップをつける
という工程をとっている。このような工程をとることに
より、ワイヤーボンディング時の温度を２００℃近辺ま
で上昇でき、超音波を加えなくとも良好なワイヤーの引
っ張り強度を得ることができるとともに、１００μｍ以
下程度のワイヤーボンドのピッチが実現できる。Next, the manufacturing process for obtaining the structure according to the first embodiment of the present invention will be described. First, the semiconductor chip 1 is die-bonded to the bottom surface 13 of the concave portion 12 provided in the ceramic multilayer substrate 2 with a solder material having a melting point of 215 ° C. or more. In addition, a circuit wiring layer is formed on the surface layer and the inner layer of the ceramic multilayer substrate 2, and a heat radiation electrode 15 is formed by plating on a surface of the ceramic multilayer substrate 2 opposite to a surface on which the concave portion 12 is formed. The lowest point of the melting point of gold-tin based solder material suitable for die bonding is about 2
Use a material near 15 ° C. Next, the semiconductor chip 1
Bonding is performed between the wiring layer and the wiring layer formed on the recess intermediate surface 14 with a wire 8, and then the semiconductor chip 1 is sealed with a potting resin 7. Then, the low-melting point solder material 6 having a melting point of 215 ° C. or less is screen-printed, the chip component 3 is mounted, and the low-melting point solder material 6 is reflowed to fix the chip component 3. Further, a step of applying a protective coating material 16 on the surface and attaching a cap of the metal case 17 is employed. By taking such a step, the temperature at the time of wire bonding can be raised to around 200 ° C., and a good wire tensile strength can be obtained without applying ultrasonic waves, and the wire bond pitch of about 100 μm or less can be obtained. realizable.
【００２３】一方、以下のような本発明の第一の実施の
形態の構造を得る第二の製造工程も可能である。それ
は、まず、表層と内層に配線層が形成され、凹部１２が
形成されている面とは反対面にメッキにより放熱用電極
１５が形成されたセラミック多層基板２を用意する。次
に、低融点半田材６のクリーム半田をセラミック多層基
板２の表面にスクリーン印刷し、チップ部品３をマウン
トしたのち、低融点半田材６をリフローして、チップ部
品３を固定する。次に、半導体チップ１を２．５×１０
-3ｃａｌ／ｃｍ・ｓｅｃ・℃以上の熱伝導率を有する窒
化ホウ素もしくは銀を含む樹脂系のペーストを用いて凹
部底面１３にダイスボンドし、半導体チップ１と凹部中
間面１４に形成された配線層との間にワイヤーでボンド
する。さらにポッティング樹脂７を用いて半導体チップ
１を封止し、保護コート材１６を塗布し、金属ケース１
７のキャップをつけるというものである。なお半導体チ
ップ１とセラミック多層基板２の間のペースト材厚を５
μｍ以下とすることにより、５００ｍＷクラス以上のパ
ワーアンプに適用できる低熱抵抗を実現できる。このよ
うな第二の製造工程によれば、半導体チップ１に与える
熱的ストレスを最小にすることができる。On the other hand, a second manufacturing process for obtaining the following structure of the first embodiment of the present invention is also possible. First, a ceramic multilayer substrate 2 is prepared in which a wiring layer is formed on a surface layer and an inner layer, and a heat radiation electrode 15 is formed by plating on a surface opposite to a surface on which the concave portion 12 is formed. Next, cream solder of the low melting point solder material 6 is screen-printed on the surface of the ceramic multilayer substrate 2 to mount the chip component 3, and then the low melting point solder material 6 is reflowed to fix the chip component 3. Next, the semiconductor chip 1 is
A wiring layer formed on the semiconductor chip 1 and the recess intermediate surface 14 by die-bonding to the recess bottom surface 13 using a resin-based paste containing boron nitride or silver having a thermal conductivity of -3 cal / cm · sec · ° C. or more. Bond with the wire. Further, the semiconductor chip 1 is sealed using a potting resin 7, a protective coating material 16 is applied, and the metal case 1 is sealed.
It is to attach the cap of 7. The thickness of the paste material between the semiconductor chip 1 and the ceramic multilayer substrate 2 is 5
By setting the thickness to μm or less, a low thermal resistance applicable to a power amplifier of 500 mW class or more can be realized. According to such a second manufacturing process, the thermal stress applied to the semiconductor chip 1 can be minimized.
【００２４】高周波集積回路装置の第一の実施の形態に
おいては凹部底面１３に半導体チップ１がダイスボンド
されていることにより、本発明によるハイブリッド高周
波集積回路装置が機器の基板に実装された場合、半導体
チップ１と機器の基板の間に存在するセラミック多層基
板２の厚さが薄くなるため層厚減少分だけ熱抵抗が低下
し、良好な放熱性を確保することができる。図１におい
ては凹部底面１３下のセラミック多層基板２の層厚はセ
ラミック多層基板２の全体厚の１／４になっており、セ
ラミック多層基板２の熱抵抗も１／４に低減でき、５０
０ｍＷ以上の大消費電力の電力増幅回路を形成できる。
また、図１では、半導体チップ１の直下に位置するセラ
ミック多層基板２の裏面に放熱用電極１５が構成されて
おり、かつこの放熱用電極１５が半田付けが容易なよう
に半田メッキ等のメッキが施されているため、半導体チ
ップ１より発生した熱を良好に実装する機器の基板に放
熱することができる。また、セラミック多層基板２の材
料をアルミナとしたが、窒化アルミニウムとすることに
より、窒化アルミニウムの良好な１５０ｍＷ／ｍＫとい
うアルミナの約９倍の熱伝導率により、セラミック多層
基板２の熱抵抗を１／９にすることができ、大電力デバ
イスにも対応可能となる。In the first embodiment of the high-frequency integrated circuit device, since the semiconductor chip 1 is die-bonded to the bottom surface 13 of the concave portion, when the hybrid high-frequency integrated circuit device according to the present invention is mounted on a substrate of a device, Since the thickness of the ceramic multilayer substrate 2 existing between the semiconductor chip 1 and the substrate of the device is reduced, the thermal resistance is reduced by the reduced layer thickness, and good heat dissipation can be secured. In FIG. 1, the thickness of the ceramic multilayer substrate 2 below the concave bottom surface 13 is 1/4 of the total thickness of the ceramic multilayer substrate 2, and the thermal resistance of the ceramic multilayer substrate 2 can be reduced to 1/4.
A power amplifier circuit with a large power consumption of 0 mW or more can be formed.
In FIG. 1, a heat radiation electrode 15 is formed on the back surface of the ceramic multilayer substrate 2 located directly below the semiconductor chip 1, and the heat radiation electrode 15 is plated by solder plating or the like so that soldering is easy. Is applied, the heat generated from the semiconductor chip 1 can be radiated to the board of the device to be mounted favorably. Although alumina was used as the material of the ceramic multilayer substrate 2, the thermal resistance of the ceramic multilayer substrate 2 was reduced to 1 by using aluminum nitride, which has a favorable thermal conductivity of 150 mW / mK, which is about 9 times that of alumina. / 9, which makes it possible to cope with high power devices.
【００２５】次に、セラミック多層基板２の表面に半田
付けされたチップ部品３上には樹脂系材料またはガラス
系材料により保護コートがなされている。これは高周波
損失の少ない材料によってなされているため損失が少な
くなるとともに、コーティングされているため当該ハイ
ブリッド高周波集積回路装置を実装する機器の基板への
半田付けリフロー時にいったん半田付けしたチップ部品
３の半田が溶けて位置ずれを起こし高周波特性が変化す
ることを避けることができる。このため機器の基板への
半田付けリフロー条件を比較的広い範囲で選択すること
ができる。そして、このセラミック多層基板２には、パ
ッケージとなる金属ケース１７が付けられて、電波遮蔽
の実用に供される。Next, the chip component 3 soldered to the surface of the ceramic multilayer substrate 2 is provided with a protective coating with a resin-based material or a glass-based material. This is made of a material having a low high-frequency loss, so that the loss is reduced. In addition, since the coating is coated, the solder of the chip component 3 once soldered at the time of reflow soldering to a substrate of a device mounting the hybrid high-frequency integrated circuit device is performed. Can be prevented from melting and displacing to change the high frequency characteristics. For this reason, the reflow condition for soldering the device to the substrate can be selected within a relatively wide range. The ceramic multilayer substrate 2 is provided with a metal case 17 serving as a package, and is used for practical use of radio wave shielding.
【００２６】（実施の形態２） 次に、本発明の高周波集積回路装置の第二の実施の形態
について図３に示した断面図を参照して説明する。(Embodiment 2) Next, a second embodiment of the high-frequency integrated circuit device of the present invention will be described with reference to the sectional view shown in FIG.
【００２７】図３において図１に示した第一の実施の形
態と異なる点は、多層基板として高周波に対して伝送損
失が少ない多結晶酸化フェニレン（ＰＰＯ）基板２ａを
用いていることである。ただしＰＰＯ基板２ａはセラミ
ック基板に比べて熱伝導率が低いため、半導体チップ１
が装着された基板に熱伝導体で充填された貫通孔３１が
設けられている。これによりＰＰＯ基板による放熱効果
を高め、高出力パワーアンプ等への適用を可能にしてい
る。FIG. 3 differs from the first embodiment shown in FIG. 1 in that a polycrystalline phenylene oxide (PPO) substrate 2a having a small transmission loss at high frequencies is used as a multilayer substrate. However, since the thermal conductivity of the PPO substrate 2a is lower than that of the ceramic substrate, the semiconductor chip 1
Is provided with a through-hole 31 filled with a heat conductor. This enhances the heat radiation effect of the PPO substrate and enables application to a high-output power amplifier and the like.
【００２８】なお、半導体チップ１はパッケージかまた
はチップキャリア等にマウントされている場合もある。The semiconductor chip 1 may be mounted on a package or a chip carrier.
【００２９】（実施の形態３） 次に、本発明の高周波集積回路装置の第三の実施の形態
について図４に示した断面図を参照して説明する。Embodiment 3 Next, a third embodiment of the high-frequency integrated circuit device of the present invention will be described with reference to the cross-sectional view shown in FIG.
【００３０】図４において図１に示した第一の実施の形
態と異なる点は、多層基板として、半導体チップ１が搭
載されている層の基板に酸化アルミニウムもしくは窒化
アルミニウム等の高温焼成のセラミック基板２ｂを用
い、他の層の基板に低温焼成のガラスセラミック基板２
ｃを用いていることである。これにより半導体チップか
らの放熱性を確保するとともに安価なガラスセラミック
を用いることでコストの低減を図ることができる。FIG. 4 is different from the first embodiment shown in FIG. 1 in that a high-temperature fired ceramic substrate such as aluminum oxide or aluminum nitride is used as a multilayer substrate on a substrate on which a semiconductor chip 1 is mounted. 2b, a low temperature fired glass ceramic substrate 2
c is used. Thus, heat dissipation from the semiconductor chip can be secured, and the cost can be reduced by using inexpensive glass ceramic.
【００３１】（実施の形態４） 次に本発明の高周波集積回路装置の第四の実施の形態に
ついて図面を参照しながら説明する。図５は本発明の第
四の実施の形態における高周波集積回路装置の断面図で
ある。図５において１８は金属塗布膜である。この構造
の特徴は、保護コート材１６を０．５mm以上に厚く形成
して表面が平坦化され、その上に金属塗布膜１８が形成
されていることである。この金属塗布膜１８が電波をシ
ールドする金属ケースの役割をはたしており、これによ
り図１に示したような金属ケースを装着する工程を削減
できる。Embodiment 4 Next, a fourth embodiment of the high-frequency integrated circuit device of the present invention will be described with reference to the drawings. FIG. 5 is a sectional view of a high-frequency integrated circuit device according to a fourth embodiment of the present invention. In FIG. 5, reference numeral 18 denotes a metal coating film. The feature of this structure is that the protective coating material 16 is formed to a thickness of 0.5 mm or more, the surface is flattened, and the metal coating film 18 is formed thereon. The metal coating film 18 serves as a metal case that shields radio waves, so that the step of mounting the metal case as shown in FIG. 1 can be reduced.
【００３２】（実施の形態５） 図６は本発明の高周波集積回路装置の第五の実施の形態
における断面図である。(Embodiment 5) FIG. 6 is a sectional view of a high-frequency integrated circuit device according to a fifth embodiment of the present invention.
【００３３】図６において１９は半導体チップ１をフリ
ップチップボンディングにするためのバンプである。こ
の構造の特徴は、凹部１２を１段階の凹部にし、配線層
が形成された凹部底面１３に半導体チップ１がバンプ１
９により、フリップチップ実装されていることである。
本構造により、ワイヤーボンディングの工程を削減でき
ると同時に、凹部１２の占める面積を小さくすることが
でき、実装密度をワイヤーボンディングするときよりも
さらに高くすることができる。また、この構造によれ
ば、周波数が１．５ＧHz以上において、ポッティング樹
脂を用いる必要がないためポッティング樹脂による損失
や、ワイヤーが無いためソースワイヤーのインダクタン
スによる利得低下を回避できる。また、半導体チップ１
の素子が形成されている面を凹部底面側に接続するた
め、バンプ１９の接続面積を半導体チップ１の面積の１
５％以上に大きくとることにより、ワイヤーボンディン
グ方式よりも半導体チップ１の厚み分の熱抵抗を回避で
き、良好な放熱性を得ることができる。In FIG. 6, reference numeral 19 denotes bumps for flip chip bonding the semiconductor chip 1. The feature of this structure is that the recess 12 is formed as a one-step recess, and the semiconductor chip 1 is provided on the bottom 13 of the recess where the wiring layer is formed.
9 means that the chip is flip-chip mounted.
With this structure, the number of steps of wire bonding can be reduced, and at the same time, the area occupied by the concave portion 12 can be reduced, and the mounting density can be further increased as compared with the case of wire bonding. Further, according to this structure, when the frequency is 1.5 GHz or more, it is not necessary to use a potting resin, so that a loss due to the potting resin and a decrease in gain due to the inductance of the source wire can be avoided because there is no wire. In addition, the semiconductor chip 1
In order to connect the surface on which the element is formed to the bottom surface side of the concave portion, the connection area of the bump 19 is set to one of the area of the semiconductor chip 1.
By setting it as large as 5% or more, the thermal resistance corresponding to the thickness of the semiconductor chip 1 can be avoided as compared with the wire bonding method, and good heat dissipation can be obtained.
【００３４】（実施の形態６） 図７は本発明の高周波集積回路装置の第六の実施の形態
における断面図である。(Embodiment 6) FIG. 7 is a sectional view of a high-frequency integrated circuit device according to a sixth embodiment of the present invention.
【００３５】図７は図６の構成と同様に、フリップチッ
プ実装を行なっているがこの構造の特徴は、凹部１２が
チップ部品３が配置されたセラミック多層基板２の表面
とは反対側の裏面側に形成され、凹部１２内に半導体チ
ップ１が配置された構成としたものである。これによっ
て実装密度をさらに高めることができる。さらに、この
場合においては凹部１２の深さと半導体チップ１の厚み
を同じにすることにより機器の基板３０への実装時、半
導体チップ１から直接機器の基板３０へ放熱することが
可能となる。これによってセラミック多層基板２の材質
が通常のアルミナ等の物質でも良好な放熱性を確保する
ことができる。FIG. 7 shows a flip chip mounting similar to the configuration of FIG. 6, but the feature of this structure is that the concave portion 12 has a rear surface opposite to the front surface of the ceramic multilayer substrate 2 on which the chip components 3 are arranged. The semiconductor chip 1 is formed on the side, and the semiconductor chip 1 is arranged in the recess 12. Thereby, the mounting density can be further increased. Further, in this case, by making the depth of the concave portion 12 and the thickness of the semiconductor chip 1 the same, it is possible to radiate heat from the semiconductor chip 1 directly to the substrate 30 of the device when the device is mounted on the substrate 30. Thus, good heat dissipation can be ensured even when the material of the ceramic multilayer substrate 2 is a material such as ordinary alumina.
【００３６】[0036]
【発明の効果】本発明による高周波集積回路装置は低抵
抗のバイアス用フィルター回路が内層（もしくは表層）
に設けられ、高周波整合回路が表層（もしくは内層）に
設けられた多層基板による立体的回路構成をとってお
り、実装密度を高くすることができる。また、本発明は
凹部を有する多層基板を用い、半導体チップを凹部中に
配置することにより、チップ部品を多層基板に実装する
際、平面の半田マスクを用いてクリーム半田の塗布が可
能となり、半導体チップとチップ部品の間隔を短縮する
ことができ、実装密度を向上させることができる。この
結果、従来の単層の基板を用いた高周波集積回路装置と
比較して、その体積は１／２以下にできる。また、半導
体チップを凹部底面に配置することにより半導体チップ
を搭載した基板厚を薄くすることができるので熱抵抗が
低減でき、大消費電力の電力増幅回路ができる。また多
層基板を熱伝導率の高いセラミックを用いることにより
大電力の半導体装置が形成できる。また多層基板として
ＰＰＯ基板を用いることにより伝送損失を少なくし利得
等の物性を向上させることができる。また多層基板とし
て高温焼成のセラミックと低温焼成のガラスセラミック
を用いることによりコストの低減を図ることができる。
また、凹部底面に位置する多層基板の裏面に放熱用電極
を設けることにより、実装する機器の基板と大面積で半
田付けでき放熱効果をさらに高めることができる。ま
た、２００μｍ以上の幅を有し、０．４Ω以下の抵抗を
有するバイアス回路に用いるフィルター回路を表層また
は内層に構成でき、実装密度を単層平板の基板を用いた
場合に比べて２倍以上にできる。また、ワイヤーボンデ
ィングは凹部中間面と半導体チップの間で行われるので
高低差を少なくすることができるため、表面を平坦化す
ることができる。また、フリップチップボンディングを
行うことにより、ワイヤーボンディング工程等の工程を
削減できるとともに実装密度を向上させることができ
る。セラミック多層配線基板上に搭載されたチップ部品
上に保護コートを行うことにより、当該高周波集積回路
装置を半田リフローにより機器の基板に実装してもチッ
プ部品の半田溶融による位置ずれが起こらず、高周波特
性の変化を防止することができる。さらに、保護コート
された表面上に金属塗布膜を形成することにより、シー
ルドケース装着の工程を不要とすることができる。In the high frequency integrated circuit device according to the present invention, the low-resistance bias filter circuit has an inner layer (or a surface layer).
And a high-frequency matching circuit has a three-dimensional circuit configuration using a multilayer substrate provided on a surface layer (or an inner layer), so that the mounting density can be increased. In addition, the present invention uses a multilayer substrate having a concave portion and arranges the semiconductor chip in the concave portion, so that when a chip component is mounted on the multilayer substrate, it becomes possible to apply cream solder using a flat solder mask, The distance between the chip and the chip component can be reduced, and the mounting density can be improved. As a result, the volume can be reduced to half or less as compared with a conventional high frequency integrated circuit device using a single-layer substrate. Further, by arranging the semiconductor chip on the bottom surface of the concave portion, the thickness of the substrate on which the semiconductor chip is mounted can be reduced, so that the thermal resistance can be reduced, and a power amplifier circuit with large power consumption can be realized. In addition, a high-power semiconductor device can be formed by using a ceramic having high thermal conductivity for the multilayer substrate. Further, by using a PPO substrate as a multilayer substrate, it is possible to reduce transmission loss and improve physical properties such as gain. The cost can be reduced by using a high-temperature fired ceramic and a low-temperature fired glass ceramic as the multilayer substrate.
Further, by providing the heat radiation electrode on the back surface of the multilayer substrate located at the bottom surface of the concave portion, the heat radiation effect can be further enhanced by soldering with a large area to the substrate of the device to be mounted. In addition, a filter circuit having a width of 200 μm or more and used for a bias circuit having a resistance of 0.4 Ω or less can be configured on the surface layer or the inner layer, and the mounting density is twice or more as compared with the case where a single-layer flat board is used. Can be. In addition, since the wire bonding is performed between the intermediate surface of the concave portion and the semiconductor chip, the difference in height can be reduced, so that the surface can be flattened. Further, by performing flip chip bonding, it is possible to reduce the number of steps such as a wire bonding step and to improve the mounting density. By performing a protective coating on the chip components mounted on the ceramic multilayer wiring board, even if the high-frequency integrated circuit device is mounted on the board of the device by solder reflow, the misalignment due to the melting of the chip components by the solder does not occur. Changes in characteristics can be prevented. Further, by forming a metal coating film on the surface coated with the protective coating, the step of mounting the shield case can be made unnecessary.
【００３７】また、本発明の高周波集積回路装置の製造
方法によれば、半導体チップとチップ部品の装着を前後
どちらにしても、あとの部品を装着したときに、先に装
着した部品が半田溶融により位置ずれをおこすことな
く、高周波特性の変化を防止することができる。Further, according to the method of manufacturing a high frequency integrated circuit device of the present invention, regardless of whether the semiconductor chip and the chip component are mounted before or after, when the subsequent component is mounted, the previously mounted component is melted by solder. Accordingly, it is possible to prevent a change in high-frequency characteristics without causing a position shift.
【図１】本発明の第一の実施の形態における高周波集積
回路装置の構成を示す断面図FIG. 1 is a sectional view showing a configuration of a high-frequency integrated circuit device according to a first embodiment of the present invention.
【図２】本発明の第一の実施の形態における高周波集積
回路装置の概略の等価回路図FIG. 2 is a schematic equivalent circuit diagram of the high-frequency integrated circuit device according to the first embodiment of the present invention.
【図３】本発明の第二の実施の形態における高周波集積
回路装置の構成を示す断面図FIG. 3 is a sectional view showing a configuration of a high-frequency integrated circuit device according to a second embodiment of the present invention.
【図４】本発明の第三の実施の形態における高周波集積
回路装置の構成を示す断面図FIG. 4 is a sectional view showing a configuration of a high-frequency integrated circuit device according to a third embodiment of the present invention.
【図５】本発明の第四の実施の形態における高周波集積
回路装置の構成を示す断面図FIG. 5 is a sectional view showing a configuration of a high-frequency integrated circuit device according to a fourth embodiment of the present invention.
【図６】本発明の第五の実施の形態における高周波集積
回路装置の構成を示す断面図FIG. 6 is a sectional view showing a configuration of a high-frequency integrated circuit device according to a fifth embodiment of the present invention.
【図７】本発明の第六の実施の形態における高周波集積
回路装置の構成を示す断面図FIG. 7 is a sectional view showing a configuration of a high-frequency integrated circuit device according to a sixth embodiment of the present invention.
【図８】従来の第一の高周波集積回路装置の構成例を示
す斜視図FIG. 8 is a perspective view showing a configuration example of a first conventional high-frequency integrated circuit device.
【図９】従来の第二の高周波集積回路装置の構成例を示
す断面図FIG. 9 is a sectional view showing a configuration example of a second conventional high-frequency integrated circuit device.
【図１０】従来の第二の高周波集積回路装置のクリーム
半田の塗布工程を示す断面図FIG. 10 is a sectional view showing a step of applying cream solder of a second conventional high-frequency integrated circuit device.
１ 半導体チップ ２ セラミック多層基板 ２ａ ＰＰＯ多層基板 ２ｂ セラミック基板 ２ｃ ガラスセラミック多層基板 ３ チップ部品 ４ 端面電極 ５ 高融点半田材 ６ 低融点半田材 ７ ポッティング樹脂 ８ ボンディングワイヤー ９ 半田マスク １０ スキージ １１ エンボス部 １２ 凹部 １３ 凹部底面 １４ 凹部中間面 １５ 放熱用電極 １６ 保護コート材 １７ 金属ケース １８ 金属塗布膜 １９ バンプ ２０ ＦＥＴ ２１ ドレインバイアス回路 ２２ 高周波整合回路 ２３ ゲートバイアス回路 ２４ 半導体デバイス ２５ 単層基板 ２６ 放熱板 ２７ 電極リード ２８ 半導体デバイス搭載穴 ２９ バイアス回路 ３０ 機器の基板 ３１ 貫通孔 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Ceramic multilayer substrate 2a PPO multilayer substrate 2b Ceramic substrate 2c Glass ceramic multilayer substrate 3 Chip component 4 End surface electrode 5 High melting point solder material 6 Low melting point soldering material 7 Potting resin 8 Bonding wire 9 Solder mask 10 Squeegee 11 Embossed part 12 Concave portion 13 Concave bottom surface 14 Concave intermediate surface 15 Heat radiation electrode 16 Protective coating material 17 Metal case 18 Metal coating film 19 Bump 20 FET 21 Drain bias circuit 22 High frequency matching circuit 23 Gate bias circuit 24 Semiconductor device 25 Single layer substrate 26 Heat radiating plate 27 Electrode lead 28 Semiconductor device mounting hole 29 Bias circuit 30 Equipment substrate 31 Through hole
───────────────────────────────────────────────────── フロントページの続き (72)発明者 立岡 一樹 大阪府高槻市幸町１番１号 松下電子工 業株式会社内 (56)参考文献 特開 平５−95236（ＪＰ，Ａ) 特開 平５−167218（ＪＰ，Ａ) 特開 昭60−10647（ＪＰ，Ａ) 特開 平２−5448（ＪＰ，Ａ) 特開 平７−22755（ＪＰ，Ａ) 特開 平６−349969（ＪＰ，Ａ) 特開 平７−22541（ＪＰ，Ａ) 特開 平６−236815（ＪＰ，Ａ) 特開 平７−46007（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 25/00 H05K 1/18 H05K 3/46 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuki Tateoka 1-1, Sachimachi, Takatsuki-shi, Osaka Prefecture Matsushita Electronics Corporation (56) References JP-A-5-95236 (JP, A) JP-A Heisei 5-167218 (JP, A) JP-A-60-10647 (JP, A) JP-A-2-5448 (JP, A) JP-A-7-22755 (JP, A) JP-A-6-349969 (JP, A A) JP-A-7-22541 (JP, A) JP-A-6-236815 (JP, A) JP-A-7-46007 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) ) H01L 23/12 H01L 25/00 H05K 1/18 H05K 3/46
Claims (1)
効果トランジスタと、ドレインバイアス回路と、高周波
整合回路と、ゲートバアス回路とを備えた高周波集積回
路装置であって、 前記多層基板は、表面に凹部を有し、該凹部中には前記
電界効果トランジスタからなる半導体チップが搭載さ
れ、かつ、前記凹部以外の部分の前記表層には前記整合
回路をなすマイクロストリップラインとチップ部品とが
搭載されており、 前記ドレインバイアス回路に用いるフィルタ回路は、前
記多層基板の前記内層に設けられ、かつ、２００μｍ以
上の幅を有する配線パターンからなる ことを特徴とする
高周波集積回路装置。A multilayer substrate comprising a surface layer and an inner layer;
Effect transistor, drain bias circuit, high frequency
High frequency integrated circuit with matching circuit and gate bias circuit
A road device, wherein the multilayer substrate has a concave portion on a surface, and the concave portion is provided in the concave portion.
A semiconductor chip consisting of a field effect transistor is mounted
And the surface layer other than the concave portion is aligned with the surface layer.
The microstrip line and the chip components that make up the circuit
And a filter circuit used for the drain bias circuit,
Provided in the inner layer of the multi-layer substrate and having a thickness of 200 μm or less.
A high-frequency integrated circuit device comprising a wiring pattern having an upper width .
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06236896A JP3235452B2 (en) | 1995-03-20 | 1996-03-19 | High frequency integrated circuit device |
| US08/638,264 US5796165A (en) | 1996-03-19 | 1996-04-26 | High-frequency integrated circuit device having a multilayer structure |
| KR1019960013253A KR100367936B1 (en) | 1996-03-19 | 1996-04-27 | High frequency integrated circuit device with laminated body |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6076095 | 1995-03-20 | ||
| JP7-60760 | 1995-03-20 | ||
| JP06236896A JP3235452B2 (en) | 1995-03-20 | 1996-03-19 | High frequency integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08321567A JPH08321567A (en) | 1996-12-03 |
| JP3235452B2 true JP3235452B2 (en) | 2001-12-04 |
Family
ID=26401816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06236896A Expired - Fee Related JP3235452B2 (en) | 1995-03-20 | 1996-03-19 | High frequency integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3235452B2 (en) |
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|---|---|
| JPH08321567A (en) | 1996-12-03 |
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