JP3235062B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of embedding a metal electrode in an opening reaching a copper wiring.

[0002]

2. Description of the Related Art Conventionally, LSIs formed on a semiconductor substrate
Aluminum has been mainly used as a wiring material of recent years. However, in recent years, for higher integration and higher speed of semiconductor integrated circuits, copper having lower resistance and higher electromigration (EM) resistance than aluminum has been used. It is attracting attention as a next-generation wiring material. Copper is being studied for filling a groove having a wiring pattern formed in an interlayer insulating film and forming a copper wiring by a chemical mechanical polishing (CMP) method (Japanese Patent Laid-Open No. 11-1691).
No. 2).

[0003] This method of forming a buried copper wiring will be described with reference to FIGS. 11 to 14 are process cross-sectional views of a semiconductor device showing a simplified method of manufacturing a semiconductor device according to an embodiment according to a conventional technique.
In FIG. 14, reference numeral 100 denotes a semiconductor substrate and 101 denotes a first substrate.
Silicon oxide film, 102 is a copper wiring, 103 is a copper wiring 1
Tantalum nitride which functions as a barrier metal on side and bottom surfaces of 02, 104 is a silicon nitride film which functions as a barrier layer on the upper surface of the copper wiring 102, 105 is a second silicon oxide film, and 106 is formed on the silicon oxide film 105 Opening 107, resist; 108, copper oxide formed on the bottom of opening 106; 109, clean copper surface;
Is a titanium nitride / titanium laminated film, 111 is a tungsten film, 112 is a cavity formed in a tungsten electrode, 1
13 is a tungsten electrode, 116 is a second silicon nitride film, 117 is a third silicon oxide film, 118 is a wiring groove,
119 is a second tantalum nitride film, 120 is a seed copper film, 12
1 is an electrolytic plating copper film.

As shown in FIG. 11A, a copper wiring 10 is formed by using a conventional lithography and dry etching technique.
An opening 106 is formed to reach 2.

[0005] Since copper is very easily oxidized, FIG.
As shown in (b), even after the removal and cleaning of the resist, a copper oxide 108 is formed on the surface of the copper wiring 102 on the bottom surface of the opening 106. Since copper oxide is a high-resistance body, if a metal electrode is formed inside the opening 106 while the copper oxide 108 remains on the bottom surface of the opening 106, variation in resistance and poor conduction are caused. Therefore,
The copper oxide 108 is reduced by a heat treatment at about 350 ° C. or a plasma treatment in a hydrogen atmosphere or an ammonia atmosphere to obtain a clean copper surface 109 (FIG. 11C). Subsequently, a titanium nitride / titanium film 110 is deposited by sputtering without being exposed to the atmosphere (FIG. 12D).

Next, as shown in FIG. 12E, tungsten 111 is deposited on the titanium nitride / titanium laminated film 110 including the inside of the opening by chemical vapor deposition. next,
The tungsten film 111 and the titanium nitride film / titanium laminated film 110 on the surface are removed by a chemical mechanical polishing method, and a tungsten plug electrode 113 is formed in the opening (FIG. 12).
(F)).

Next, as shown in FIG. 13G, a second silicon nitride film 116 and a third silicon oxide film 117 are formed.
Is deposited, a wiring groove 118 is formed using a conventional lithography technique and a dry etching technique. Next, as shown in FIG. 13H, a second tantalum nitride film 119 and a seed copper film 120 are deposited by a sputtering method, and the wiring groove 118 is filled with copper 121 by an electrolytic plating method.

Next, as shown in FIG. 13I, the second tantalum nitride film 11 other than the groove is formed by a chemical mechanical polishing method.
9. The seed copper film 120 and the electrolytic plated copper 121 are removed to form a copper wiring.

[0009]

However, in the above conventional example, after the barrier metal is deposited, the barrier metal has an overhanging shape as shown in part C of FIG. When the tungsten is deposited by the phase growth method, a cavity 112 (FIG. 12E) is formed, and this cavity 112 is known to adversely affect the reliability of the tungsten electrode 113 and the reliability of the wiring formed thereon. I have.

When the lower wiring forming the opening is an aluminum wiring, the aluminum oxide formed at the bottom of the opening is removed by irradiating the substrate with a plasma of an inert gas such as argon. Since the etching was performed by physical etching, the corner of the entrance of the opening was removed as shown in FIG. 14B by this etching, and even after the barrier metal was deposited, the overhang shape as shown in the C part of FIG. Did not become.

However, in the case of copper wiring, if the copper oxide is removed by physical etching in the same manner as in the case of aluminum wiring, the corner of the entrance of the opening can be removed, but at the same time the bottom of the hole removed is removed. Copper 114
Adhere to the side wall of the opening (FIG. 14B), and the copper atoms 115 adhered to the silicon oxide film by the subsequent heat treatment process and the electric field during the operation of the LSI are diffused into the silicon oxide film, and the leakage current between the wires and the device characteristics There was a problem of causing deterioration.

The effect of the overhang of the barrier metal does not cause much problem in an opening having a large diameter (for example, when the diameter exceeds 0.3 μm). However, when the size of the opening becomes 0.3 μm or less. It begins to appear noticeably.

SUMMARY OF THE INVENTION The present invention has been made in view of these inconveniences. It is an object of the present invention to form an opening in a copper wiring by chamfering the entrance of the opening and at the same time to form copper on the side wall of the opening. It is an object of the present invention to provide a semiconductor device provided with a metal electrode having a small amount of adverse effects on device characteristics and having no voids, and a method of manufacturing the same.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device comprising a first wiring having copper or copper as a main component (hereinafter simply referred to as a "copper wiring"). ], Forming an insulating film covering the first wiring, and forming an opening in the insulating film on the first wiring. a step of forming a formed and forming so that at least the portion of the insulating film is left on the bottom of the opening, an inclined portion to the upper end of the opening, the opening area of the upper end of the opening After forming a slope at the upper end of the opening, a groove for forming a wiring is formed in the uppermost layer of the insulating film, and a space between the groove for the wiring and the opening is confirmed.
And forming while retaining, and removing the insulating film left on the bottom of the opening, by filling a conductive member in said opening and said groove, and forming a second wiring . The wiring groove formed here may be used as a wiring or may not be formed as a wiring, but may be formed because it is required in a subsequent step.

The reason why the insulating film is left is to prevent copper at the bottom of the opening from adhering to the side wall of the opening when the opening is chamfered, and the insulating film left during the physical etching is formed. May be a single type of insulating film or two or more types of insulating films as long as all of them are not etched.

After the copper wiring is exposed, heat treatment, plasma treatment, or ultraviolet irradiation treatment (hereinafter simply referred to as "heat treatment etc.") is performed on the copper wiring surface in a reducing atmosphere after the copper wiring is exposed in order to reduce resistance variation and conduction failure. And the like, a step of reducing the copper oxide formed on the surface of the copper wiring at the bottom of the opening may be included.

With such a structure, the barrier metal at the entrance of the opening is not formed with an overhanging shape while preventing copper from adhering to the side wall of the opening, and the metal electrode having no cavity in the opening is embedded with the metal electrode. Wiring and can be formed
At the same time, the formation of the wiring groove pattern is
The wiring groove is cut after performing
So that the grooved wiring is not
A sufficient space with the opening can be obtained.

[0018]

[0019]

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 and 2 are process sectional views showing a method for forming a metal wiring according to an embodiment of the present invention.

In FIGS. 1 and 2, reference numeral 1 denotes a semiconductor substrate on which LSI components (not shown) such as a transistor element, a capacitor element, and metal wiring are formed, and 2 denotes a first substrate functioning as an interlayer insulating film. Silicon oxide film, 3 is copper wiring, 4
Is a tantalum nitride film for preventing copper diffusion, 5 is a silicon nitride film, 6 is a second silicon oxide film, 7 is a first resist for forming an opening, and 8 is a first resist 7. An opening 9 opened as a mask, 9 is an opening entrance opened by etching by irradiation with argon plasma, 10
Is a copper oxide, 11 is a clean copper surface, 12 is a laminated film of titanium nitride and titanium functioning as an adhesion layer, 13 is a tungsten film, and 14 is a tungsten electrode formed in the opening.

First, as shown in FIG.
The second silicon oxide film 6 is etched using the first resist 7 for forming the opening 8 reaching the surface. At this time, the silicon nitride film 5 is left without being etched as shown in FIG. Next, as shown in FIG. 1B, the entrance of the opening 8 is widened by removing the first resist 7 and etching the surface of the second silicon oxide film 6 by physical etching. Here, the physical etching means, for example, irradiation with argon plasma (argon reverse sputtering) and the like, and the etching amount needs to be changed depending on the film formation method and the film thickness of the barrier metal. The thickness is about 30 nm. In the case of such physical etching, since the etching rate of the corner portion is higher than that of the flat portion, an inclined portion is formed in the opening as shown in FIG. 1B, and the entrance 9 of the opening is widened. Can be done.

Next, as shown in FIG. 1C, the silicon nitride film 5 remaining at the bottom of the opening 8 is removed by reactive ion etching to expose the copper wiring 3, but a subsequent cleaning process is performed. The copper surface at the bottom of the opening 8 is also exposed to the atmosphere by exposure to copper oxide.
Is formed. Therefore, the copper oxide 10 is reduced by performing a heat treatment or the like in a reducing atmosphere, and the clean copper surface 1 is reduced.
1 (FIG. 2D). Subsequently, a laminated film 12 of titanium nitride / titanium as a barrier metal is deposited using a sputtering method without being exposed to the atmosphere, and a tungsten film 13 is deposited by a chemical vapor deposition method (FIG. 2E).

Finally, as shown in FIG. 2 (f), the tungsten film 13 and the titanium nitride / titanium laminated film 12 other than the opening are polished and removed by a chemical mechanical polishing method.
Is formed.

According to the above method, since the surface of the copper wiring is not exposed at the time of physical etching, the entrance of the opening can be widened without contaminating the side wall of the hole with copper. Since the overhang is eliminated (part A in FIG. 2E), it is possible to prevent the generation of a cavity when tungsten is buried.

In the method shown in the present embodiment, the diameter at which the overhang shape becomes a problem in the conventional method is about 0.3 mm.
This is particularly effective when a fine opening of 3 μm or less is formed.

(Embodiment 2) FIGS. 3 and 4 are process cross-sectional views of a semiconductor device showing a simplified method of forming a metal wiring according to another embodiment of the present invention.

First, as shown in FIG. 3A, a case is considered in which an opening 8 is formed to reach the copper wiring 3 covered with titanium nitride 12 (TiN) as a lower layer and a silicon nitride film as an upper layer. Also in this case, the second silicon oxide film 6 is etched using the first resist 7 as in the first embodiment.
Here, TiN is for securing the adhesion to the first silicon oxide film, and when the adhesion between the copper wiring 3 and the underlying film can be secured and the reliability and the like can be sufficiently secured, this TiN is used.
No N film is required. The material may not be TiN as long as the material can ensure the adhesion between copper and the underlying layer (the silicon oxide film 2 in the present embodiment). For example, Ta, Ta
N, W, WN, TaSiN, TiSiN, and the like.

The silicon nitride film 5 functions as a mask for forming the copper wiring 3 by dry etching. If the silicon nitride film 5 can ensure a sufficient selectivity with copper at the time of dry etching, The film need not be a silicon nitride film. For example, Ta, TaN, W, WN, TaSi
N, TiSiN, and the like.

When the opening 8 is formed by dry etching, the silicon nitride film 5 is left without being etched as shown in FIG. Next, as shown in FIG. 3B, the entrance of the opening 8 is widened by removing the first resist 7 and etching the surface of the second silicon oxide film 6 by physical etching. The physical etching here means, for example, irradiation with argon plasma (argon reverse sputtering) or the like as in the case of Embodiment 1, and the etching amount needs to be changed depending on the film formation method and film thickness of the barrier metal. The thickness is approximately 5 to 30 nm in terms of a thermal oxide film. In the case of physical etching, the partial etching rate of the corner is higher than that of the flat part, and the entrance 9 of the opening can be widened as shown in FIG.

Next, as shown in FIG. 3 (c), the silicon nitride film 5 at the bottom of the opening 8 is etched away by reactive ion etching or the like to expose the copper wiring 3, but after the subsequent cleaning processing, In this case, the copper oxide 10 is formed on the copper surface at the bottom of the opening 8 by exposure to the atmosphere. Therefore, the copper oxide 10 is reduced by performing a heat treatment in a reducing atmosphere or the like to obtain a clean copper surface 11 (FIG. 4D). Subsequently, as shown in FIG. 4E, after the titanium nitride / titanium laminated film 12 as a barrier metal is deposited by sputtering without being exposed to the air, the copper film 20 is deposited by chemical vapor deposition. accumulate.

Subsequently, a second silicon nitride film 21 is deposited. After the deposition of the copper film 20, if the film is exposed to the atmosphere or is placed in an atmosphere in which a copper oxide film is formed on the surface, the second silicon nitride film 21 is deposited. Before depositing the second silicon nitride film, the surface oxide film may be removed by heat treatment in a reducing atmosphere or the like, and then a second silicon nitride film may be deposited. By doing so, the adhesion between copper and the second silicon nitride film is further improved.

Next, the second silicon nitride film is etched into a desired wiring pattern by conventional lithography and dry etching. Next, copper is etched using the silicon nitride film having the wiring pattern as a mask material (FIG. 4F).

According to the above method, since the surface of the copper wiring is not exposed at the time of physical etching, the entrance of the opening can be widened without contaminating the side wall of the hole with copper. Since the overhang is eliminated (part E in FIG. 4E), it is possible to prevent the occurrence of a cavity when copper is embedded.

(Embodiment 3) FIGS. 8 and 9 show an example of a sectional view of a semiconductor device according to another embodiment of the present invention. Copper wiring 3 is formed in first silicon oxide film 2 on semiconductor substrate 1. Opening 8 reaching copper wiring 3
The wiring groove 16 has a tantalum nitride film 17 and a seed copper film 18.
And electrolytic plated copper 19 is embedded. The tantalum nitride film is formed to prevent the diffusion of the seed copper film 18 and the electroplated copper 19, and other conductive films such as a tantalum film, a titanium nitride film, A tungsten nitride film or the like may be used.

The feature of this embodiment is that the entrance of the opening 8 is inclined and the upper part of the opening is widened, but the entrance of the wiring groove 16 adjacent to the opening 8 has no inclination. It is almost vertical.

According to this structure, as shown in FIG. 8, even if the center line (A) of the opening coincides with the center line (A) of the wiring groove in design, the wiring When the opening is formed, misalignment may occur. According to the present embodiment, as described above, the entrance of the opening is inclined, but the entrance of the wiring groove is formed almost vertically without inclination. For example, as shown in FIG. Even if the misalignment occurs with respect to the opening 8 formed earlier when the wiring groove 16 is formed, a sufficient space (f) between the wiring and the opening can be ensured, and a short circuit failure may occur. Absent.

The method of manufacturing the above semiconductor device is shown in FIGS.
This will be described with reference to FIG. FIG. 5 is a process sectional view of a semiconductor device showing a simplified method of manufacturing a semiconductor device according to a third embodiment. In FIGS. 5 to 7, reference numeral 15 denotes a second resist for forming a wiring groove; Reference numeral 16 denotes a wiring groove having a wiring pattern, 17 denotes a second tantalum nitride film, 18 denotes copper used as a seed during electrolytic copper plating, and 19 denotes copper formed by electrolytic plating. 5 and FIG. 7, FIG.
The same or corresponding parts are denoted by the same reference numerals.

First, as shown in FIG. 5A, the second silicon oxide film 6 is etched using a first resist 7 for forming an opening 8 reaching the copper wiring 3. At this time, as shown in the figure, the silicon nitride film 5 is left without being etched. Next, as shown in FIG. 5B, the first resist 7 is removed, and the surface of the second silicon oxide film 6 is etched by physical etching to form the opening 8.
Widen the entrance 9 of. The physical etching here means, for example, irradiation with argon plasma (argon reverse sputtering) or the like as in the case of Embodiment 1, and the etching amount needs to be changed depending on the film formation method and film thickness of the barrier metal. The thickness is approximately 5 to 30 nm in terms of a thermal oxide film.

Next, as shown in FIG. 5C, a second resist 15 having a desired wiring groove pattern is formed. Here, the resist for forming the wiring groove does not function as a wiring, but may include a pattern for forming a concave portion required in a subsequent step.

Next, as shown in FIG. 6D, the second silicon oxide film 6 is etched to a desired thickness, and the second resist 15 is removed. Thus, the opening 8 and the wiring groove 16 are formed in the second silicon oxide film 6. At this time, the corner of the entrance of the opening (portion B in FIG. 6D) that overlaps with the wiring groove 16 is also dropped, so that no overhang occurs when depositing a barrier metal and a seed copper film serving as a seed ( FIG. 7 (g)).

Next, the silicon nitride film 5 at the bottom of the opening 8 is etched away by reactive ion etching or the like to expose the copper wiring 3. Even after the subsequent cleaning treatment, the opening is exposed to the atmosphere. Copper oxide 10 is formed on the bottom copper surface (FIG. 6E). Next, the copper oxide 1 is subjected to heat treatment in a reducing atmosphere or the like.
0 is reduced to obtain a clean copper surface 11 (FIG. 6 (f)).

Subsequently, the tantalum nitride film 17 as a barrier metal is formed by sputtering without being exposed to the atmosphere.
Then, a seed copper film 18 serving as a seed for electrolytic plating is deposited, and copper 19 is deposited on the seed copper film 18 including the openings 8 and the wiring grooves 16 by an electrolytic plating method (FIG. 7G). Finally, as shown in FIG. 7H, the copper 19, the seed copper film 18 and the tantalum nitride film 17 other than the opening 8 and the wiring groove 16 are removed by a chemical mechanical polishing method, so that the lower copper wiring 3 is formed.
The electrode and the copper wiring to be connected to are formed at the same time.

According to the above method, since the surface of the copper wiring is not exposed at the time of physical etching, the entrance of the opening can be widened without contaminating the side wall of the hole with copper. The effect of overhang after film deposition is eliminated, and the generation of cavities when copper electrolytic plating is embedded can be prevented. Further, by performing physical etching after opening the opening and before forming the wiring groove, a space (E) between the wirings or a space (E) between the wirings as shown in FIG. F) can be taken sufficiently.

When this method is used, even when misalignment (g) occurs with respect to the opening at the time of wiring patterning, the space (f) between the wiring and the opening is reduced as shown in FIG. Short-circuit failure does not occur because it is sufficiently secured.

On the other hand, unlike the present embodiment, if physical etching is performed after the opening and the wiring groove are formed, FIG.
As shown in FIG. 0, the space (f) between the wiring and the opening is eliminated, and the corners come into contact with each other, so that a short circuit is likely to occur.

In the first to third embodiments described above, the adhesion layer is a laminated film of titanium nitride and titanium or tantalum nitride. However, the present invention is not limited to these. For example, if it is a conductive film having adhesion, diffusion preventing properties, such as tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), tungsten (W), and a nitride film and a carbide film thereof. good. Embodiment 1
2 to 3 describe the two-layer copper wiring, but the present invention can be applied to three or more wirings. Embodiment 1
In the above, a tungsten film formed by a chemical vapor deposition method and a copper film formed by an electrolytic plating method in the second embodiment have been described by way of example. However, the present invention is particularly effective when copper is used for an underlying wiring, The type of metal to be filled in the opening and the wiring groove reaching the copper wiring and the film forming method are not limited to these.

[0049]

As described above, when the semiconductor device and the method for manufacturing the same according to the present invention are used, there is no adhesion of metallic copper generated from the lower copper wiring on the side wall of the opening, and the corner of the upper part of the opening is cut off. Since it becomes possible, no cavity is formed in the step of embedding metal in the opening. Therefore, it is possible to form a metal electrode without a cavity without adversely affecting device characteristics due to diffusion of metallic copper.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a process cross-sectional view of the semiconductor device manufacturing method for explaining the first embodiment of the present invention;

FIG. 3 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a process cross-sectional view of the semiconductor device manufacturing method for explaining the third embodiment of the present invention;

FIG. 7 is a process sectional view of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a sectional view illustrating an effect of the third embodiment of the present invention.

FIG. 9 is a sectional view illustrating an effect of the third embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a problem of a conventional example.

FIG. 11 is a process sectional view of a conventional semiconductor device manufacturing method.

FIG. 12 is a process sectional view of a conventional semiconductor device manufacturing method.

FIG. 13 is a process sectional view of a conventional semiconductor device manufacturing method.

FIG. 14 is a cross-sectional view illustrating a problem of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 First silicon oxide film 3 Copper wiring 4 Tantalum nitride film 5 Silicon nitride film 6 Second silicon oxide film 7 First resist for forming an opening 8 Opening 9 Entrance of expanded opening DESCRIPTION OF SYMBOLS 10 Copper oxide 11 Clean copper surface 12 Titanium nitride / titanium laminated film 13 Tungsten film 14 Tungsten electrode 15 Second resist for forming a wiring pattern 16 Wiring groove 17 Second tantalum nitride film 18 Seed copper film 19 Electrolysis Plated copper

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (4)

(57) [Claims] A step of forming a first wiring mainly containing copper or copper on a substrate; a step of forming an insulating film covering the first wiring; and a step of forming an insulating film on the first wiring. Forming an opening in the film; forming the opening such that at least a part of the insulating film remains at the bottom of the opening; and an upper end of the opening. to form an inclined portion, and the step of extending the opening area of the upper end of the opening, after forming the inclined portion to the upper end of the opening, the uppermost layer portion of the insulating film,
A groove for forming a wiring is formed between the wiring groove and the opening.
Forming while maintaining over scan, removing the insulating film left on the bottom of the opening, by filling a conductive member in the opening and the groove, forming a second wiring A method for manufacturing a semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein said insulating film is formed by a first layer left at a bottom of said opening and a second layer forming an inclined portion at an upper end of said opening. Production method. 3. The semiconductor device according to claim 1, further comprising a step of reducing the surface of the first wiring exposed in the opening after removing the insulating film remaining on the bottom of the opening. Manufacturing method. 4. A filling a conductive member in the process as well as the groove filled with a conductive member in the opening, in the step of forming the second wiring, a refractory metal film on the inner surface of the opening and said groove and after depositing the seed copper film, method of manufacturing a semiconductor device according to any one of claims 3 to said opening and said groove from claim 1, further comprising a step of filling with copper by plating process.